Page 1 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
Page 3 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8/3067 Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series H8/3067 H8/3066 H8/3065 H8/3067RF...
Page 4 (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp.
Page 5 This manual describes the H8/3067 Group hardware. For details of the instruction set, refer to the H8/300H Series Programming Manual. Note: * F-ZTAT™ (Flexible ZTAT) is a registered trademark of Renesas Technology Corp. Rev. 4.00 Jan 26, 2006 page iii of xxii...
Page 6 Rev. 4.00 Jan 26, 2006 page iv of xxii...
Page 7 Revision (See Manual for Details)  Company name changed All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names changed to Renesas Technology Corp. Designation for categories changed from “series” to “group” Designation changed H8/3067 Series → H8/3067 Group Changes due to change in package codes FP-100A →...
Page 8 Item Page Revision (See Manual for Details) 7.4.3 Idle Mode Table amended Table 7.7 Register Function Functions in Idle Mode Activated by SCI 0 Receive-Data-Full Interrupt or by A/D Converter Other Register Conversion-End Interrupt Activation Initial Setting Operation 7.4.4 Repeat Mode Table amended Table 7.8 Register Function...
Page 9: Table Of Contents
Contents Section 1 Overview ......................Overview........................... Block Diagram ........................Pin Description........................1.3.1 Pin Arrangement ....................1.3.2 Pin Functions ....................... 10 1.3.3 Pin Assignments in Each Mode ................16 Notes on Flash Memory R Version Model ............... 21 1.4.1 Pin Arrangement ....................21 1.4.2 Differences in Flash Memory R Version .............
Page 10 2.8.4 Exception-Handling Sequences ................57 2.8.5 Bus-Released State....................58 2.8.6 Reset State......................58 2.8.7 Power-Down State ....................59 Basic Operational Timing ....................60 2.9.1 Overview......................60 2.9.2 On-Chip Memory Access Timing................ 60 2.9.3 On-Chip Supporting Module Access Timing ............61 2.9.4 Access to External Address Space ...............
Page 11 Section 5 Interrupt Controller ..................91 Overview........................... 91 5.1.1 Features........................ 91 5.1.2 Block Diagram ..................... 92 5.1.3 Pin Configuration....................93 5.1.4 Register Configuration..................93 Register Descriptions ......................94 5.2.1 System Control Register (SYSCR) ..............94 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)..........95 5.2.3 IRQ Status Register (ISR)..................
Page 12 6.2.10 Refresh Timer Counter (RTCNT)................ 141 6.2.11 Refresh Time Constant Register (RTCOR) ............142 6.2.12 Address Control Register (ADRCR) (Provided Only in Flash Memory R Version and Mask ROM Versions) .... 143 Operation .......................... 144 6.3.1 Area Division ....................... 144 6.3.2 Bus Specifications....................
Page 13 6.10 Bus Arbiter........................203 6.10.1 Operation ......................203 6.11 Register and Pin Input Timing ..................206 6.11.1 Register Write Timing ..................206 6.11.2 BREQ Pin Input Timing ..................207 Section 7 DMA Controller ....................209 Overview........................... 209 7.1.1 Features........................ 209 7.1.2 Block Diagram .....................
Page 14 7.6.2 DMAC Self-Access ..................... 263 7.6.3 Longword Access to Memory Address Registers ..........263 7.6.4 Note on Full Address Mode Setup ............... 263 7.6.5 Note on Activating DMAC by Internal Interrupts ..........264 7.6.6 NMI Interrupts and Block Transfer Mode ............265 7.6.7 Memory and I/O Address Register Values ............
Page 15 8.12 Port B ..........................317 8.12.1 Overview......................317 8.12.2 Register Descriptions ................... 319 Section 9 16-Bit Timer ....................... 327 Overview........................... 327 9.1.1 Features........................ 327 9.1.2 Block Diagrams ....................330 9.1.3 Input/Output Pins ....................333 9.1.4 Register Configuration..................334 Register Descriptions ......................336 9.2.1 Timer Start Register (TSTR)................
Page 16 10.1.2 Block Diagram ..................... 399 10.1.3 Pin Configuration....................400 10.1.4 Register Configuration..................401 10.2 Register Descriptions ......................402 10.2.1 Timer Counters (TCNT) ..................402 10.2.2 Time Constant Registers A (TCORA) ..............403 10.2.3 Time Constant Registers B (TCORB)..............404 10.2.4 Timer Control Register (TCR) ................405 10.2.5 Timer Control/Status Registers (TCSR) ..............
Page 17 11.2 Register Descriptions ......................439 11.2.1 Port A Data Direction Register (PADDR) ............439 11.2.2 Port A Data Register (PADR) ................439 11.2.3 Port B Data Direction Register (PBDDR)............440 11.2.4 Port B Data Register (PBDR) ................440 11.2.5 Next Data Register A (NDRA) ................441 11.2.6 Next Data Register B (NDRB)................
Page 18 Section 13 Serial Communication Interface ..............477 13.1 Overview........................... 477 13.1.1 Features........................ 477 13.1.2 Block Diagram ..................... 479 13.1.3 Input/Output Pins ....................480 13.1.4 Register Configuration..................481 13.2 Register Descriptions ......................482 13.2.1 Receive Shift Register (RSR) ................482 13.2.2 Receive Data Register (RDR) ................482 13.2.3 Transmit Shift Register (TSR) ................
Page 19 14.3.6 Transmitting and Receiving Data ................ 558 14.4 Usage Notes ........................566 Section 15 A/D Converter ....................569 15.1 Overview........................... 569 15.1.1 Features........................ 569 15.1.2 Block Diagram ..................... 570 15.1.3 Input Pins ......................571 15.1.4 Register Configuration..................572 15.2 Register Descriptions ......................573 15.2.1 A/D Data Registers A to D (ADDRA to ADDRD)..........
Page 20 Section 18 ROM ........................607 18.1 Overview........................... 607 18.2 Overview of Flash Memory ....................608 18.2.1 Features........................ 608 18.2.2 Block Diagram ..................... 609 18.2.3 Pin Configuration....................610 18.2.4 Register Configuration..................610 18.3 Register Descriptions ......................611 18.3.1 Flash Memory Control Register (FLMCR)............611 18.3.2 Erase Block Register (EBR) ................
Page 21 Section 19 Clock Pulse Generator .................. 665 19.1 Overview........................... 665 19.1.1 Block Diagram ..................... 666 19.2 Oscillator Circuit....................... 667 19.2.1 Connecting a Crystal Resonator................667 19.2.2 External Clock Input .................... 669 19.3 Duty Adjustment Circuit....................672 19.4 Prescalers .......................... 672 19.5 Frequency Divider ......................
Page 22 21.1.1 Absolute Maximum Ratings ................695 21.1.2 DC Characteristics ....................696 21.1.3 AC Characteristics ....................706 21.1.4 A/D Conversion Characteristics................714 21.1.5 D/A Conversion Characteristics................716 21.2 Electrical Characteristics of Flash Memory and Flash Memory R Versions ....717 21.2.1 Absolute Maximum Ratings ................717 21.2.2 DC Characteristics ....................
Page 23 C.10 Port A Block Diagrams ..................... 903 C.11 Port B Block Diagrams ..................... 906 Appendix D Pin States ...................... 914 Port States in Each Mode ....................914 Pin States at Reset ......................921 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode ......................
Page 24 Rev. 4.00 Jan 26, 2006 page xxii of xxii...
Page 25: Section 1 Overview
The H8/3067 Group is a group of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Renesas architecture. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed.
Page 26 Section 1 Overview Table 1.1 Features Feature Description Upward-compatible with the H8/300 CPU at the object-code level General-register machine • Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation • Maximum clock rate: 20 MHz •...
Page 27 Section 1 Overview Feature Description • Bus controller Address space can be partitioned into eight areas, with independent bus specifications in each area • Chip select output available for areas 0 to 7 • 8-bit access or 16-bit access selectable for each area •...
Page 28 Section 1 Overview Feature Description • 8-bit timer, 8-bit up-counter (external event count capability) 4 channels • Two time constant registers • Two channels can be connected • Programmable Maximum 16-bit pulse output, using 16-bit timer as time base timing pattern •...
Page 29 Section 1 Overview Feature Description Operating modes Seven MCU operating modes Mode Address Space A ddress Pins Initial Bus Width Max. Bus Width Mode 1 1 Mbyte to A 8 bits 16 bits Mode 2 1 Mbyte to A 16 bits 16 bits Mode 3 16 Mbytes to A...
Page 30 Section 1 Overview Feature Description Product Product Type Product Code Package lineup H8/3067 On-chip 5 VR HD64F3067RF 100-pin QFP (PRQP0100KA-A) flash HD64F3067RTE 100-pin TQFP (PTQP0100KA-A) memory HD64F3067RFP 100-pin QFP (PRQP0100JE-B) 3 VR HD64F3067RVF 100-pin QFP (PRQP0100KA-A) HD64F3067RVTE 100-pin TQFP (PTQP0100KA-A) HD64F3067RVFP 100-pin QFP (PRQP0100JE-B) On-chip...
Page 31: Block Diagram
Section 1 Overview Block Diagram Figure 1.1 shows an internal block diagram. Port 3 Port 4 Address bus P5 /A Data bus (upper) P5 /A P5 /A Data bus (lower) P5 /A EXTAL P2 /A XTAL P2 /A STBY H8/300H CPU P2 /A P2 /A FWE*/RESO...
Page 32: Pin Description
Section 1 Overview Pin Description 1.3.1 Pin Arrangement The pin arrangement of the H8/3067 Group PRQP0100KA-A and PTQP0100KA-A packages is shown in figure 1.2, and that of the PRQP0100JE-B package in figure 1.3. /IRQ /RFSH Top view /IRQ (PRQP0100KA-A, PTQP0100KA-A) /IRQ /IRQ /ADTRG...
Page 33 Section 1 Overview /IRQ /RFSH Top view /IRQ (PRQP0100JE-B) /IRQ /IRQ /ADTRG /TCLKA/TEND /TCLKB/TEND /TIOCA /TCLKC /TIOCB /TCLKD /TIOCA /TIOCB Note: * Functions as RESO in the mask ROM versions, and as FWE in the flash memory and flash memory R versions. Figure 1.3 Pin Arrangement (PRQP0100JE-B, Top View) Rev.
Page 34: Pin Functions
Section 1 Overview 1.3.2 Pin Functions Table 1.2 summarizes the pin functions. Table 1.2 Pin Functions Pin No. PRQP 0100KA-A PTQP PRQP Type Symbol 0100KA-A 0100JE-B I/O Name and Function Power 1, 35, 68 3, 37, 70 Input Power: For connection to the power supply.
Page 35 Section 1 Overview Pin No. PRQP 0100KA-A PTQP PRQP Type Symbol 0100KA-A 0100JE-B I/O Name and Function Operating 75 to 73 77 to 75 Input Mode 2 to mode 0: For setting the mode operating mode, as follows. Inputs at these control pins must not be changed during operation.
Page 36 Section 1 Overview Pin No. PRQP 0100KA-A PTQP PRQP Type Symbol 0100KA-A 0100JE-B I/O Name and Function Address to A 97 to 100, 99, 100, 1, Output Address bus: Outputs address signals 56 to 45, 2, 58 to 47, 43 to 36 45 to 38 Data bus to D...
Page 37 Section 1 Overview Pin No. PRQP 0100KA-A PTQP PRQP Type Symbol 0100KA-A 0100JE-B I/O Name and Function 16-bit TCLKD 96 to 93 98 to95 Input Clock input D to A: External clock inputs timer TCLKA TIOCA 99, 97, 95 1, 99, 97 Input/ Input capture/output compare A2 to A0: output...
Page 38 Section 1 Overview Pin No. PRQP 0100KA-A PTQP PRQP Type Symbol 0100KA-A 0100JE-B I/O Name and Function A/D and Input Power supply pin for the A/D and D/A converters. Connect to the system power converters supply when not using the A/D and D/A converters.
Page 39 Section 1 Overview Pin No. PRQP 0100KA-A PTQP PRQP Type Symbol 0100KA-A 0100JE-B I/O Name and Function I/O ports 100 to 93 2, 1, Input/ Port A: Eight input/output pins. The 100 to 95 output direction of each pin can be selected in the port A data direction register (PADDR).
Page 40: Pin Assignments In Each Mode
Section 1 Overview 1.3.3 Pin Assignments in Each Mode Table 1.3 lists the pin assignments in each mode. Table 1.3 Pin Assignments in Each Mode (PRQP0100KA-A or PTQP0100KA-A, PRQP0100JE-B) Pin No. Pin name PRQP 0100KA-A PTQP PRQP 0100KA-A 0100JE-B Mode 1 Mode 2 Mode 3 Mode 4...
Page 41 Section 1 Overview Pin No. Pin name PRQP 0100KA-A PTQP PRQP 0100KA-A 0100JE-B Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ Rev. 4.00 Jan 26, 2006 page 17 of 938 REJ09B0276-0400...
Page 42 Section 1 Overview Pin No. Pin name PRQP 0100KA-A PTQP PRQP 0100KA-A 0100JE-B Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 /WAIT /WAIT /WAIT /WAIT /WAIT /BREQ /BREQ /BREQ /BREQ /BREQ /BACK /BACK /BACK /BACK /BACK φ...
Page 43 Section 1 Overview Pin No. Pin name PRQP 0100KA-A PTQP PRQP 0100KA-A 0100JE-B Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ RFSH RFSH RFSH RFSH RFSH /IRQ /IRQ /IRQ /IRQ...
Page 44 Section 1 Overview Pin No. Pin name PRQP 0100KA-A PTQP PRQP 0100KA-A 0100JE-B Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 TIOCA TIOCA TIOCA TIOCA TIOCA TIOCA TIOCA TIOCB TIOCB TIOCB TIOCB TIOCB Notes: 1. In modes 1, 3, 5 the P4 to P4 functions of pins P4 to P4...
Page 45: Notes On Flash Memory R Version Model
Section 1 Overview Notes on Flash Memory R Version Model There are two models with on-chip flash memory in the H8/3067 Group: the flash memory version (HD64F3067) and the flash memory R version (HD64F3067R). Points to be noted when using the flash memory R version are given below.
Page 46 Section 1 Overview Rev. 4.00 Jan 26, 2006 page 22 of 938 REJ09B0276-0400...
Page 47: Section 2 Cpu
Section 2 CPU Section 2 CPU Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. 2.1.1 Features The H8/300H CPU has the following features.
Page 48: Differences From H8/300 Cpu
Section 2 CPU • High-speed operation  All frequently-used instructions execute in two to four states  Maximum clock frequency: 20 MHz  8/16/32-bit register-register add/subtract: 100 ns  8 × 8-bit register-register multiply: 700 ns  16 ÷ 8-bit register-register divide: 700 ns ...
Page 49: Cpu Operating Modes
Section 2 CPU CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. Maximum 64 kbytes, program Normal mode and data areas combined CPU operating modes Maximum 16 Mbytes, program Advanced mode...
Page 50: Address Space
Section 2 CPU Address Space Figure 2.2 shows a simple memory map for the H8/3067 Group. The H8/300H CPU can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in advanced mode. For further details see section 3.6, Memory Map in Each Operating Mode. The 1-Mbyte operating modes use 20-bit addressing.
Page 51: Register Configuration
Section 2 CPU Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers. General Registers (ERn) (SP) Control Registers (CR) 6 5 4 3 2 1 0 I UI H U N Z V C Legend Stack pointer...
Page 52: General Registers
Section 2 CPU 2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7).
Page 53: Control Registers
Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the stack. Free area SP (ER7) Stack area Figure 2.5 Stack 2.4.3 Control Registers...
Page 54: Initial Cpu Register Values
Section 2 CPU Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3—Negative Flag (N): Stores the value of the most significant bit of data, regarded as the sign bit.
Page 55: Data Formats
Section 2 CPU Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 56: Memory Data Formats
Section 2 CPU General Data Type Register Data Format Word data Word data Longword data Legend ERn: General register General register E General register R MSB: Most significant bit LSB: Least significant bit Figure 2.7 General Register Data Formats 2.5.2 Memory Data Formats Figure 2.8 shows the data formats on memory.
Page 57 Section 2 CPU Data Type Address Data Format 1-bit data Address L Byte data Address L Word data Address 2M Address 2M + 1 Address 2N Longword data Address 2N + 1 Address 2N + 2 Address 2N + 3 Figure 2.8 Memory Data Formats When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size.
Page 58: Instruction Set
Section 2 CPU Instruction Set 2.6.1 Instruction Set Overview The H8/300H CPU has 62 types of instructions, which are classified in table 2.1. Table 2.1 Instruction Classification Function Instruction Types MOV, PUSH * , POP * , MOVTPE * , MOVFPE * Data transfer Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS, EXTU...
Page 59: Instructions And Addressing Modes
Section 2 CPU 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the instructions available in the H8/300H CPU. Table 2.2 Instructions and Addressing Modes Addressing Modes (d:16, (d:24, @ERn+/ (d:8, (d:16, Function Instruction @ERn ERn) ERn) @–ERn aa:8 aa:16 aa:24 aa:8 —...
Page 60: Tables Of Instructions Classified By Function
Section 2 CPU 2.6.3 Tables of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register or address register) (EAd) Destination operand...
Page 61 Section 2 CPU Table 2.3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) → Rd MOVFPE Cannot be used in this LSI.
Page 62 Section 2 CPU Table 2.4 Arithmetic Operation Instructions Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD,SUB B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register.
Page 63 Section 2 CPU Instruction Size* Function Rd (sign extension) → Rd EXTS Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by extending the sign bit.
Page 64 Section 2 CPU Table 2.6 Shift Instructions Instruction Size* Function Rd (shift) → Rd SHAL, B/W/L SHAR Performs an arithmetic shift on general register contents. Rd (shift) → Rd SHLL, B/W/L SHLR Performs a logical shift on general register contents. Rd (rotate) →...
Page 65 Section 2 CPU Table 2.7 Bit Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
Page 66 Section 2 CPU Instruction Size* Function C ⊕ [¬ (<bit-No.> of <EAd>)] → C BIXOR Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
Page 67 Section 2 CPU Table 2.8 Branching Instructions Instruction Size Function — Branches to a specified address if address specified condition is met. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never C ∨...
Page 68 Section 2 CPU Table 2.9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling — Returns from an exception-handling routine SLEEP — Causes a transition to the power-down state (EAs) → CCR Moves the source operand contents to the condition code register. The condition code register size is one byte, but in transfer from memory, data is read by word access.
Page 69: Basic Instruction Formats
Section 2 CPU Table 2.10 Block Transfer Instruction Instruction Size Function if R4L ≠ 0 then EEPMOV.B — @ER5+ → @ER6+, R4L – 1 → R4L repeat until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W — @ER5+ →...
Page 70: Notes On Use Of Bit Manipulation Instructions
Section 2 CPU Operation field only NOP, RTS, etc. Operation field and register fields ADD.B Rn, Rm, etc. Operation field, register fields, and effective address extension MOV.B @(d:16, Rn), Rm EA (disp) Operation field, effective address extension, and condition field EA (disp) BRA d:8 Figure 2.9 Instruction Formats...
Page 71 Section 2 CPU Before Execution of BCLR Instruction Input/output Input Input Output Output Output Output Output Output Execution of BCLR Instruction BCLR #0, @P4DDR ;Clear bit 0 in data direction register After Execution of BCLR Instruction Input/output Output Output Output Output Output Output...
Page 72: Addressing Modes And Effective Address Calculation
Section 2 CPU Addressing Modes and Effective Address Calculation 2.7.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes.
Page 73 Section 2 CPU 4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register.
Page 74: Effective Address Calculation
Section 2 CPU 7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign- extended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction.
Page 75 Section 2 CPU Rev. 4.00 Jan 26, 2006 page 51 of 938 REJ09B0276-0400...
Page 76 Section 2 CPU Rev. 4.00 Jan 26, 2006 page 52 of 938 REJ09B0276-0400...
Page 77 Section 2 CPU Rev. 4.00 Jan 26, 2006 page 53 of 938 REJ09B0276-0400...
Page 78: Processing States
Section 2 CPU Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2.11 classifies the processing states.
Page 79: Program Execution State
Section 2 CPU 2.8.2 Program Execution State In this state the CPU executes program instructions in normal sequence. 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and branches to that address.
Page 80 Section 2 CPU Reset External interrupts Exception Interrupt sources Internal interrupts (from on-chip supporting modules) Trap instruction Figure 2.12 Classification of Exception Sources Bus request End of bus release Program execution state End of bus SLEEP release instruction with SSBY = 0 request Exception handling source...
Page 81: Exception-Handling Sequences
Section 2 CPU 2.8.4 Exception-Handling Sequences Reset Exception Handling: Reset exception handling has the highest priority. The reset state is entered when the RES signal goes low. Reset exception handling starts after that, when RES changes from low to high. When reset exception handling starts the CPU fetches a start address from the exception vector table and starts program execution from that address.
Page 82: Bus-Released State
Section 2 CPU SP−4 SP (ER7) SP−3 SP+1 SP−2 SP+2 SP−1 SP+3 Stack area SP (ER7) SP+4 Even address Before exception After exception Pushed on stack handling starts handling ends Legend CCR: Condition code register Stack pointer Notes: 1. PC is the address of the first instruction executed after the return from the exception-handling routine.
Page 83: Power-Down State
Section 2 CPU 2.8.7 Power-Down State In the power-down state the CPU stops operating to conserve power. There are three modes: sleep mode, software standby mode, and hardware standby mode. Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the SSBY bit is cleared to 0 in the system control register (SYSCR).
Page 84: Basic Operational Timing
Section 2 CPU Basic Operational Timing 2.9.1 Overview The H8/300H CPU operates according to the system clock (φ). The interval from one rise of the system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of two or three states.
Page 85: On-Chip Supporting Module Access Timing
Section 2 CPU φ Address bus Address RD HWR LWR High High impedance to D Figure 2.16 Pin States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide, depending on the internal I/O register being accessed.
Page 86: Access To External Address Space
Section 2 CPU φ Address bus Address RD HWR LWR High High impedance to D Figure 2.18 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings determine whether each area is accessed via an 8-bit or 16-bit bus, and whether it is accessed in two or three states.
Page 87: Section 3 Mcu Operating Modes
Section 3 MCU Operating Modes Section 3 MCU Operating Modes Overview 3.1.1 Operating Mode Selection The H8/3067 Group has seven operating modes (modes 1 to 7) that are selected by the mode pins to MD ) as indicated in table 3.1. The input at these pins determines the size of the address space and the initial bus mode.
Page 88: Register Configuration
Section 3 MCU Operating Modes Mode 5 is an externally expanded mode that enables access to external memory and peripheral devices and also enables access to the on-chip ROM. Mode 5 supports a maximum address space of 16 Mbytes. Modes 6 and 7 are single-chip modes that operate using the on-chip ROM, RAM, and registers, and makes all I/O ports available.
Page 89: Mode Control Register (Mdcr)
Section 3 MCU Operating Modes Mode Control Register (MDCR) MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3067 Group.      MDS2 MDS1 MDS0 * * * Initial value   ...
Page 90: System Control Register (Syscr)
Section 3 MCU Operating Modes System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3067 Group. SSBY STS2 STS1 STS0 NMIEG SSOE RAME Initial value Read/Write RAM enable Enables or disables on-chip RAM Software standby output port enable Selects the output state of the address bus and bus control signals in software standby mode NMI edge select...
Page 91 Section 3 MCU Operating Modes Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt. When using a crystal oscillator, set these bits so that the waiting time will be at least 7 ms at the system clock rate.
Page 92: Operating Mode Descriptions
Section 3 MCU Operating Modes Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and to CS , AS, RD, HWR, LWR, UCAS, LCAS, and RFSH) are kept as bus control signals (CS outputs or fixed high, or placed in the high-impedance state in software standby mode. Bit 1 SSOE Description...
Page 93: Mode 4
Section 3 MCU Operating Modes 16 bits. A to A are valid when 0 is written in bits 7 to 5 of the bus release control register (BRCR). (In this mode A is always used for address output.) 3.4.4 Mode 4 Ports 1, 2, and 5 and part of port A function as address pins A to A , permitting access to a...
Page 94: Pin Functions In Each Operating Mode
Section 3 MCU Operating Modes Pin Functions in Each Operating Mode The pin functions of ports 1 to 5 and port A vary depending on the operating mode. Table 3.3 indicates their functions in each operating mode. Table 3.3 Pin Functions in Each Mode Port Mode 1 Mode 2...
Page 95: Memory Map In Each Operating Mode
Section 3 MCU Operating Modes Memory Map in Each Operating Mode Figure 3.1 to 3.3 show a memory maps of the H8/3067, H8/3066, and H8/3065. The address space is divided into eight areas. The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4. The address locations of the on-chip RAM and on-chip registers differ between the 64-kbyte mode (mode 6), the 1-Mbyte modes (modes 1, 2, and 7), and the 16-Mbyte modes (modes 3, 4, and 5).
Page 96 Section 3 MCU Operating Modes Modes 1 and 2 Modes 3 and 4 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'20000 H'1FFFFF...
Page 97 Section 3 MCU Operating Modes Mode 5 Mode 6 Mode 7 (16-Mbyte expanded mode with (single-chip normal mode) (single-chip advanced mode) on-chip ROM enabled) H'000000 H'00000 H'0000 Vector area Vector area Vector area H'0000FF H'00FF H'000FF On-chip ROM On-chip ROM On-chip ROM H'007FFF H'07FFF...
Page 98 Section 3 MCU Operating Modes Modes 1 and 2 Modes 3 and 4 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'007FFF H'07FFF Area 0 Area 0 H'1FFFF H'1FFFFF H'20000...
Page 99 Section 3 MCU Operating Modes Mode 5 Mode 6 Mode 7 (16-Mbyte expanded mode with (single-chip normal mode) (single-chip advanced mode) on-chip ROM enabled) H'000000 H'0000 H'00000 Vector area Vector area Vector area H'00FF H'000FF H'0000FF On-chip ROM On-chip ROM On-chip ROM H'007FFF H'07FFF...
Page 100 Section 3 MCU Operating Modes Modes 1 and 2 Modes 3 and 4 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'20000 H'1FFFFF...
Page 101 Section 3 MCU Operating Modes Mode 5 Mode 6 Mode 7 (16-Mbyte expanded mode with (single-chip normal mode) (single-chip advanced mode) on-chip ROM enabled) H'000000 H'0000 H'00000 Vector area Vector area Vector area H'0000FF H'000FF H'00FF On-chip ROM On-chip ROM On-chip ROM H'07FFF H'007FFF...
Page 102 Section 3 MCU Operating Modes Rev. 4.00 Jan 26, 2006 page 78 of 938 REJ09B0276-0400...
Page 103: Section 4 Exception Handling
Section 4 Exception Handling Section 4 Exception Handling Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in priority order.
Page 104: Exception Vector Table
Section 4 Exception Handling 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4.1. Different vectors are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. • Reset External interrupts: NMI, IRQ to IRQ Exception •...
Page 105 Section 4 Exception Handling Table 4.2 Exception Vector Table Vector Address * Exception Source Vector Number Advanced Mode Normal Mode Reset H'0000 to H'0003 H'0000 to H'0001 Reserved for system use H'0004 to H'0007 H'0002 to H'0003 H'0008 to H'000B H'0004 to H'0005 H'000C to H'000F H'0006 to H'0007...
Page 106: Reset
Section 4 Exception Handling Reset 4.2.1 Overview A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip supporting modules.
Page 107 Section 4 Exception Handling Figure 4.2 Reset Sequence (Modes 1 and 3) Rev. 4.00 Jan 26, 2006 page 83 of 938 REJ09B0276-0400...
Page 108 Section 4 Exception Handling Internal Vector fetch processing Prefetch of first program instruction φ Address bus High to D (1), (3) Address of reset vector: (1) = H'000000, (3) = H'000002 (2), (4) Start address (contents of reset exception handling vector address) Start address First instruction of program Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Page 109: Interrupts After Reset
Section 4 Exception Handling Prefetch of Internal first program processing Vector fetch instruction φ Internal address bus Internal read signal Internal write signal Internal data bus (16 bits wide) (1) Address of reset vector (H'0000) (2) Start address (contents of reset exception handling vector address) (3) First instruction of program Figure 4.4 Reset Sequence (Mode 6) 4.2.3...
Page 110: Interrupts
Section 4 Exception Handling Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ to IRQ ), and 36 internal sources in the on-chip supporting modules. Figure 4.5 classifies the interrupt sources and indicates the number of interrupts of each type. The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), DRAM interface, 16-bit timer, 8-bit timer, DMA controller (DMAC), serial communication interface (SCI), and A/D converter.
Page 111: Trap Instruction
Section 4 Exception Handling Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1 in CCR.
Page 112: Stack Status After Exception Handling
Section 4 Exception Handling Stack Status after Exception Handling Figure 4.6 shows the stack after completion of trap instruction exception handling and interrupt exception handling. → SP–4 SP (ER7) SP–3 SP+1 SP–2 SP+2 SP–1 SP+3 SP (ER7) → Stack area SP+4 Even address Before exception handling...
Page 113: Notes On Stack Usage
Section 4 Exception Handling Notes on Stack Usage When accessing word data or longword data, the H8/3067 Group regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack pointer (SP, ER7) should always be kept even.
Page 114 Section 4 Exception Handling H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFF TRAPA instruction executed MOV. B R1L, @-ER7 SP set to H'FFFEFF Data saved above SP CCR contents lost Legend CCR: Condition code register Program counter R1L: General register R1L Stack pointer Note: The diagram illustrates modes 3 and 4.
Page 115: Section 5 Interrupt Controller
Section 5 Interrupt Controller Section 5 Interrupt Controller Overview 5.1.1 Features The interrupt controller has the following features: • Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt priority registers A and B (IPRA and IPRB).
Page 116: Block Diagram
Section 5 Interrupt Controller 5.1.2 Block Diagram Figure 5.1 shows a block diagram of the interrupt controller. ISCR IPRA, IPRB input IRQ input IRQ input section ISR Interrupt request Priority decision logic Vector number TEIE Interrupt controller SYSCR Legend ISCR: IRQ sense control register IER: IRQ enable register...
Page 117: Pin Configuration
Section 5 Interrupt Controller 5.1.3 Pin Configuration Table 5.1 lists the interrupt pins. Table 5.1 Interrupt Pins Name Abbreviation I/O Function Nonmaskable interrupt Input Nonmaskable interrupt*, rising edge or falling edge selectable to IRQ External interrupt request 5 to 0 Input Maskable interrupts, falling edge or level sensing selectable Note: * In the flash memory and flash memory R versions, NMI input is sometimes disabled.
Page 118: Register Descriptions
Section 5 Interrupt Controller Register Descriptions 5.2.1 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM. Only bits 3 and 2 are described here.
Page 119: Interrupt Priority Registers A And B (Ipra, Iprb)
Section 5 Interrupt Controller Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3 Description UI bit in CCR is used as interrupt mask bit UI bit in CCR is used as user bit (Initial value) Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.
Page 120 Section 5 Interrupt Controller Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 Initial value Read/Write Priority level A0 Selects the priority level of 16-bit timer channel 2 interrupt...
Page 121 Section 5 Interrupt Controller Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ interrupt requests. Bit 7 IPRA7 Description interrupt requests have priority level 0 (low priority) (Initial value) interrupt requests have priority level 1 (high priority) Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ interrupt requests.
Page 122 Section 5 Interrupt Controller Bit 3—Priority Level A3 (IPRA3): Selects the priority level of WDT, DRAM interface, and A/D converter interrupt requests. Bit 3 IPRA3 Description WDT, DRAM interface, and A/D converter interrupt requests have priority level 0 (low priority) (Initial value) WDT, DRAM interface, and A/D converter interrupt requests have priority level 1 (high priority)
Page 123 Section 5 Interrupt Controller Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set.   IPRB7 IPRB6 IPRB5 IPRB3 IPRB2 IPRB1 Initial value Read/Write Reserved bit Priority level B1 Selects the priority level of SCI channel 2 interrupt requests Priority level B2...
Page 124 Section 5 Interrupt Controller Bit 7—Priority Level B7 (IPRB7): Selects the priority level of 8-bit timer channel 0, 1 interrupt requests. Bit 7 IPRB7 Description 8-bit timer channel 0, 1 interrupt requests have priority level 0 (low priority)(Initial value) 8-bit timer channel 0, 1 interrupt requests have priority level 1 (high priority) Bit 6—Priority Level B6 (IPRB6): Selects the priority level of 8-bit timer channel 2, 3 interrupt requests.
Page 125 Section 5 Interrupt Controller Bit 2—Priority Level B2 (IPRB2): Selects the priority level of SCI channel 1 interrupt requests. Bit 2 IPRB2 Description SCI1 interrupt requests have priority level 0 (low priority) (Initial value) SCI1 interrupt requests have priority level 1 (high priority) Bit 1—Priority Level B1 (IPRB1): Selects the priority level of SCI channel 2 interrupt requests.
Page 126: Irq Status Register (Isr)
Section 5 Interrupt Controller 5.2.3 IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ to IRQ interrupt requests.   IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value   Read/Write R/(W) * R/(W) * R/(W) * R/(W) *...
Page 127: Irq Enable Register (Ier)
Section 5 Interrupt Controller 5.2.4 IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ to IRQ interrupt requests.   IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value Read/Write IRQ to IRQ enable Reserved bits These bits enable or disable IRQ to IRQ interrupts IER is initialized to H'00 by a reset and in hardware standby mode.
Page 128: Irq Sense Control Register (Iscr)
Section 5 Interrupt Controller 5.2.5 IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins IRQ to IRQ   IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC Initial value Read/Write IRQ to IRQ sense control Reserved bits...
Page 129: Interrupt Sources
Section 5 Interrupt Controller Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ to IRQ ) and 36 internal interrupts. 5.3.1 External Interrupts There are seven external interrupts: NMI, and IRQ to IRQ . Of these, NMI, IRQ , IRQ , and IRQ can be used to exit software standby mode.
Page 130: Internal Interrupts
Section 5 Interrupt Controller Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF). φ IRQn input pin IRQnF Note: n = 5 to 0 Figure 5.3 Timing of Setting of IRQnF Interrupts IRQ to IRQ have vector numbers 12 to 17. These interrupts are detected regardless of whether the corresponding pin is set for input or output.
Page 131 Section 5 Interrupt Controller Table 5.3 Interrupt Sources, Vector Addresses, and Priority Vector Address* Vector Interrupt Source Origin Number Advanced Mode Normal Mode Priority H'001C to H'001F H'000E to H'000F  External High pins H'0030 to H'0033 H'0018 to H'0019 IPRA7 H'0034 to H0037 H'001A to H'001B IPRA6 H'0038 to H'003B...
Page 132 Section 5 Interrupt Controller Vector Address* Vector Interrupt Source Origin Number Advanced Mode Normal Mode Priority IMIA2 16-bit timer H'0080 to H'0083 H'0040 to H'0041 IPRA0 High (compare match/ channel 2 input capture A2) IMIB2 H'0084 to H'0087 H'0042 to H'0043 (compare match/ input capture B2) OVI2 (overflow 2)
Page 133 Section 5 Interrupt Controller Vector Address* Vector Interrupt Source Origin Number Advanced Mode Normal Mode Priority ERI0 H'00D0 to H'00D3 H'0068 to H'0069 IPRB3 High (receive error 0) channel 0 RXI0 (receive H'00D4 to H'00D7 H'006A to H'006B data full 0) H'00D8 to H'00DB H'006C to H'006D TXI0 (transmit...
Page 134: Interrupt Operation
Section 5 Interrupt Controller Interrupt Operation 5.4.1 Interrupt Handling Process The H8/3067 Group handles interrupts differently depending on the setting of the UE bit. When UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI bits.
Page 135 Section 5 Interrupt Controller Program execution state Interrupt requested? Pending Priority level 1? TEI2 TEI2 I = 0 Save PC and CCR ← Read vector address Branch to interrupt service routine Figure 5.4 Process Up to Interrupt Acceptance when UE = 1 Rev.
Page 136 Section 5 Interrupt Controller • If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. • When the interrupt controller receives one or more interrupt requests, it selects the highest- priority request, following the IPR interrupt priority settings, and holds other requests pending.
Page 137 Section 5 Interrupt Controller Figure 5.5 shows the transitions among the above states. ← All interrupts are Only NMI, IRQ , and ← ← 1, UI unmasked IRQ are unmasked Exception handling, ← ← or I 1, UI ← ← Exception handling, ←...
Page 138 Section 5 Interrupt Controller Program execution state Interrupt requested? Pending Priority level 1? TEI2 TEI2 I = 0 I = 0 UI = 0 Save PC and CCR ← ← 1, UI Read vector address Branch to interrupt service routine Figure 5.6 Process Up to Interrupt Acceptance when UE = 0 Rev.
Page 139: Interrupt Sequence
Section 5 Interrupt Controller 5.4.2 Interrupt Sequence Figure 5.7 shows the interrupt sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. Figure 5.7 Interrupt Sequence Rev.
Page 140: Interrupt Response Time
Section 5 Interrupt Controller 5.4.3 Interrupt Response Time Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5.5 Interrupt Response Time External Memory 8-Bit Bus 16-Bit Bus On-Chip...
Page 141: Usage Notes
Section 5 Interrupt Controller Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR, MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt exception handling is carried out.
Page 142: Instructions That Inhibit Interrupts
Section 5 Interrupt Controller 5.5.2 Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting instructions, however, when the instruction is completed the CPU always continues by executing the next instruction.
Page 143: Section 6 Bus Controller
Section 6 Bus Controller Section 6 Bus Controller Overview The H8/3067 Group has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily.
Page 144 Section 6 Bus Controller • Idle cycle insertion  An idle cycle can be inserted in case of an external read cycle between different areas  An idle cycle can be inserted when an external read cycle is immediately followed by an external write cycle •...
Page 145: Block Diagram
Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. to CS ABWCR ASTCR Area Internal address bus Internal signals CSCR decoder Chip select ADRCR Bus mode control signal control signals Bus size control signal Bus control circuit Access state control signal...
Page 146: Pin Configuration
Section 6 Bus Controller 6.1.3 Pin Configuration Table 6.1 summarizes the input/output pins of the bus controller. Table 6.1 Bus Controller Pins Name Abbreviation Function to CS Chip select 0 to 7 Output Strobe signals selecting areas 0 to 7 Address strobe Output Strobe signal indicating valid address output...
Page 147: Register Configuration
Section 6 Bus Controller 6.1.4 Register Configuration Table 6.2 summarizes the bus controller's registers. Table 6.2 Bus Controller Registers Address * Name Abbreviation Initial Value H'FF * H'EE020 Bus width control register ABWCR H'EE021 Access state control register ASTCR H'FF H'EE022 Wait control register H WCRH...
Page 148: Register Descriptions
Section 6 Bus Controller Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area. ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Modes Initial value 1, 3, 5, 6, and 7 Read/Write Modes...
Page 149: Access State Control Register (Astcr)
Section 6 Bus Controller 6.2.2 Access State Control Register (ASTCR) ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two states or three states. AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial value Read/Write Bits selecting number of states for access to each area ASTCR is initialized to H'FF by a reset and in hardware standby mode.
Page 150 Section 6 Bus Controller WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode. They are not initialized in software standby mode. WCRH Initial value Read/Write Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1.
Page 151 Section 6 Bus Controller Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1.
Page 152 Section 6 Bus Controller WCRL Initial value Read/Write Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1.
Page 153 Section 6 Bus Controller Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1.
Page 154: Bus Release Control Register (Brcr)
Section 6 Bus Controller 6.2.4 Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables address output on bus lines A to A enables or disables release of the bus to an external device. A23E A22E A21E A20E —...
Page 155 Section 6 Bus Controller Bit 6—Address 22 Enable (A22E): Enables PA to be used as the A address output pin. Writing 0 in this bit enables A output from PA . In modes other than 3, 4, and 5, this bit cannot be modified and PA has its ordinary port functions.
Page 156: Bus Control Register (Bcr)
Section 6 Bus Controller 6.2.5 Bus Control Register (BCR) ICIS1 ICIS0 BROME BRSTS1 BRSTS0 — RDEA WAITE Initial value Read/Write — BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the area division unit, and enables or disables WAIT pin input. BCR is initialized to H'C6 by a reset and in hardware standby mode.
Page 157 Section 6 Bus Controller Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycle states for the burst ROM interface. Bit 4 BRSTS1 Description Burst access cycle comprises 2 states (Initial value) Burst access cycle comprises 3 states Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access.
Page 158: Chip Select Control Register (Cscr)
Section 6 Bus Controller 6.2.6 Chip Select Control Register (CSCR) CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals to CS If output of a chip select signal is enabled by a setting in this register, the corresponding pin to CS functions as a chip select signal (CS ) output regardless of any other settings.
Page 159: Dram Control Register A (Drcra)
Section 6 Bus Controller Bits 3 to 0—Reserved: These bits cannot be modified and are always read as 1. 6.2.7 DRAM Control Register A (DRCRA) DRAS2 DRAS1 DRAS0 — SRFMD RFSHE Initial value Read/Write — DRCRA is an 8-bit readable/writable register that selects the areas that have a DRAM interface function, and the access mode, and enables or disables self-refreshing and refresh pin output.
Page 160 Section 6 Bus Controller When an arbitrary value has been set in DRAS2 to DRAS0, a write of a different value other than 000 must not be performed. Bit 4—Reserved: This bit cannot be modified and is always read as 1. Bit 3—Burst Access Enable (BE): Enables or disables burst access to DRAM space.
Page 161: Dram Control Register B (Drcrb)
Section 6 Bus Controller Bit 0—Refresh Pin Enable (RFSHE): Enables or disables RFSH pin refresh signal output. If areas 2 to 5 are not designated as DRAM space, this bit should not be set to 1. Bit 0 RFSHE Description RFSH pin refresh signal output disabled (Initial value) (RFSH pin can be used as input/output port)
Page 162 Section 6 Bus Controller Bits 7 and 6—Multiplex Control 1 and 0 (MXC1, MXC0): These bits select the row address/column address multiplexing method used on the DRAM interface. In burst operation, the row address used for comparison is determined by the setting of these bits and the bus width of the relevant area set in ABWCR.
Page 163 Section 6 Bus Controller Bit 4—Refresh Cycle Enable (RCYCE): Enables or disables CAS-before-RAS refresh cycle insertion. When none of areas 2 to 5 has been designated as DRAM space, refresh cycles are not inserted regardless of the setting of this bit. Bit 4 RCYCE Description...
Page 164: Refresh Timer Control/Status Register (Rtmcsr)
Section 6 Bus Controller 6.2.9 Refresh Timer Control/Status Register (RTMCSR) CMIE CKS2 CKS1 CKS0 — — — Initial value Read/Write R(W)* — — — RTMCSR is an 8-bit readable/writable register that selects the refresh timer counter clock. When the refresh timer is used as an interval timer, RTMCSR also enables or disables interrupt requests. Bits 7 and 6 of RTMCSR are initialized to 0 by a reset and in the standby modes.
Page 165: Refresh Timer Counter (Rtcnt)
Section 6 Bus Controller Bits 5 to 3—Refresh Counter Clock Select (CKS2 to CKS0): These bits select the clock to be input to RTCNT from among 7 clocks obtained by dividing the system clock (φ). When the input clock is selected with bits CKS2 to CKS0, RTCNT begins counting up. Bit 5 Bit 4 Bit 3...
Page 166: Refresh Time Constant Register (Rtcor)
Section 6 Bus Controller 6.2.11 Refresh Time Constant Register (RTCOR) Initial value Read/Write RTCOR is an 8-bit readable/writable register that determines the interval at which RTCNT is cleared. RTCOR and RTCNT are constantly compared. When their values match, the CMF flag is set to 1 in RTMCSR, and RTCNT is simultaneously cleared to H'00.
Page 167: Address Control Register (Adrcr) (Provided Only In Flash Memory R Version And Mask Rom Versions)
Section 6 Bus Controller 6.2.12 Address Control Register (ADRCR) (Provided Only in Flash Memory R Version and Mask ROM Versions) ADRCR is an 8-bit readable/writable register that selects either address update mode 1 or address update mode 2 as the address output method. —...
Page 168: Operation
Section 6 Bus Controller Operation 6.3.1 Area Division The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the 1- Mbyte modes, or 2-Mbytes in the 16-Mbyte modes. Figure 6.2 shows a general view of the memory map.
Page 169 Section 6 Bus Controller to CS Chip select signals (CS ) can be output for areas 0 to 7. The bus specifications for each area are selected in ABWCR, ASTCR, WCRH, and WCRL. In 16-Mbyte mode, the area division units can be selected with the RDEA bit in BCR. Rev.
Page 170 Section 6 Bus Controller H'000000 Area 0 Area 0 2 Mbytes 2 Mbytes H'1FFFFF H'200000 Area 1 Area 1 2 Mbytes 2 Mbytes H'3FFFFF H'400000 Area 2 2 Mbytes Area 2 H'5FFFFF 8 Mbytes H'600000 Area 3 2 Mbytes H'7FFFFF H'800000 Area 4 2 Mbytes...
Page 171: Bus Specifications
Section 6 Bus Controller 6.3.2 Bus Specifications The external space bus specifications consist of three elements: (1) bus width, (2) number of access states, and (3) number of program wait states. The bus width and number of access states for on-chip memory and registers are fixed, and are not affected by the bus controller.
Page 172: Memory Interfaces
Section 6 Bus Controller Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH/WCRL Bus Specifications (Basic Bus Interface) ABWn ASTn Bus Width Access States Program Wait States — — — — Note: n = 7 to 0 6.3.3 Memory Interfaces The H8/3067 Group memory interfaces comprise a basic bus interface that allows direct...
Page 173 Section 6 Bus Controller in the input state. To output chip select signals CS to CS , the corresponding DDR bits must be set to 1. For details, see section 8, I/O Ports. Output of CS to CS : Output of CS to CS is enabled or disabled in the chip select control register (CSCR).
Page 174: Address Output Method
Section 6 Bus Controller 6.3.5 Address Output Method The H8/3067 Group provides a choice of two address update methods: either the same method as in the previous H8/300H Series (address update mode 1), or a method in which address update is restricted to external space accesses or self-refresh cycles (address update mode 2).
Page 175 Section 6 Bus Controller • ADRCR is allocated to address H'FEE01E. In the flash memory version, the corresponding address is empty space, but it is necessary to confirm that no accesses are made to H'FEE01E in the program. • When address update mode 2 is selected, the address in an internal space (on-chip memory or internal I/O) access cycle is not output externally.
Page 176: Basic Bus Interface
Section 6 Bus Controller Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword.
Page 177: Valid Strobes
Section 6 Bus Controller In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address.
Page 178: Memory Areas
Section 6 Bus Controller Table 6.4 Data Buses Used and Valid Strobes Access Upper Data Bus Lower Data Bus Area Size Read/Write Address Valid Strobe to D to D 8-bit Byte Read — Valid Invalid access Write — Undetermined area data 16-bit Byte...
Page 179 Section 6 Bus Controller Areas 2 to 5: In external expansion mode, areas 2 to 5 are entirely external space. When area 2 to 5 external space is accessed, signals CS to CS can be output. Basic bus interface or DRAM interface can be selected for areas 2 to 5. With the DRAM interface, signals CS to CS are used as RAS signals.
Page 180: Basic Bus Control Signal Timing
Section 6 Bus Controller 6.4.5 Basic Bus Control Signal Timing 8-Bit, Three-State-Access Areas Figure 6.9 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper ) is used in accesses to these areas. The LWR pin is always high. Wait states can data bus (D to D be inserted.
Page 181 Section 6 Bus Controller 8-Bit, Two-State-Access Areas Figure 6.10 shows the timing of bus control signals for an 8-bit, two-state-access area. The upper ) is used in accesses to these areas. The LWR pin is always high. Wait states data bus (D to D cannot be inserted.
Page 182 Section 6 Bus Controller 16-Bit, Three-State-Access Areas Figures 6.11 to 6.13 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper data bus (D to D ) is used in accesses to even addresses and the lower data bus (D to D ) in accesses to odd addresses.
Page 183 Section 6 Bus Controller Bus cycle φ Address bus Odd external address in area n to D Invalid Read access to D Valid High Write access Undetermined data to D to D Valid Note: n = 7 to 0 Figure 6.12 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2) (Byte Access to Odd Address) Rev.
Page 184 Section 6 Bus Controller Bus cycle φ Address bus External address in area n Valid to D Read access to D Valid Write access Valid to D to D Valid Note: n = 7 to 0 Figure 6.13 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3) (Word Access) Rev.
Page 185 Section 6 Bus Controller 16-Bit, Two-State-Access Areas: Figures 6.14 to 6.16 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper data bus (D to D ) is used in accesses to even addresses and the lower data bus (D to D ) in accesses to odd addresses.
Page 186 Section 6 Bus Controller Bus cycle φ Address bus Odd external address in area n to D Invalid Read access to D Valid High Write access to D Undetermined data to D Valid Note: n = 7 to 0 Figure 6.15 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2) (Byte Access to Odd Address) Rev.
Page 187: Wait Control
Section 6 Bus Controller Bus cycle φ Address bus External address in area n Valid to D Read access to D Valid Write access Valid to D Valid to D Note: n = 7 to 0 Figure 6.16 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3) (Word Access) 6.4.6 Wait Control...
Page 188 Section 6 Bus Controller Pin Wait Insertion: Setting the WAITE bit in BCR to 1 enables wait insertion by means of the WAIT pin. When external space is accessed in this state, a program wait is first inserted. If the WAIT pin is low at the falling edge of φ...
Page 189: Dram Interface
Section 6 Bus Controller DRAM Interface 6.5.1 Overview The H8/3067 Group is provided with a DRAM interface with functions for DRAM control signal (RAS, UCAS, LCAS, WE) output, address multiplexing, and refreshing, that direct connection of DRAM. In the expanded modes, external address space areas 2 to 5 can be designated as DRAM space accessed via the DRAM interface.
Page 190 Section 6 Bus Controller Table 6.5 Settings of Bits DRAS2 to DRAS0 and Corresponding DRAM Space (RAS Output Pin) DRAS2 DRAS1 DRAS0 Area 5 Area 4 Area 3 Area 2 Normal space Normal space Normal space Normal space Normal space Normal space Normal space DRAM space...
Page 191: Address Multiplexing
Section 6 Bus Controller 6.5.3 Address Multiplexing When DRAM space is accessed, the row address and column address are multiplexed. The address multiplexing method is selected with bits MXC1 and MXC0 in DRCRB according to the number of bits in the DRAM column address. Table 6.6 shows the correspondence between the settings of MXC1 and MXC0 and the address multiplexing method.
Page 192: Pins Used For Dram Interface
Section 6 Bus Controller 6.5.5 Pins Used for DRAM Interface Table 6.7 shows the pins used for DRAM interfacing and their functions. Table 6.7 DRAM Interface Pins With DRAM Designated Name Function UCAS Upper column Output Upper column address strobe for DRAM address strobe space access (when CSEL = 0 in DRCRB) LCAS...
Page 193 Section 6 Bus Controller If a DRAM read/write cycle is followed by an access cycle for an external area other than DRAM space when HWR and LWR are selected as the UCAS and LCAS output pins, an idle cycle (Ti) is inserted unconditionally immediately after the DRAM access cycle.
Page 194: Precharge State Control
Section 6 Bus Controller 6.5.7 Precharge State Control In the H8/3067 Group, provision is made for the DRAM RAS precharge time by always inserting one RAS precharge state (T ) when DRAM space is accessed. This can be changed to two T states by setting the TPC bit to 1 in DRCRB.
Page 195: Wait Control
Section 6 Bus Controller 6.5.8 Wait Control In a DRAM access cycle, wait states can be inserted (1) between the T state and T state, and (2) between the T state and T state. Insertion of T Wait State between T and T : One T state can be inserted between T...
Page 196: Byte Access Control And Cas Output Pin
Section 6 Bus Controller φ Column to A High level CSn(RAS) (UCAS /LCAS) Read access RD(WE) High level Read data to D (UCAS /LCAS) Write access RD(WE) Write data to D Note: n = 2 to 5 Figure 6.20 Example of Wait State Insertion Timing (CSEL = 0) Byte Access Control and CAS CAS Output Pin 6.5.9...
Page 197 Section 6 Bus Controller When an access is made to DRAM space designated as an 8-bit-access area in ABWCR, only UCAS is output. When the entire DRAM space is designated as 8-bit-access space and CSEL = 0, PB5 can be used as an input/output port. Note that RAS down mode cannot be used when a device other than DRAM is connected to external space and HWR and LWR are used as write strobes.
Page 198: Burst Operation
Section 6 Bus Controller 6.5.10 Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number of consecutive accesses to the same row address.
Page 199 Section 6 Bus Controller φ to A Column 1 Column 2 High level CSn(RAS) (UCAS /LCAS) Read access RD(WE) to D (UCAS/LCAS) Write access RD(WE) to D Note: n = 2 to 5 Figure 6.22 Operation Timing in Fast Page Mode Rev.
Page 200 Section 6 Bus Controller Table 6.9 Correspondence between Settings of MXC1 and MXC0 Bits and ABWCR, and Row Address Compared in Burst Access DRCRB ABWCR Operating Mode MXC1 MXC0 ABWn Bus Width Compared Row Address Modes 1 and 2 16 bits A19 to A9 (1-Mbyte) 8 bits...
Page 201 Section 6 Bus Controller External space access DRAM access DRAM access φ to A CSn (RAS) (UCAS/LCAS) to D Note: n = 2 to 5 Figure 6.23 Example of Operation Timing in RAS Down Mode (CSEL = 0) When RAS down mode is selected, the conditions for an asserted RASn signal to return to the high level are as shown below.
Page 202 Section 6 Bus Controller DRAM access cycle φ RASn (a) Access to DRAM space with a different row address CBR refresh cycle φ RASn (b) CAS-before-RAS refresh cycle DRCRA write cycle φ RASn (c) BE bit or RDM bit cleared to 0 in DRCRA External bus released φ...
Page 203 Section 6 Bus Controller When RAS down mode is selected, the CAS-before-RAS refresh function provided with this DRAM interface must always be used as the DRAM refreshing method. When a refresh operation is performed, the RAS signal goes high immediately beforehand. The refresh interval setting must be made so that the maximum DRAM RAS pulse width specification is observed.
Page 204: Refresh Control
Section 6 Bus Controller 6.5.11 Refresh Control The H8/3067 Group is provided with a CAS-before-RAS (CBR) function and self-refresh function as DRAM refresh control functions. CAS-Before-RAS (CBR) Refreshing: To select CBR refreshing, set the RCYCE bit to 1 in DRCRB. With CBR refreshing, RTCNT counts up using the input clock selected by bits CKS2 to CKS0 in RTMCSR, and a refresh request is generated when the count matches the value set in RTCOR (compare match).
Page 205 Section 6 Bus Controller φ RTCNT H'00 RTCOR Refresh request signal and CMF bit setting signal Figure 6.27 Compare Match Timing φ Area 2 start address Address bus* (RAS) (UCAS/LCAS) RD(WE) High RFSH High level Note: * In address update mode 1, the area 2 start address is output. In address update mode 2, the address in the preceding bus cycle is retained.
Page 206 Section 6 Bus Controller The basic CBS refresh cycle timing comprises three states: one RAS precharge cycle (T ) state, and two RAS output cycle (T ) states. Either one or two states can be selected for the RAS precharge cycle. When the TPC bit is set to 1 in DRCRB, RAS signal output is delayed by one cycle.
Page 207 Section 6 Bus Controller DRAM must be refreshed immediately after powering on in order to stabilize its internal state. When using the H8/3067 Group CAS-before-RAS refresh function, therefore, a DRAM stabilization period should be provided by means of interrupts by another timer module, or by counting the number of times bit 7 (CMF) of RTMCSR is set, for instance, immediately after bits DRAS2 to DRAS0 have been set in DRCRA.
Page 208: Examples Of Use
Section 6 Bus Controller Software standby Oscillation stabilization mode time φ High-impedance Address bus (RAS) (UCAS) (LCAS) RD(WE) RFSH Figure 6.30 Self-Refresh Timing (CSEL = 0) RFSH): A refresh signal (RFSH) that transmits a refresh cycle off-chip can be RFSH RFSH Refresh Signal (RFSH output by setting the RFSHE bit to 1 in DRCRA.
Page 209 Section 6 Bus Controller 2-CAS 16-Mbit DRAM 10-bit row address x 10-bit column address x16-bit organization H8/3067 Group chip (RAS (RAS (UCAS) UCAS (LCAS) LCAS No.1 RD (WE) UCAS LCAS No.2 (a) Interconnections (example) (UCAS) (LCAS) H'400000 Area 2 DRAM (No.1) (RAS H'5FFFFE H'600000...
Page 210 Section 6 Bus Controller • Figure 6.32 shows typical interconnections when using two 16-Mbit DRAMs using a × 8-bit organization, and the corresponding address map. The DRAMs used in this example are of the 11-bit row address × 10-bit column address type. The CS pin is used as the common RAS output pin for areas 2 and 3.
Page 211 Section 6 Bus Controller • Figure 6.33 shows typical interconnections when using two 4-Mbit DRAMs, and the corresponding address map. The DRAMs used in this example are of the 9-bit row address × 10-bit column address type. In this example, upper address decoding allows multiple DRAMs to be connected to a single area.
Page 212: Usage Notes
Section 6 Bus Controller Example of Program Setup Procedure: Figure 6.34 shows an example of the program setup procedure. Set ABWCR Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Set DRCRB Set DRCRA Wait for DRAM stabilization time DRAM can be accessed Figure 6.34 Example of Setup Procedure when Using DRAM Interface 6.5.13 Usage Notes...
Page 213 Section 6 Bus Controller • In the event of contention with a bus request from an external bus master when a transition is made to software standby mode, the BACK and strobe states may be indeterminate after the transition to software standby mode (see figure 6.36). When software standby mode is used, the BRLE bit should be cleared to 0 in BRCR before executing the SLEEP instruction.
Page 214 Section 6 Bus Controller Software standby mode φ BREQ BACK Address bus Strobe Figure 6.36 Bus-Released State and Software Standby Mode Oscillation stabilization CPU internal cycle CPU cycle time on exit from software (period in which external standby mode bus can be released) φ...
Page 215: Interval Timer
Section 6 Bus Controller Interval Timer 6.6.1 Operation When DRAM is not connected to the H8/3067 Group chip, the refresh timer can be used as an interval timer by clearing bits DRAS2 to DRAS0 in DRCRA to 0. After setting RTCOR, selection a clock source with bits CKS2 to CKS0 in RTMCSR, and set the CMIE bit to 1.
Page 216 Section 6 Bus Controller Operation in Power-Down State: The interval timer operates in sleep mode. It does not operate in hardware standby mode. In software standby mode, RTCNT and RTMCSR bits 7 and 6 are initialized, but RTMCSR bits 5 to 3 and RTCOR retain their settings prior to the transition to software standby mode.
Page 217 Section 6 Bus Controller Contention between RTCNT Write and Increment: If an increment pulse occurs in the T state of an RTCNT write cycle, writing takes priority and RTCNT is not incremented. See Figure 6.40. φ Address bus RTCNT address Internal write signal RTCNT input clock RTCNT...
Page 218 Section 6 Bus Controller Contention between RTCOR Write and Compare Match: If a compare match occurs in the T state of an RTCOR write cycle, writing takes priority and the compare match signal is inhibited. See Figure 6.41. φ Address bus RTCOR address Internal write signal RTCNT...
Page 219 Section 6 Bus Controller Table 6.10 Internal Clock Switchover and RTCNT Operation (1) CKS2 to CKS0 RTCNT Operation Write Timing "Low" "Low" switchover* Old clock source New clock source RTCNT clock RTCNT CKS bits rewritten "Low" "High" switchover* Old clock source New clock source RTCNT clock RTCNT...
Page 220 Section 6 Bus Controller Table 6.10 Internal Clock Switchover and RTCNT Operation (2) CKS2 to CKS0 RTCNT Operation Write Timing "High" "Low" switchover* Old clock source New clock source RTCNT clock RTCNT CKS bits rewritten "High" "High" switchover* Old clock source New clock source RTCNT clock RTCNT...
Page 221: Interrupt Sources
Section 6 Bus Controller Interrupt Sources Compare match interrupts (CMI) can be generated when the refresh timer is used as an interval timer. Compare match interrupt requests are masked/unmasked with the CMIE bit in RTMCSR. Burst ROM Interface 6.8.1 Overview With the H8/3067 Group, external space area 0 can be designated as burst ROM space, and burst ROM space interfacing can be performed.
Page 222: Wait Control
Section 6 Bus Controller Full access Burst access φ Address bus Only lower address changes Data bus Read data Read data Read data Figure 6.42 Example of Burst ROM Access Timing 6.8.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface.
Page 223: Idle Cycle
Section 6 Bus Controller Idle Cycle 6.9.1 Operation When the H8/3067 Group chip accesses external space, it can insert a 1-state idle cycle (T between bus cycles in the following cases: (1) when read accesses between different areas occur consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) immediately after a DRAM space access.
Page 224 Section 6 Bus Controller Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.44 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.
Page 225 Section 6 Bus Controller Bus cycle A Bus cycle A (DRAM access cycle) Bus cycle B (DRAM access cycle) Bus cycle B Tr Tc1 Tc2 Tr Tc1 Tc2 φ φ Address bus Address bus HWR/LWR HWR/LWR (UCAS/LCAS) (UCAS/LCAS) Simultaneous change of HWR/LWR and CSn (a) Idle cycle not inserted (b) Idle cycle inserted...
Page 226: Pin States In Idle Cycle
Section 6 Bus Controller A setting whereby idle cycle insertion is not performed can be made only when RD and CSn do not change simultaneously, or when it does not matter if they do. Bus cycle A Bus cycle B Bus cycle A Bus cycle B φ...
Page 227: Bus Arbiter
Section 6 Bus Controller 6.10 Bus Arbiter The bus controller has a built-in bus arbiter that arbitrates between different bus masters. There are four bus masters: the CPU, DMA controller (DMAC), DRAM interface, and an external bus master. When a bus master has the bus right it can carry out read, write, or refresh access. Each bus master uses a bus request signal to request the bus right.
Page 228 Section 6 Bus Controller DMAC: When the DMAC receives an activation request, it requests the bus right from the bus arbiter. If the DMAC is bus master and the DRAM interface or an external bus master requests the bus, the bus arbiter transfers the bus right from the DMAC to the bus master that requested the bus.
Page 229 Section 6 Bus Controller CPU cycles External bus released CPU cycles φ High-impedance Address Address bus High-impedance Data bus High-impedance High-impedance High High-impedance HWR, LWR BREQ BACK Minimum 3 cycles Figure 6.48 Example of External Bus Master Operation In the event of contention with a bus request from an external bus master when a transition is made to software standby mode, the BACK and strobe states may be indeterminate after the transition to software standby mode (see figure 6.36).
Page 230: Register And Pin Input Timing
Section 6 Bus Controller 6.11 Register and Pin Input Timing 6.11.1 Register Write Timing ABWCR, ASTCR, WCRH, and WCRL Write Timing: Data written to ABWCR, ASTCR, WCRH, and WCRL takes effect starting from the next bus cycle. Figure 6.49 shows the timing when an instruction fetched from area 0 changes area 0 from three-state access to two-state access.
Page 231: Breq Pin Input Timing
Section 6 Bus Controller BRCR Write Timing: Data written to BRCR to switch between A , or A output and generic input or output takes effect starting from the T state of the BRCR write cycle. Figure 6.51 shows the timing when a pin is changed from generic input to A , or A output.
Page 232 Section 6 Bus Controller Rev. 4.00 Jan 26, 2006 page 208 of 938 REJ09B0276-0400...
Page 233: Section 7 Dma Controller
Section 7 DMA Controller Section 7 DMA Controller Overview The H8/3067 Group has an on-chip DMA controller (DMAC) that can transfer data on up to four channels. When the DMA controller is not used, it can be independently halted to conserve power. For details see section 20.6, Module Standby Function.
Page 234: Block Diagram
Section 7 DMA Controller 7.1.2 Block Diagram Figure 7.1 shows a DMAC block diagram. Internal address bus Address buffer Internal IMIA0 interrupts IMIA1 Arithmetic-logic unit IMIA2 TXI0 MAR0A RXI0 Channel IOAR0A ETCR0A Channel DREQ Control logic DREQ MAR0B TEND Channel IOAR0B TEND DTCR0A...
Page 235: Functional Overview
Section 7 DMA Controller 7.1.3 Functional Overview Table 7.1 gives an overview of the DMAC functions. Table 7.1 DMAC Functional Overview Address Reg. Length Transfer Mode Activation Source Destination • Short I/O mode Compare match/input • address capture A interrupts from Transfers one byte or one word 16-bit timer channels 0 to mode...
Page 236: Input/Output Pins
Section 7 DMA Controller 7.1.4 Input/Output Pins Table 7.2 lists the DMAC pins. Table 7.2 DMAC Pins Abbrevia- Input/ Channel Name tion Output Function DREQ DMA request 0 Input External request for DMAC channel 0 TEND Transfer end 0 Output Transfer end on DMAC channel 0 DREQ DMA request 1...
Page 237 Section 7 DMA Controller Table 7.3 DMAC Registers Channel Address* Name Abbreviation R/W Initial Value H'FFF20 Memory address register 0AR MAR0AR Undetermined H'FFF21 Memory address register 0AE MAR0AE Undetermined H'FFF22 Memory address register 0AH MAR0AH Undetermined H'FFF23 Memory address register 0AL MAR0AL Undetermined H'FFF26...
Page 238: Register Descriptions (1) (Short Address Mode)
Section 7 DMA Controller Register Descriptions (1) (Short Address Mode) In short address mode, transfers can be carried out independently on channels A and B. Short address mode is selected by bits DTS2A and DTS1A in data transfer control register A (DTCRA) as indicated in table 7.4.
Page 239: I/O Address Registers (Ioar)
Section 7 DMA Controller The MARs are not initialized by a reset or in standby mode. 7.2.2 I/O Address Registers (IOAR) An I/O address register (IOAR) is an 8-bit readable/writable register that specifies a source or destination address. The IOAR value is the lower 8 bits of the address. The upper 16 address bits are all 1 (H'FFFF).
Page 240 Section 7 DMA Controller • Repeat mode Initial value Undetermined Read/Write ETCRH Transfer counter Initial value Undetermined Read/Write ETCRL Initial count In repeat mode, ETCRH functions as an 8-bit transfer counter and ETCRL holds the initial transfer count. ETCRH is decremented by 1 each time one transfer is executed. When ETCRH reaches H'00, the value in ETCRL is reloaded into ETCRH and the same operation is repeated.
Page 241: Data Transfer Control Registers (Dtcr)
Section 7 DMA Controller 7.2.4 Data Transfer Control Registers (DTCR) A data transfer control register (DTCR) is an 8-bit readable/writable register that controls the operation of one DMAC channel. DTSZ DTID DTIE DTS2 DTS1 DTS0 Initial value Read/Write Data transfer enable Data transfer select Enables or disables These bits select the data...
Page 242 Section 7 DMA Controller Bit 6—Data Transfer Size (DTSZ): Selects the data size of each transfer. Bit 6 DTSZ Description Byte-size transfer (Initial value) Word-size transfer Bit 5—Data Transfer Increment/Decrement (DTID): Selects whether to increment or decrement the memory address register (MAR) after a data transfer in I/O mode or repeat mode. Bit 5 DTID Description...
Page 243 Section 7 DMA Controller Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND) requested when the DTE bit is cleared to 0. Bit 3 DTIE Description The DEND interrupt requested by DTE is disabled (Initial value) The DEND interrupt requested by DTE is enabled Bits 2 to 0—Data Transfer Select (DTS2, DTS1, DTS0): These bits select the data transfer activation source.
Page 244: Register Descriptions (2) (Full Address Mode)
Section 7 DMA Controller Register Descriptions (2) (Full Address Mode) In full address mode the A and B channels operate together. Full address mode is selected as indicated in table 7.4. 7.3.1 Memory Address Registers (MAR) A memory address register (MAR) is a 32-bit readable/writable register. MARA functions as the source address register of the transfer, and MARB as the destination address register.
Page 245: Execute Transfer Count Registers (Etcr)
Section 7 DMA Controller 7.3.3 Execute Transfer Count Registers (ETCR) An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the number of transfers to be executed. The functions of these registers differ between normal mode and block transfer mode. •...
Page 246 Section 7 DMA Controller • Block transfer mode ETCRA Initial value Undetermined Read/Write ETCRAH Block size counter Initial value Undetermined Read/Write ETCRAL Initial block size ETCRB Initial value Undetermined Read/Write Block transfer counter In block transfer mode, ETCRAH functions as an 8-bit block size counter. ETCRAL holds the initial block size.
Page 247: Data Transfer Control Registers (Dtcr)
Section 7 DMA Controller 7.3.4 Data Transfer Control Registers (DTCR) The data transfer control registers (DTCRs) are 8-bit readable/writable registers that control the operation of the DMAC channels. A channel operates in full address mode when bits DTS2A and DTS1A are both set to 1 in DTCRA. DTCRA and DTCRB have different functions in full address mode.
Page 248 Section 7 DMA Controller Bit 7—Data Transfer Enable (DTE): Together with the DTME bit in DTCRB, this bit enables or disables data transfer on the channel. When the DTME and DTE bits are both set to 1, the channel is enabled. If auto-request is specified, data transfer begins immediately. Otherwise, the channel waits for transfers to be requested.
Page 249 Section 7 DMA Controller Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND) requested when the DTE bit is cleared to 0. Bit 3 DTIE Description The DEND interrupt requested by DTE is disabled (Initial value) The DEND interrupt requested by DTE is enabled Bits 2 and 1—Data Transfer Select 2A and 1A (DTS2A, DTS1A): A channel operates in full address mode when DTS2A and DTS1A are both set to 1.
Page 250 Section 7 DMA Controller DTCRB DTME Ñ DAID DAIDE DTS2B DTS1B DTS0B Initial value Read/Write Data transfer master enable Enables or disables data transfer, together with Transfer mode select the DTE bit, and is cleared Selects whether the to 0 by an interrupt block area is the source or destination in block Reserved bit...
Page 251 Section 7 DMA Controller Bit 5—Destination Address Increment/Decrement (DAID) and, Bit 4—Destination Address Increment/Decrement Enable (DAIDE): These bits select whether the destination address register (MARB) is incremented, decremented, or held fixed during the data transfer. Bit 5 Bit 4 DAID DAIDE Description MARB is held fixed...
Page 252 Section 7 DMA Controller Bits 2 to 0—Data Transfer Select 2B to 0B (DTS2B, DTS1B, DTS0B): These bits select the data transfer activation source. The selectable activation sources differ between normal mode and block transfer mode. Normal mode Bit 2 Bit 1 Bit 0 DTS2B...
Page 253: Operation
Section 7 DMA Controller Operation 7.4.1 Overview Table 7.5 summarizes the DMAC modes. Table 7.5 DMAC Modes Transfer Mode Activation Notes • Short address I/O mode Compare match/input Up to four channels mode Idle mode capture A interrupt from can operate Repeat mode 16-bit timer channels 0 to 2 independently...
Page 254 Section 7 DMA Controller transfers. One 24-bit address and one 8-bit address are specified. The addresses are held fixed. The transfer direction is determined automatically from the activation source. Repeat Mode: One byte or word is transferred per request. A designated number of these transfers are executed.
Page 255: I/O Mode
Section 7 DMA Controller 7.4.2 I/O Mode I/O mode can be selected independently for each channel. One byte or word is transferred at each transfer request in I/O mode. A designated number of these transfers are executed. One address is specified in the memory address register (MAR), the other in the I/O address register (IOAR).
Page 256 Section 7 DMA Controller MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or destination address, which is incremented or decremented as each byte or word is transferred. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not incremented or decremented.
Page 257: Idle Mode
Section 7 DMA Controller Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit timer channels 0 to 2, transmit-data-empty and receive-data-full interrupts from SCI channel 0, conversion-end interrupts from the A/D converter, and external request signals. For the detailed settings see section 7.2.4, Data Transfer Control Registers (DTCR).
Page 258 Section 7 DMA Controller Table 7.7 indicates the register functions in idle mode. Table 7.7 Register Functions in Idle Mode Function Activated by SCI 0 Receive- Data-Full Interrupt or by A/D Converter Conversion- Other Register End Interrupt Activation Initial Setting Operation Destination Source...
Page 259 Section 7 DMA Controller Transfer IOAR 1 byte or word is transferred per request Figure 7.4 Operation in Idle Mode The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared, the transfer ends, and a CPU interrupt is requested.
Page 260: Repeat Mode
Section 7 DMA Controller Idle mode setup Set the source and destination addresses in MAR and IOAR. The transfer direction is deter- mined automatically from the activation source. Set the transfer count in ETCR. Set source and Read DTCR while the DTE bit is cleared to 0. destination addresses Set the DTCR bits as follows.
Page 261 Section 7 DMA Controller Table 7.8 Register Functions in Repeat Mode Function Activated by SCI 0 Receive- Data-Full Interrupt or by A/D Converter Conversion- Other Register End Interrupt Activation Initial Setting Operation Destination Source Destination or Incremented or address address source start decremented at register...
Page 262 Section 7 DMA Controller In repeat mode transfers continue until the CPU clears the DTE bit to 0. After DTE is cleared to 0, if the CPU sets DTE to 1 again, transfers resume from the state at which DTE was cleared. No CPU interrupt is requested.
Page 263 Section 7 DMA Controller For the detailed settings see section 7.2.4, Data Transfer Control Registers (DTCR). Figure 7.7 shows a sample setup procedure for repeat mode. Repeat mode Set the source and destination addresses in MAR and IOAR. The transfer direction is determined automatically from the activation source.
Page 264: Normal Mode
Section 7 DMA Controller 7.4.5 Normal Mode In normal mode the A and B channels are combined. One byte or word is transferred per request. A designated number of these transfers are executed. Addresses are specified in MARA and MARB. Table 7.9 indicates the register functions in I/O mode. Table 7.9 Register Functions in Normal Mode Register...
Page 265 Section 7 DMA Controller Figure 7.8 illustrates how normal mode operates. Address T Transfer Address T Address B Address B Legend = initial setting of MARA = initial setting of MARB = initial setting of ETCRA = L + SAIDE • (−1) •...
Page 266 Section 7 DMA Controller For the detailed settings see section 7.3.4, Data Transfer Control Registers (DTCR). Figure 7.9 shows a sample setup procedure for normal mode. Normal mode Set the initial source address in MARA. Set the initial destination address in MARB. Set the transfer count in ETCRA.
Page 267: Block Transfer Mode
Section 7 DMA Controller 7.4.6 Block Transfer Mode In block transfer mode the A and B channels are combined. One block of a specified size is transferred per request. A designated number of block transfers are executed. Addresses are specified in MARA and MARB. The block area address can be either held fixed or cycled. Table 7.10 indicates the register functions in block transfer mode.
Page 268 Section 7 DMA Controller If M (1 to 255) is the size of the block transferred at each request and N (1 to 65,536) is the number of blocks to be transferred, then ETCRAH and ETCRAL should initially be set to M and ETCRB should initially be set to N.
Page 269 Section 7 DMA Controller When activated by a transfer request, the DMAC executes a burst transfer. During the transfer MARA and MARB are updated according to the DTCR settings, and ETCRAH is decremented. When ETCRAH reaches H'00, it is reloaded from ETCRAL to restore the initial value. The memory address register of the block area is also restored to its initial value, and ETCRB is decremented.
Page 270 Section 7 DMA Controller Start Start (DTE = DTME = 1) (DTE = DTME = 1) Transfer requested? Transfer requested? Get bus Get bus Read from MARA address Read from MARA address MARA = MARA + 1 MARA = MARA + 1 Write to MARB address Write to MARB address MARB = MARB + 1...
Page 271 Section 7 DMA Controller Figure 7.12 shows a sample setup procedure for block transfer mode. Block transfer mode Set the source address in MARA. Set the destination address in MARB. Set the block transfer count in ETCRB. Set the block size (number of bytes or words) Set source address in both ETCRAH and ETCRAL.
Page 272: Dmac Activation
Section 7 DMA Controller 7.4.7 DMAC Activation The DMAC can be activated by an internal interrupt, external request, or auto-request. The available activation sources differ depending on the transfer mode and channel as indicated in table 7.11. Table 7.11 DMAC Activation Sources Short Address Mode Channels Channels...
Page 273 Section 7 DMA Controller executed. If level sensing is selected, the transfer continues while DREQ is low, until the transfer is completed. The bus is released temporarily after each byte or word has been transferred, however. If the DREQ input goes high during a transfer, the transfer is suspended after the current byte or word has been transferred.
Page 274: Dmac Bus Cycle
Section 7 DMA Controller 7.4.8 DMAC Bus Cycle Figure 7.13 shows an example of the timing of the basic DMAC bus cycle. This example shows a word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the DMAC gets the bus from the CPU, after one dead cycle (T ), it reads from the source address and writes to the destination address.
Page 275 Section 7 DMA Controller Figure 7.14 shows the timing when the DMAC is activated by low input at a DREQ pin. This example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-state access area. The DMAC continues the transfer while the DREQ pin is held low. DMAC cycle CPU cycle DMAC cycle...
Page 276 Section 7 DMA Controller Figure 7.15 shows an auto-requested burst-mode transfer. This example shows a transfer of three words from a 16-bit two-state access area to another 16-bit two-state access area. CPU cycle DMAC cycle CPU cycle φ Source Destination address address Address...
Page 277 Section 7 DMA Controller Figure 7.16 shows the timing when the DMAC is activated by the falling edge of DREQ in normal mode. CPU cycle DMAC cycle cycle DMAC cycle φ DREQ Address Minimum 4 states Next sampling point Figure 7.16 Timing of DMAC Activation by Falling Edge of DREQ DREQ DREQ in Normal Mode DREQ...
Page 278 Section 7 DMA Controller Figure 7.17 shows the timing when the DMAC is activated by level-sensitive low DREQ input in normal mode. CPU cycle DMAC cycle CPU cycle φ DREQ Address Minimum 4 states Next sampling point Figure 7.17 Timing of DMAC Activation by Low DREQ DREQ DREQ DREQ Level in Normal Mode...
Page 279 Section 7 DMA Controller Figure 7.18 shows the timing when the DMAC is activated by the falling edge of DREQ in block transfer mode. End of 1 block transfer DMAC cycle CPU cycle DMAC cycle φ DREQ Address TEND Next sampling Minimum 4 states Figure 7.18 Timing of DMAC Activation by Falling Edge of DREQ DREQ in Block Transfer Mode...
Page 280: Multiple-Channel Operation
Section 7 DMA Controller 7.4.9 Multiple-Channel Operation The DMAC channel priority order is: channel 0 > channel 1 and channel A > channel B. Table 7.12 shows the complete priority order. Table 7.12 Channel Priority Order Short Address Mode Full Address Mode Priority Channel 0A Channel 0...
Page 281: External Bus Requests, Dram Interface, And Dmac
Section 7 DMA Controller DMAC cycle DMAC cycle DMAC cycle (channel 1) cycle (channel 0A) cycle (channel 1) φ Address Figure 7.19 Timing of Multiple-Channel Operations 7.4.10 External Bus Requests, DRAM Interface, and DMAC During a DMAC transfer, if the bus right is requested by an external bus request signal (BREQ) or by the DRAM interface (refresh cycle), the DMAC releases the bus after completing the transfer of the current byte or word.
Page 282: Nmi Interrupts And Dmac
Section 7 DMA Controller 7.4.11 NMI Interrupts and DMAC NMI interrupts do not affect DMAC operations in short address mode. If an NMI interrupt occurs during a transfer in full address mode, the DMAC suspends operations. In full address mode, a channel is enabled when its DTE and DTME bits are both set to 1. NMI input clears the DTME bit to 0.
Page 283: Aborting A Dmac Transfer
Section 7 DMA Controller 7.4.12 Aborting a DMAC Transfer When the DTE bit in an active channel is cleared to 0, the DMAC halts after transferring the current byte or word. The DMAC starts again when the DTE bit is set to 1. In full address mode, the DTME bit can be used for the same purpose.
Page 284: Exiting Full Address Mode
Section 7 DMA Controller 7.4.13 Exiting Full Address Mode Figure 7.23 shows the procedure for exiting full address mode and initializing the pair of channels. To set the channels up in another mode after exiting full address mode, follow the setup procedure for the relevant mode.
Page 285: Dmac States In Reset State, Standby Modes, And Sleep Mode
Section 7 DMA Controller 7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode When the chip is reset or enters software standby mode, the DMAC is initialized and halts. DMAC operations continue in sleep mode. Figure 7.24 shows the timing of a cycle-steal transfer in sleep mode.
Page 286: Interrupts
Section 7 DMA Controller Interrupts The DMAC generates only DMA-end interrupts. Table 7.13 lists the interrupts and their priority. Table 7.13 DMAC Interrupts Description Interrupt Short Address Mode Full Address Mode Interrupt Priority DEND0A End of transfer on channel 0A End of transfer on channel 0 High ...
Page 287: Usage Notes
Section 7 DMA Controller Usage Notes 7.6.1 Note on Word Data Transfer Word data cannot be accessed starting at an odd address. When word-size transfer is selected, set even values in the memory and I/O address registers (MAR and IOAR). 7.6.2 DMAC Self-Access The DMAC itself cannot be accessed during a DMAC cycle.
Page 288: Note On Activating Dmac By Internal Interrupts
Section 7 DMA Controller 7.6.5 Note on Activating DMAC by Internal Interrupts When using an internal interrupt to activate the DMAC, make sure that the interrupt selected as the activating source does not occur during the interval after it has been selected but before the DMAC has been enabled.
Page 289: Nmi Interrupts And Block Transfer Mode
Section 7 DMA Controller When 16-bit timer interrupt activates the DMAC, make sure the next interrupt does not occur before the DMA transfer ends. If one 16-bit timer interrupt activates two or more channels, make sure the next interrupt does not occur before the DMA transfers end on all the activated channels. If the next interrupt occurs before a transfer ends, the channel or channels for which that interrupt was selected may fail to accept further activation requests.
Page 290: Bus Cycle When Transfer Is Aborted
Section 7 DMA Controller Table 7.14 Address Ranges Specifiable in MAR and IOAR 1-Mbyte Mode 16-Mbyte Mode H'00000 to H'FFFFF H'000000 to H'FFFFFF (0 to 1048575) (0 to 16777215) IOAR H'FFF00 to H'FFFFF H'FFFF00 to H'FFFFFF (1048320 to 1048575) (16776960 to 16777215) MAR bits 23 to 20 are ignored in 1-Mbyte mode.
Page 291: Transfer Requests By A/D Converter
Section 7 DMA Controller 7.6.9 Transfer Requests by A/D Converter When the A/D converter is set to scan mode and conversion is performed on more than one channel, the A/D converter generates a transfer request when all conversions are completed. The converted data is stored in the appropriate ADDR registers.
Page 292 Section 7 DMA Controller Rev. 4.00 Jan 26, 2006 page 268 of 938 REJ09B0276-0400...
Page 293: Section 8 I/O Ports
Section 8 I/O Ports Section 8 I/O Ports Overview The H8/3067 Group has 11 input/output ports (ports 1, 2, 3, 4, 5, 6, 7, 8, 9, A, and B). Table 8.1 summarizes the port functions. The pins in each port are multiplexed as shown in table 8.1. Each port has a data direction register (DDR) for selecting input or output, and a data register (DR) for storing output data.
Page 294 Section 8 I/O Ports Table 8.1 Port Functions (1) Expanded Modes Single-Chip Modes Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Port 1 • 8-bit I/O port to P1 Address output pins (A to A Address output (A Generic input/output...
Page 295 Section 8 I/O Ports Expanded Modes Single-Chip Modes Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Port 9 • 6-bit I/O port /IRQ Input and output (SCK , SCK , RxD , RxD , TxD , TxD...
Page 296: Port 1
Section 8 I/O Ports Port 1 8.2.1 Overview Port 1 is an 8-bit input/output port also used for address output, with the pin configuration shown in figure 8.1. The pin functions differ between the expanded modes with on-chip ROM disabled, expanded modes with on-chip ROM enabled, and single-chip mode.
Page 297: Register Descriptions
Section 8 I/O Ports 8.2.2 Register Descriptions Table 8.2 summarizes the registers of port 1. Table 8.2 Port 1 Registers Initial Value Address* Name Abbreviation R/W Modes 1 to 4 Modes 5 to 7 H'EE000 Port 1 data direction register P1DDR H'FF H'00 H'FFFD0...
Page 298 Section 8 I/O Ports In modes 1 to 4, P1DDR bits are always read as 1, and cannot be modified. In modes 5 to 7, P1DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
Page 299: Port 2
Section 8 I/O Ports Port 2 8.3.1 Overview Port 2 is an 8-bit input/output port with the pin configuration shown in figure 8.2. The pin functions differ according to the operating mode. In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 2 consists of address bus output pins (A to A ).
Page 300: Register Descriptions
Section 8 I/O Ports 8.3.2 Register Descriptions Table 8.3 summarizes the registers of port 2. Table 8.3 Port 2 Registers Initial Value Address* Name Abbreviation R/W Modes 1 to 4 Modes 5 to 7 H'EE001 Port 2 data direction register P2DDR H'FF H'00...
Page 301 Section 8 I/O Ports In modes 1 to 4, P2DDR bits are always read as 1, and cannot be modified. In modes 5 to 7, P2DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
Page 302 Section 8 I/O Ports P2PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Table 8.4 Input Pull-Up Transistor States (Port 2) Hardware Software Mode Reset Standby Mode Standby Mode Other Modes On/off...
Page 303: Port 3
Section 8 I/O Ports Port 3 8.4.1 Overview Port 3 is an 8-bit input/output port with the pin configuration shown in figure 8.3. Port 3 is a data bus in modes 1 to 5 (expanded modes) and a generic input/output port in mode 6, 7 (single-chip mode).
Page 304 Section 8 I/O Ports Port 3 Data Direction Register (P3DDR): P3DDR is an 8-bit write-only register that can select input or output for each pin in port 3. P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR Initial value...
Page 305: Port 4
Section 8 I/O Ports Port 4 8.5.1 Overview Port 4 is an 8-bit input/output port with the pin configuration shown in figure 8.4. The pin functions differ depending on the operating mode. In modes 1 to 5 (expanded modes), when the bus width control register (ABWCR) designates areas 0 to 7 all as 8-bit-access areas, the chip operates in 8-bit bus mode and port 4 is a generic input/output port.
Page 306: Register Descriptions
Section 8 I/O Ports 8.5.2 Register Descriptions Table 8.6 summarizes the registers of port 4. Table 8.6 Port 4 Registers Address* Name Abbreviation Initial Value H'EE003 Port 4 data direction register P4DDR H'00 H'FFFD3 Port 4 data register P4DR H'00 H'EE03E Port 4 input pull-up control register P4PCR...
Page 307 Section 8 I/O Ports ABWCR and P4DDR are not initialized in software standby mode. Therefore, if a transition is made to software standby mode while port 4 is functioning as an input/output port and a P4DDR bit is set to 1, the corresponding pin maintains its output state. Port 4 Data Register (P4DR): P4DR is an 8-bit readable/writable register that stores output data for port 4.
Page 308 Section 8 I/O Ports Table 8.7 summarizes the states of the input pull-ups in each operating mode. Table 8.7 Input Pull-Up Transistor States (Port 4) Hardware Software Mode Reset Standby Mode Standby Mode Other Modes 1 to 5 8-bit bus mode On/off On/off 16-bit bus mode...
Page 309: Port 5
Section 8 I/O Ports Port 5 8.6.1 Overview Port 5 is a 4-bit input/output port with the pin configuration shown in figure 8.5. The pin functions differ depending on the operating mode. In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 5 consists of address output pins (A to A ).
Page 310: Register Descriptions
Section 8 I/O Ports 8.6.2 Register Descriptions Table 8.8 summarizes the registers of port 5. Table 8.8 Port 5 Registers Initial Value Address* Name Abbreviation R/W Modes 1 to 4 Modes 5 to 7 H'EE004 Port 5 data direction register P5DDR H'FF H'F0...
Page 311 Section 8 I/O Ports In modes 5 to 7, P5DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P5DDR is initialized to H'FF in modes 1 to 4, and to H'F0 in modes 5 to 7, by a reset and in hardware standby mode.
Page 312 Section 8 I/O Ports In modes 5 to 7, when a P5DDR bit is cleared to 0 (selecting generic input), if the corresponding bit in P5PCR is set to 1, the input pull-up transistor is turned on. P5PCR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting.
Page 313: Port 6
Section 8 I/O Ports Port 6 8.7.1 Overview Port 6 is an 8-bit input/output port that is also used for input and output of bus control signals (LWR, HWR, RD, AS, BACK, BREQ, WAIT) and for clock (φ) output. (generic input)/φ, LWR, HWR, RD, In modes 1 to 5 (expanded modes), the pin functions are P6 AS, P6 /BACK, P6...
Page 314: Register Descriptions
Section 8 I/O Ports 8.7.2 Register Descriptions Table 8.10 summarizes the registers of port 6. Table 8.10 Port 6 Registers Address* Name Abbreviation Initial Value H'EE005 Port 6 data direction register P6DDR H'80 H'FFFD5 Port 6 data register P6DR H'80 Note: * Lower 20 bits of the address in advanced mode.
Page 315 Section 8 I/O Ports becomes an output port if the corresponding bit of P6 DDR to P6 DDR is set to 1, and an input port if this pin is cleared to 0. P6DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P6DDR is initialized to H'80 by a reset and in hardware standby mode.
Page 316 Section 8 I/O Ports Table 8.11 Port 6 Pin Functions in Modes 1 to 5 Pin Functions and Selection Method /φ Bit PSTOP in MSTCRH selects the pin function. PSTOP φ output Pin function input Functions as LWR regardless of the setting of bit P6 LWR output* Pin function If any of bits DRAS2 to DRAS0 in DRCRA is 1 and bit CSEL in DRCRB is 1, LWR...
Page 317: Port 7
Section 8 I/O Ports Port 7 8.8.1 Overview Port 7 is an 8-bit input port that is also used for analog input to the A/D converter and analog output from the D/A converter. The pin functions are the same in all operating modes. Figure 8.7 shows the pin configuration of port 7.
Page 318: Register Description
Section 8 I/O Ports 8.8.2 Register Description Table 8.12 summarizes the port 7 register. Port 7 is an input port, and port 7 has no data direction register. Table 8.12 Port 7 Data Register Address* Name Abbreviation Initial Value H'FFFD6 Port 7 data register P7DR Undetermined...
Page 319: Port 8
Section 8 I/O Ports Port 8 8.9.1 Overview Port 8 is a 5-bit input/output port that is also used for CS to CS output, RFSH output, IRQ input, and A/D converter ADTRG input. Figure 8.8 shows the pin configuration of port 8. In modes 1 to 5 (expanded modes), port 8 can provide CS to CS output, RFSH output, IRQ...
Page 320: Register Descriptions
Section 8 I/O Ports Port 8 pins Pin functions in modes 1 to 5 (expanded modes) P8 / P8 (input)/ (output) P8 / IRQ / ADTRG P8 (input)/ (output)/ (input) / ADTRG (input) P8 / P8 (input)/ (output)/ (input) Port 8 P8 / P8 (input/output)/ CS (output)/IRQ...
Page 321 Section 8 I/O Ports Port 8 Data Direction Register (P8DDR): P8DDR is an 8-bit write-only register that can select input or output for each pin in port 8. Bits 7 to 5 are reserved. They are fixed at 1, and cannot be modified. ...
Page 322 Section 8 I/O Ports Port 8 Data Register (P8DR): P8DR is an 8-bit readable/writable register that stores output data for port 8. When port 8 functions as an output port, the value of this register is output. When a bit in P8DDR is set to 1, if port 8 is read the value of the corresponding P8DR bit is returned.
Page 323 Section 8 I/O Ports Table 8.14 Port 8 Pin Functions in Modes 1 to 5 Pin Functions and Selection Method Bit P8 DDR selects the pin function as follows Pin function input output /IRQ /ADTRG Bit P8 DDR selects the pin function as follows Pin function input output...
Page 324 Section 8 I/O Ports Table 8.15 Port 8 Pin Functions in Mode 6 and 7 Pin Functions and Selection Method Bit P8 DDR selects the pin function as follows Pin function input output /IRQ /ADTRG Bit P8 DDR selects the pin function as follows Pin function input output...
Page 325: Port 9
Section 8 I/O Ports 8.10 Port 9 8.10.1 Overview Port 9 is a 6-bit input/output port that is also used for input and output (TxD , TxD , RxD , RxD ) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for IRQ , SCK and IRQ input.
Page 326: Register Descriptions
Section 8 I/O Ports 8.10.2 Register Descriptions Table 8.16 summarizes the registers of port 9. Table 8.16 Port 9 Registers Address* Name Abbreviation Initial Value H'EE008 Port 9 data direction register P9DDR H'C0 H'FFFD8 Port 9 data register P9DR H'C0 Note: * Lower 20 bits of the address in advanced mode.
Page 327 Section 8 I/O Ports Port 9 Data Register (P9DR): P9DR is an 8-bit readable/writable register that stores output data for port 9. When port 9 functions as an output port, the value of this register is output. When a bit in P9DDR is set to 1, if port 9 is read the value of the corresponding P9DR bit is returned.
Page 328 Section 8 I/O Ports Table 8.17 Port 9 Pin Functions Pin Functions and Selection Method /SCK /IRQ Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR, and bit P9 DDR select the pin function as follows CKE1 —...
Page 329 Section 8 I/O Ports Pin Functions and Selection Method /TxD Bit TE in SCR of SCI1, bit SMIF in SCMR, and bit P9 DDR select the pin function as follows. SMIF — — — Pin function input output output output* Note: * Functions as the TxD output pin, but there are two states: one in which the pin is...
Page 330: Port A
Section 8 I/O Ports 8.11 Port A 8.11.1 Overview Port A is an 8-bit input/output port that is also used for output (TP to TP ) from the programmable timing pattern controller (TPC), input and output, (TIOCB , TIOCA , TIOCB , TIOCA , TIOCB TIOCA...
Page 331 Section 8 I/O Ports Port A pins PA /TP /TIOCB /A PA /TP /TIOCA /A PA /TP /TIOCB /A PA /TP /TIOCA /A Port A PA /TP /TIOCB /TCLKD PA /TP /TIOCA /TCLKC PA /TP /TEND /TCLKB PA /TP /TEND /TCLKA Pin functions in modes 1, 2, 6 and 7 PA (input/output)/TP (output)/TIOCB (input/output) PA (input/output)/TP (output)/TIOCA (input/output)
Page 332: Register Descriptions
Section 8 I/O Ports 8.11.2 Register Descriptions Table 8.18 summarizes the registers of port A. Table 8.18 Port A Registers Initial Value Address* Name Modes 1, 2, 5, 6 and 7 Modes 3, 4 H'EE009 Port A data direction PADDR H'00 H'80 register...
Page 333 Section 8 I/O Ports PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1, 2, 5, 6, and 7. It is initialized to H'80 by a reset and in hardware standby mode in modes 3 and 4. In software standby mode it retains its previous setting.
Page 334 Section 8 I/O Ports Table 8.19 Port A Pin Functions (Modes 1, 2, 6, 7) Pin Functions and Selection Method PA 7 /TP 7 / Bit PWM2 in TMDR, bits IOB2 to IOB0 in TIOR2, bit NDER7 in NDERA, and bit PA 7 DDR select the pin TIOCB function as follows.
Page 335 Section 8 I/O Ports Pin Functions and Selection Method Bit PWM1 in TMDR, bits IOB2 to IOB0 in TIOR1, bit NDER5 in NDERA, and bit PA DDR select the pin TIOCB function as follows. 16-bit timer channel 1 settings (1) in table below (2) in table below —...
Page 336 Section 8 I/O Ports Table 8.20 Port A Pin Functions (Modes 3, 4, 5) Pin Functions and Selection Method Modes 3 and 4: Always used as A output. TIOCB Pin function output Mode 5: Bit PWM2 in TMDR, bits IOB2 to IOB0 in TIOR2, bit NDER7 in NDERA, bit A20E in BRCR, and bit PA select the pin function as follows.
Page 337 Section 8 I/O Ports Pin Functions and Selection Method Bit PWM1 in TMDR, bits IOB2 to IOB0 in TIOR1, bit NDER5 in NDERA, bit A22E in BRCR, and bit PA TIOCB select the pin function as follows. A22E 16-bit timer channel 1 settings (1) in table below (2) in table below...
Page 338 Section 8 I/O Ports Table 8.21 Port A Pin Functions (Modes 1 to 7) Pin Functions and Selection Method Bit PWM0 in TMDR, bits IOB2 to IOB0 in TIOR0, bits TPSC2 to TPSC0 in TCR2 to TCR0 of the 16-bit timer, TIOCB bits CKS2 to CKS0 in TCR3 of the 8-bit timer, bit NDER3 in NDERA, and bit PA DDR select the pin function...
Page 339 Section 8 I/O Ports Pin Functions and Selection Method Bit PWM0 in TMDR, bits IOA2 to IOA0 in TIOR0, bits TPSC2 to TPSC0 in TCR2 to TCR0 of the 16-bit timer, TIOCA bits CKS2 to CKS0 in TCR1 of the 8-bit timer, bit NDER2 in NDERA, and bit PA DDR select the pin function TCLKC as follows.
Page 340 Section 8 I/O Ports Pin Functions and Selection Method Bit MDF in TMDR, bits TPSC2 to TPSC0 in TCR2 to TCR0 of the 16-bit timer, bits CKS2 to CKS0 in TCR2 of TCLKB/ the 8-bit timer, bit NDER1 in NDERA, and bit PA DDR select the pin function as follows.
Page 341: Port B
Section 8 I/O Ports 8.12 Port B 8.12.1 Overview Port B is an 8-bit input/output port that is also used for output (TP to TP ) from the programmable timing pattern controller (TPC), input/output (TMIO , TMO , TMIO , TMO ) by the 8-bit timer, CS to CS...
Page 342 Section 8 I/O Ports Port B pins /RxD /TxD /SCK /LCAS /UCAS Port B /TMIO /DREQ /TMO /TP /TMIO /DREQ /TP /TMO Pin functions in modes 1 to 5 (input/output)/TP (output) /RxD (input) (input/output)/TP (output) /TxD (output) (input/output)/TP (output) /SCK (input/output) /LCAS (output) (input/output)/TP (output) /UCAS (output)
Page 343: Register Descriptions
Section 8 I/O Ports 8.12.2 Register Descriptions Table 8.22 summarizes the registers of port B. Table 8.22 Port B Registers Address* Name Abbreviation Initial Value H'EE00A Port B data direction register PBDDR H'00 H'FFFDA Port B data register PBDR H'00 Note: * Lower 20 bits of the address in advanced mode.
Page 344 Section 8 I/O Ports Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores output data for pins port B. When port B functions as an output port, the value of this register is output. When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is returned. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin logic level is read.
Page 345 Section 8 I/O Ports Table 8.23 Port B Pin Functions (Modes 1 to 5) Pin Functions and Selection Method Bit RE in SCR of SCI2, bit SMIF in SCMR, bit NDER15 in NDERB, and bit PB DDR select the pin function as follows.
Page 346 Section 8 I/O Ports Pin Functions and Selection Method The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and OS1/0 in TCSR3, bits TMIO CCLR1 and CCLR0 in TCR3, bit CS4E in CSCR, bit NDER11 in NDERB, and bit PB DDR select the pin DREQ function as follows.
Page 347 Section 8 I/O Ports Pin Functions and Selection Method Bits OIS3/2 and OS1/0 in TCSR1, bits CCLR1 and CCLR0 in TCR1, bit CS6E in CSCR, bit NDER9 in TMIO NDERB, and bit PB DDR select the pin function as follows. DREQ OIS3/2 and OS1/0 All 0...
Page 348 Section 8 I/O Ports Table 8.24 Port B Pin Functions (Modes 6 to 7) Pin Functions and Selection Method Bit RE in SCR of SCI2, bit SMIF in SCMR, bit NDER15 in NDERB, and bit PB DDR select the pin function as follows.
Page 349 Section 8 I/O Ports Pin Functions and Selection Method Bits OIS3/2 and OS1/0 in TCSR3, bits CCLR1 and CCLR0 in TCR3, bit NDER11 in NDERB, and bit PB TMIO select the pin function as follows. DREQ OIS3/2 and OS1/0 All 0 Not all 0 —...
Page 350 Section 8 I/O Ports Rev. 4.00 Jan 26, 2006 page 326 of 938 REJ09B0276-0400...
Page 351: Section 9 16-Bit Timer
Section 9 16-Bit Timer Section 9 16-Bit Timer Overview The H8/3067 Group has built-in 16-bit timer module with three 16-bit counter channels. 9.1.1 Features 16-bit timer features are listed below. • Capability to process up to 6 pulse outputs or 6 pulse inputs •...
Page 352 Section 9 16-Bit Timer • Nine interrupt sources Each channel has two compare match/input capture interrupts and an overflow interrupt. All interrupts can be requested independently. • Output triggering of programmable timing pattern controller (TPC) Compare match/input capture signals from channels 0 to 2 can be used as TPC output triggers. Rev.
Page 353 Section 9 16-Bit Timer Table 9.1 summarizes the 16-bit timer functions. Table 9.1 16-bit timer Functions Item Channel 0 Channel 1 Channel 2 Internal clocks: φ, φ/2, φ/4, φ/8 Clock sources External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable independently General registers (output GRA0, GRB0 GRA1, GRB1 GRA2, GRB2...
Page 354: Block Diagrams
Section 9 16-Bit Timer 9.1.2 Block Diagrams 16-bit timer Block Diagram (Overall): Figure 9.1 is a block diagram of the 16-bit timer. IMIA0 to IMIA2 TCLKA to TCLKD Clock selector IMIB0 to IMIB2 φ, φ/2, φ/4, φ/8 OVI0 to OVI2 Control logic TIOCA to TIOCA...
Page 355 Section 9 16-Bit Timer Block Diagram of Channels 0 and 1: 16-bit timer channels 0 and 1 are functionally identical. Both have the structure shown in figure 9.2. TCLKA to TCLKD TIOCA Clock selector TIOCB φ, φ/2, φ/4, φ/8 Control logic IMIA0 Comparator IMIB0...
Page 356 Section 9 16-Bit Timer Block Diagram of Channel 2: Figure 9.3 is a block diagram of channel 2 TCLKA to TCLKD TIOCA Clock selector TIOCB φ, φ/2, φ/4, φ/8 Control logic IMIA2 Comparator IMIB2 OVI2 Module data bus Legend TCNT2: Timer counter 2 (16 bits) GRA2, GRB2: General registers A2 and B2 (input capture/output compare registers)
Page 357: Input/Output Pins
Section 9 16-Bit Timer 9.1.3 Input/Output Pins Table 9.2 summarizes the 16-bit timer pins. Table 9.2 16-bit timer Pins Abbre- Input/ Channel Name viation Output Function Common Clock input A TCLKA Input External clock A input pin (phase-A input pin in phase counting mode) Clock input B TCLKB Input...
Page 358: Register Configuration
Section 9 16-Bit Timer 9.1.4 Register Configuration Table 9.3 summarizes the 16-bit timer registers. Table 9.3 16-bit timer Registers Abbre- Initial Address * Channel Name viation Value Common H'FFF60 Timer start register TSTR H'F8 H'FFF61 Timer synchro register TSNC H'F8 H'FFF62 Timer mode register TMDR...
Page 359 Section 9 16-Bit Timer Abbre- Initial Address * Channel Name viation Value H'FFF78 Timer control register 2 TCR2 H'80 H'FFF79 Timer I/O control register 2 TIOR2 H'88 H'FFF7A Timer counter 2H TCNT2H H'00 H'FFF7B Timer counter 2L TCNT2L H'00 H'FFF7C General register A2H GRA2H H'FF...
Page 360: Register Descriptions
Section 9 16-Bit Timer Register Descriptions 9.2.1 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that starts and stops the timer counter (TCNT) in channels 0 to 2.      STR2 STR1 STR0 Initial value ...
Page 361: Timer Synchro Register (Tsnc)
Section 9 16-Bit Timer Bit 0—Counter Start 0 (STR0): Starts and stops timer counter 0 (TCNT0). Bit 0 STR0 Description TCNT0 is halted (Initial value) TCNT0 is counting 9.2.2 Timer Synchro Register (TSNC) TSNC is an 8-bit readable/writable register that selects whether channels 0 to 2 operate independently or synchronously.
Page 362 Section 9 16-Bit Timer Bit 1—Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or synchronously. Bit 1 SYNC1 Description Channel 1’s timer counter (TCNT1) operates independently (Initial value) TCNT1 is preset and cleared independently of other channels Channel 1 operates synchronously TCNT1 can be synchronously preset and cleared Bit 0—Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or synchronously.
Page 363: Timer Mode Register (Tmdr)
Section 9 16-Bit Timer 9.2.3 Timer Mode Register (TMDR) TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 2. It also selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2. ...
Page 364 Section 9 16-Bit Timer When MDF is set to 1 to select phase counting mode, TCNT2 operates as an up/down-counter and pins TCLKA and TCLKB become counter clock input pins. TCNT2 counts both rising and falling edges of TCLKA and TCLKB, and counts up or down as follows. Counting Direction Down-Counting Up-Counting...
Page 365 Section 9 16-Bit Timer Bit 1—PWM Mode 1 (PWM1): Selects whether channel 1 operates normally or in PWM mode. Bit 1 PWM1 Description Channel 1 operates normally (Initial value) Channel 1 operates in PWM mode When bit PWM1 is set to 1 to select PWM mode, pin TIOCA becomes a PWM output pin.
Page 366: Timer Interrupt Status Register A (Tisra)
Section 9 16-Bit Timer 9.2.4 Timer Interrupt Status Register A (TISRA) TISRA is an 8-bit readable/writable register that indicates GRA compare match or input capture and enables or disables general register compare match and input capture interrupt requests.   IMIEA2 IMIEA1 IMIEA0...
Page 367 Section 9 16-Bit Timer Bit 5—Input Capture/Compare Match Interrupt Enable A1 (IMIEA1): Enables or disables the interrupt requested by the IMFA1 flag when IMFA1 is set to 1. Bit 5 IMIEA1 Description IMIA1 interrupt requested by IMFA1 flag is disabled (Initial value) IMIA1 interrupt requested by IMFA1 flag is enabled Bit 4—Input Capture/Compare Match Interrupt Enable A0 (IMIEA0): Enables or disables...
Page 368 Section 9 16-Bit Timer Bit 1—Input Capture/Compare Match Flag A1 (IMFA1): This status flag indicates GRA1 compare match or input capture events. Bit 1 IMFA1 Description [Clearing conditions] (Initial value) Read IMFA1 when IMFA1 =1, then write 0 in IMFA1. DMAC activated by IMIA1 interrupt.
Page 369: Timer Interrupt Status Register B (Tisrb)
Section 9 16-Bit Timer 9.2.5 Timer Interrupt Status Register B (TISRB) TISRB is an 8-bit readable/writable register that indicates GRB compare match or input capture and enables or disables general register compare match and input capture interrupt requests.   IMIEB2 IMIEB1 IMIEB0...
Page 370 Section 9 16-Bit Timer Bit 5—Input Capture/Compare Match Interrupt Enable B1 (IMIEB1): Enables or disables the interrupt requested by the IMFB1 flag when IMFB1 is set to 1. Bit 5 IMIEB1 Description IMIB1 interrupt requested by IMFB1 flag is disabled (Initial value) IMIB1 interrupt requested by IMFB1 flag is enabled Bit 4—Input Capture/Compare Match Interrupt Enable B0 (IMIEB0): Enables or disables...
Page 371 Section 9 16-Bit Timer Bit 1—Input Capture/Compare Match Flag B1 (IMFB1): This status flag indicates GRB1 compare match or input capture events. Bit 1 IMFB1 Description [Clearing condition] (Initial value) Read IMFB1 when IMFB1 =1, then write 0 in IMFB1. [Setting conditions] TCNT1 = GRB1 when GRB1 functions as an output compare register.
Page 372: Timer Interrupt Status Register C (Tisrc)
Section 9 16-Bit Timer 9.2.6 Timer Interrupt Status Register C (TISRC) TISRC is an 8-bit readable/writable register that indicates TCNT overflow or underflow and enables or disables overflow interrupt requests.   OVIE2 OVIE1 OVIE0 OVF2 OVF1 OVF0 Initial value ...
Page 373 Section 9 16-Bit Timer Bit 5—Overflow Interrupt Enable 1 (OVIE1): Enables or disables the interrupt requested by the OVF1 flag when OVF1 is set to 1. Bit 5 OVIE1 Description OVI1 interrupt requested by OVF1 flag is disabled (Initial value) OVI1 interrupt requested by OVF1 flag is enabled Bit 4—Overflow Interrupt Enable 0 (OVIE0): Enables or disables the interrupt requested by the OVF0 flag when OVF0 is set to 1.
Page 374: Timer Counters (Tcnt)
Section 9 16-Bit Timer Bit 0—Overflow Flag 0 (OVF0): This status flag indicates TCNT0 overflow. Bit 0 OVF0 Description [Clearing condition] (Initial value) Read OVF0 when OVF0 =1, then write 0 in OVF0. [Setting condition] TCNT0 overflowed from H'FFFF to H'0000. 9.2.7 Timer Counters (TCNT) TCNT is a 16-bit counter.
Page 375: General Registers (Gra, Grb)
Section 9 16-Bit Timer The TCNTs are linked to the CPU by an internal 16-bit bus and can be written or read by either word access or byte access. Each TCNT is initialized to H'0000 by a reset and in standby mode. 9.2.8 General Registers (GRA, GRB) The general registers are 16-bit registers.
Page 376: Timer Control Registers (Tcr)
Section 9 16-Bit Timer 9.2.9 Timer Control Registers (TCR) TCR is an 8-bit register. The 16-bit timer has three TCRs, one in each channel. Channel Abbreviation Function TCR0 CR controls the timer counter. The TCRs in all channels are functionally identical. When phase counting mode is TCR1 selected in channel 2, the settings of bits CKEG1 and TCR2...
Page 377 Section 9 16-Bit Timer Bits 6 and 5—Counter Clear 1/0 (CCLR1, CCLR0): These bits select how TCNT is cleared. Bit 6 Bit 5 CCLR1 CCLR0 Description TCNT is not cleared (Initial value) TCNT is cleared by GRA compare match or input capture * TCNT is cleared by GRB compare match or input capture * Synchronous clear: TCNT is cleared in synchronization with other synchronized timers *...
Page 378: Timer I/O Control Register (Tior)
Section 9 16-Bit Timer Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock source. Bit 2 Bit 1 Bit 0 TPSC2 TPSC1 TPSC0 Function Internal clock: φ (Initial value) Internal clock: φ/2 Internal clock: φ/4 Internal clock: φ/8 External clock A: TCLKA input...
Page 379 Section 9 16-Bit Timer   IOB2 IOB1 IOB0 IOA2 IOA1 IOA0 Initial value   Read/Write I/O control A2 to A0 These bits select GRA functions Reserved bit I/O control B2 to B0 These bits select GRB functions Reserved bit Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture function for GRA and GRB, and specifies the functions of the TIORA and TIORC pins.
Page 380: Timer Output Level Setting Register C (Tolr)
Section 9 16-Bit Timer Bit 3—Reserved: This bit cannot be modified and is always read as 1. Bits 2 to 0—I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function. Bit 2 Bit 1 Bit 0 IOA2 IOA1 IOA0...
Page 381 Section 9 16-Bit Timer Bits 7 and 6—Reserved: These bits cannot be modified. Bit 5—Output Level Setting B2 (TOB2): Sets the value of timer output TIOCB Bit 5 TOB2 Description TIOCB is 0 (Initial value) TIOCB is 1 Bit 4—Output Level Setting A2 (TOA2): Sets the value of timer output TIOCA Bit 4 TOA2 Description...
Page 382 Section 9 16-Bit Timer Bit 0—Output Level Setting A0 (TOA0): Sets the value of timer output TIOCA Bit 0 TOA0 Description TIOCA is 0 (Initial value) TIOCA is 1 Rev. 4.00 Jan 26, 2006 page 358 of 938 REJ09B0276-0400...
Page 383: Cpu Interface
Section 9 16-Bit Timer CPU Interface 9.3.1 16-Bit Accessible Registers The timer counters (TCNTs), general registers A and B (GRAs and GRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data bus. These registers can be written or read a word at a time, or a byte at a time.
Page 384 Section 9 16-Bit Timer On-chip data bus Module Bus interface data bus TCNTH TCNTL Figure 9.6 Access to Timer Counter (CPU Writes to TCNT, Upper Byte) On-chip data bus Module Bus interface data bus TCNTH TCNTL Figure 9.7 Access to Timer Counter (CPU Writes to TCNT, Lower Byte) On-chip data bus Module Bus interface...
Page 385: 8-Bit Accessible Registers
Section 9 16-Bit Timer On-chip data bus Module Bus interface data bus TCNTH TCNTL Figure 9.9 Access to Timer Counter (CPU Reads TCNT, Lower Byte) 9.3.2 8-Bit Accessible Registers The registers other than the timer counters, general registers, and buffer registers are 8-bit registers.
Page 386: Operation
Section 9 16-Bit Timer On-chip data bus Module Bus interface data bus Figure 9.11 TCR Access (CPU Reads TCR) Operation 9.4.1 Overview A summary of operations in the various modes is given below. Normal Operation: Each channel has a timer counter and general registers. The timer counter counts up, and can operate as a free-running counter, periodic counter, or external event counter.
Page 387: Basic Functions
Section 9 16-Bit Timer 9.4.2 Basic Functions Counter Operation: When one of bits STR0 to STR2 is set to 1 in the timer start register (TSTR), the timer counter (TCNT) in the corresponding channel starts counting. The counting can be free- running or periodic.
Page 388 Section 9 16-Bit Timer 2. For periodic counting, set CCLR1 and CCLR0 in TCR to have TCNT cleared at GRA compare match or GRB compare match. 3. Set TIOR to select the output compare function of GRA or GRB, whichever was selected in step 2.
Page 389 Section 9 16-Bit Timer TCNT value Counter cleared by general register compare match H'0000 Time STR bit Figure 9.14 Periodic Counter Operation • TCNT count timing  Internal clock source Bits TPSC2 to TPSC0 in TCR select the system clock (φ) or one of three internal clock sources obtained by prescaling the system clock (φ/2, φ/4, φ/8).
Page 390 Section 9 16-Bit Timer φ External clock input TCNT input N − 1 N + 1 TCNT Figure 9.16 Count Timing for External Clock Sources (when Both Edges are Detected) Waveform Output by Compare Match: In 16-bit timer channels 0, 1 compare match A or B can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle.
Page 391 Section 9 16-Bit Timer TCNT value H'FFFF H'0000 Time TIOCB No change No change 1 output No change No change 0 output TIOCA Figure 9.18 0 and 1 Output (TOA = 1, TOB = 0) Figure 9.19 shows examples of toggle output. TCNT operates as a periodic counter, cleared by compare match B.
Page 392 Section 9 16-Bit Timer • Output compare output timing The compare match signal is generated in the last state in which TCNT and the general register match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the output compare pin (TIOCA or TIOCB).
Page 393 Section 9 16-Bit Timer • Sample setup procedure for input capture Figure 9.21 shows a sample procedure for setting up input capture. Input selection Set TIOR to select the input capture function of a general register and the rising edge, falling edge, or both edges of the input capture signal.
Page 394 Section 9 16-Bit Timer • Input capture signal timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in TIOR. Figure 9.23 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges.
Page 395: Synchronization
Section 9 16-Bit Timer 9.4.3 Synchronization The synchronization function enables two or more timer counters to be synchronized by writing the same data to them simultaneously (synchronous preset). With appropriate TCR settings, two or more timer counters can also be cleared simultaneously (synchronous clear). Synchronization enables additional general registers to be associated with a single time base.
Page 396 Section 9 16-Bit Timer Example of Synchronization: Figure 9.25 shows an example of synchronization. Channels 0, 1, and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by compare match with GRB0.
Page 397: Pwm Mode
Section 9 16-Bit Timer 9.4.4 PWM Mode In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin. GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which the PWM output changes to 0.
Page 398 Section 9 16-Bit Timer Sample Setup Procedure for PWM Mode: Figure 9.26 shows a sample procedure for setting up PWM mode. PWM mode 1. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in TCR to Select counter clock select the desired edge(s) of the...
Page 399 Section 9 16-Bit Timer Examples of PWM Mode: Figure 9.27 shows examples of operation in PWM mode. In PWM mode TIOCA becomes an output pin. The output goes to 1 at compare match with GRA, and to 0 at compare match with GRB. In the examples shown, TCNT is cleared by compare match with GRA or GRB.
Page 400 Section 9 16-Bit Timer Figure 9.28 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%. If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB, the duty cycle is 0%.
Page 401: Phase Counting Mode
Section 9 16-Bit Timer 9.4.5 Phase Counting Mode In phase counting mode the phase difference between two external clock inputs (at the TCLKA and TCLKB pins) is detected, and TCNT2 counts up or down accordingly. In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock input pins and TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to TPSC0, CKEG1, and CKEG0 in TCR2.
Page 402 Section 9 16-Bit Timer Example of Phase Counting Mode: Figure 9.30 shows an example of operations in phase counting mode. Table 9.5 lists the up-counting and down-counting conditions for TCNT2. In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must also be at least 1.5 states, and the pulse width must be at least 2.5 states.
Page 403: Setting Initial Value Of 16-Bit Timer Output
Section 9 16-Bit Timer 9.4.6 Setting Initial Value of 16-Bit Timer Output Any desired value can be specified for the initial 16-bit timer output value when a timer count operation is started by making a setting in TOLR. Figure 9.32 shows the timing for setting the initial output value with TOLR. Only write to TOLR when the corresponding bit in TSTR is cleared to 0.
Page 404: Interrupts
Section 9 16-Bit Timer Interrupts The 16-bit timer has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 9.5.1 Setting of Status Flags Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a compare match signal generated when TCNT matches a general register (GR).
Page 405 Section 9 16-Bit Timer Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an input capture signal. The TCNT contents are simultaneously transferred to the corresponding general register. Figure 9.34 shows the timing. φ...
Page 406: Timing Of Clearing Of Status Flags
Section 9 16-Bit Timer Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when TCNT overflows from H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 9.35 shows the timing. φ TCNT Overflow signal Figure 9.35 Timing of Setting of OVF 9.5.2 Timing of Clearing of Status Flags If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is...
Page 407: Interrupt Sources And Dma Controller Activation
Section 9 16-Bit Timer 9.5.3 Interrupt Sources and DMA Controller Activation Each 16-bit timer channel can generate a compare match/input capture A interrupt, a compare match/input capture B interrupt, and an overflow interrupt. In total there are nine interrupt sources of three kinds, all independently vectored.
Page 408: Usage Notes
Section 9 16-Bit Timer Usage Notes This section describes contention and other matters requiring special attention during 16-bit timer operations. Contention between TCNT Write and Clear: If a counter clear signal occurs in the T state of a TCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure 9.37.
Page 409 Section 9 16-Bit Timer Contention between TCNT Word Write and Increment: If an increment pulse occurs in the T state of a TCNT word write cycle, writing takes priority and TCNT is not incremented. Figure 9.38 shows the timing in this case. TCNT word write cycle φ...
Page 410 Section 9 16-Bit Timer Contention between TCNT Byte Write and Increment: If an increment pulse occurs in the T or T state of a TCNT byte write cycle, writing takes priority and TCNT is not incremented. The TCNT byte that was not written retains its previous value. See figure 9.39, which shows an increment pulse occurring in the T state of a byte write to TCNTH.
Page 411 Section 9 16-Bit Timer Contention between General Register Write and Compare Match: If a compare match occurs in the T state of a general register write cycle, writing takes priority and the compare match signal is inhibited. See figure 9.40. General register write cycle φ...
Page 412 Section 9 16-Bit Timer Contention between TCNT Write and Overflow or Underflow: If an overflow occurs in the T state of a TCNT write cycle, writing takes priority and the counter is not incremented. OVF is set to 1.The same holds for underflow. See figure 9.41. TCNT write cycle φ...
Page 413 Section 9 16-Bit Timer Contention between General Register Read and Input Capture: If an input capture signal occurs during the T state of a general register read cycle, the value before input capture is read. See figure 9.42. General register read cycle φ...
Page 414 Section 9 16-Bit Timer Contention between Counter Clearing by Input Capture and Counter Increment: If an input capture signal and counter increment signal occur simultaneously, the counter is cleared according to the input capture signal. The counter is not incremented by the increment signal.The counter is not incremented by the increment signal.
Page 415 Section 9 16-Bit Timer Contention between General Register Write and Input Capture: If an input capture signal occurs in the T state of a general register write cycle, input capture takes priority and the write to the general register is not performed. See figure 9.44. General register write cycle φ...
Page 416 Section 9 16-Bit Timer Note on Writes in Synchronized Operation: When channels are synchronized, if a TCNT value is modified by byte write access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. (Example) When channels 1 and 2 are synchronized •...
Page 417 Section 9 16-Bit Timer 16-bit timer Operating Modes: Table 9.7 (a)16-bit timer Operating Modes (Channel 0) Register Settings TSNC TMDR TIOR0 TCR0 Synchro- Clear Clock Operating Mode nization FDIR PWM Select Select SYNC0 = 1   Synchronous preset  ...
Page 418 Section 9 16-Bit Timer Table 9.7 (b) 16-bit timer Operating Modes (Channel 1) Register Settings TSNC TMDR TIOR1 TCR1 Synchro- Clear Clock Operating Mode nization FDIR PWM Select Select SYNC1 = 1   Synchronous preset    PWM mode PWM1 = 1 ...
Page 419 Section 9 16-Bit Timer Table 9.7 (c) 16-bit timer Operating Modes (Channel 2) Register Settings TSNC TMDR TIOR2 TCR2 Synchro- Clear Clock Operating Mode nization FDIR PWM Select Select  Synchronous preset SYNC2 = 1   PWM mode PWM2 = 1 ...
Page 420 Section 9 16-Bit Timer Rev. 4.00 Jan 26, 2006 page 396 of 938 REJ09B0276-0400...
Page 421: Section 10 8-Bit Timers
Section 10 8-Bit Timers Section 10 8-Bit Timers 10.1 Overview The H8/3067 Group has a built-in 8-bit timer module with four channels (TMR0, TMR1, TMR2, and TMR3), based on 8-bit counters. Each channel has an 8-bit timer counter (TCNT) and two 8- bit time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare match events.
Page 422 Section 10 8-Bit Timers Two of the compare match sources and two of the combined compare match/input capture sources each have an independent interrupt vector. The remaining compare match interrupts, combined compare match/input capture interrupts, and overflow interrupts have one interrupt vector for two sources.
Page 423: Block Diagram
Section 10 8-Bit Timers 10.1.2 Block Diagram The 8-bit timers are divided into two groups of two channels each: group 0 comprising channels 0 and 1, and group 1 comprising channels 2 and 3. Figure 10.1 shows a block diagram of 8-bit timer group 0.
Page 424: Pin Configuration
Section 10 8-Bit Timers 10.1.3 Pin Configuration Table 10.1 summarizes the input/output pins of the 8-bit timer module. Table 10.1 8-Bit Timer Pins Group Channel Name Abbreviation I/O Input/output Timer output Output Compare match output Timer clock input TCLKC Input Counter external clock input Timer input/output TMIO Compare match output/input...
Page 425: Register Configuration
Section 10 8-Bit Timers 10.1.4 Register Configuration Table 10.2 summarizes the registers of the 8-bit timer module. Table 10.2 8-Bit Timer Registers Channel Address * Name Abbreviation R/W Initial value H’FFF80 Timer control register 0 TCR0 H’00 R/(W) * H’FFF82 Timer control/status register 0 TCSR0 H’00...
Page 426: Register Descriptions
Section 10 8-Bit Timers 10.2 Register Descriptions 10.2.1 Timer Counters (TCNT) TCNT0 TCNT1 Initial value Read/Write TCNT2 TCNT3 Initial value Read/Write The timer counters (TCNT) are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source. The clock source is selected by clock select bits 2 to 0 (CKS2 to CKS0) in the timer control register (TCR).
Page 427: Time Constant Registers A (Tcora)
Section 10 8-Bit Timers 10.2.2 Time Constant Registers A (TCORA) TCORA0 TCORA1 Initial value Read/Write TCORA2 TCORA3 Initial value Read/Write TCORA0 to TCORA3 are 8-bit readable/writable registers. The TCORA0 and TCORA1 pair, and the TCORA2 and TCORA3 pair, can each be accessed as a 16-bit register by word access. The TCORA value is constantly compared with the TCNT value.
Page 428: Time Constant Registers B (Tcorb)
Section 10 8-Bit Timers 10.2.3 Time Constant Registers B (TCORB) TCORB0 TCORB1 Initial value Read/Write TCORB2 TCORB3 Initial value Read/Write TCORB0 to TCORB3 are 8-bit readable/writable registers. The TCORB0 and TCORB1 pair, and the TCORB2 and TCORB3 pair, can each be accessed as a 16-bit register by word access. The TCORB value is constantly compared with the TCNT value.
Page 429: Timer Control Register (Tcr)
Section 10 8-Bit Timers 10.2.4 Timer Control Register (TCR) CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value Read/Write TCR is an 8-bit readable/writable register that selects the input clock source and the time at which TCNT is cleared, and enables interrupts. TCR is initialized to H'00 by a reset and in standby mode.
Page 430 Section 10 8-Bit Timers Bits 4 and 3—Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select how TCNT is cleared: by compare match A or B, or input capture B.. Bit 4 Bit 3 CCLR1 CCLR0 Description Clearing is disabled (Initial value) Cleared by compare match A Cleared by compare match B/ input capture B...
Page 431 Section 10 8-Bit Timers Bits 2 to 0—Clock Select 2 to 0 (CSK2 to CSK0): These bits select whether the clock input to TCNT is an internal or external clock. Three internal clocks can be selected, all divided from the system clock (φ): φ/8, φ/64, and φ/8192. The rising edge of the selected internal clock triggers the count.
Page 432: Timer Control/Status Registers (Tcsr)
Section 10 8-Bit Timers 10.2.5 Timer Control/Status Registers (TCSR) TCSR0 CMFB CMFA ADTE OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* TCSR2  CMFB CMFA OIS3 OIS2 Initial value  Read/Write R/(W)* R/(W)* R/(W)* TCSR1, TCSR3 CMFB CMFA OIS3 OIS2 Initial value Read/Write R/(W)*...
Page 433 Section 10 8-Bit Timers Bit 7—Compare Match/Input Capture Flag B (CMFB): Status flag that indicates the occurrence of a TCORB compare match or input capture. Bit 7 CMFB Description Clearing condition (Initial value) Read CMFB when CMFB = 1, then write 0 in CMFB Setting conditions TCNT = TCORB The TCNT value is transferred to TCORB by an input capture signal when...
Page 434 Section 10 8-Bit Timers Bit 4—A/D Trigger Enable (ADTE) (TCSR0): In combination with TRGE in the A/D control register (ADCR), enables or disables A/D converter start requests by compare match A or an external trigger. TCSR2 is a reserved bit, but can be read and written. Bit 4 TRGE* ADTE...
Page 435 Section 10 8-Bit Timers Bits 3 and 2—Output/Input Capture Edge Select B3 and B2 (OIS3, OIS2): In combination with the ICE bit in TCSR1 (TCSR3), these bits select the compare match B output level or the input capture input detected edge. The function of TCORB1 (TCORB3) depends on the setting of bit 4 of TCSR1 (TCSR3).
Page 436 Section 10 8-Bit Timers • If compare match A and B occur simultaneously, the output changes in accordance with the higher-priority compare match. • When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled. Rev.
Page 437: Cpu Interface
Section 10 8-Bit Timers 10.3 CPU Interface 10.3.1 8-Bit Registers TCNT, TCORA, TCORB, TCR, and TCSR are 8-bit registers. These registers are connected to the CPU by an internal 16-bit data bus and can be read and written a word at a time or a byte at a time. Figures 10.2 and 10.3 show the operation in word read and write accesses to TCNT.
Page 438 Section 10 8-Bit Timers Internal data bus Module data bus interface TCNT0 TCNT1 Figure 10.4 TCNT Access Operation (CPU Writes to TCNT, Upper Byte) Internal data bus Module data bus interface TCNT0 TCNT1 Figure 10.5 TCNT Access Operation (CPU Writes to TCNT, Lower Byte) Internal data bus Module data bus interface...
Page 439: Operation
Section 10 8-Bit Timers 10.4 Operation 10.4.1 TCNT Count Timing TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (φ/8, φ/64, or φ/8192) divided from the system clock (φ) can be selected, by setting bits CKS2 to CKS0 in TCR. Figure 10.8 shows the count timing.
Page 440: Compare Match Timing
Section 10 8-Bit Timers φ External clock input TCNT input clock N − 1 TCNT N + 1 Figure 10.9 Count Timing for External Clock Input (when Detecting the Both Edges) 10.4.2 Compare Match Timing Timer Output Timing: When compare match A or B occurs, the timer output is as specified by the OIS3, OIS2, OS1, and OS0 bits in TCSR (unchanged, 0 output, 1 output, or toggle output).
Page 441: Input Capture Signal Timing
Section 10 8-Bit Timers Clear by Compare Match: Depending on the setting of the CCLR1 and CCLR0 bits in TCR, TCNT can be cleared when compare match A or B occurs, Figure 10.11 shows the timing of this operation. φ Compare match signal TCNT H'00...
Page 442: Timing Of Status Flag Setting
Section 10 8-Bit Timers φ Input capture input Input capture signal TCNT TCORB Figure 10.13 Timing of Input Capture Input Signal 10.4.4 Timing of Status Flag Setting Timing of CMFA/CMFB Flag Setting when Compare Match Occurs: CMFA and CMFB in TCSR are set to 1 by the compare match signal output when the TCOR and TCNT values match.
Page 443: Operation With Cascaded Connection
Section 10 8-Bit Timers φ TCNT TCORB Input capture signal CMFB Figure 10.15 CMFB Flag Setting Timing when Input Capture Occurs Timing of Overflow Flag (OVF) Setting: The OVF flag in TCSR is set to 1 by the overflow signal generated when TCNT overflows (from H'FF to H'00). Figure 10.16 shows the timing in this case.
Page 444 Section 10 8-Bit Timers 16-Bit Count Mode • Channels 0 and 1: When bits CKS2 to CKS0 are set to B'100 in TCR0, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. ...
Page 445: Input Capture Setting
Section 10 8-Bit Timers  Setting when Input Capture Occurs • The CMFB flag is set to 1 in TCR2 and TCR3 when the ICE bit is 1 in TCSR3 and input capture occurs. • TMIO pin input capture input signal edge detection is selected by bits OIS3 and OIS2 in TCSR2.
Page 446 Section 10 8-Bit Timers Setting Input Capture Operation in 8-Bit Timer Mode (Normal Operation) • Channel 1:  Set TCORB1 as an 8-bit input capture register with the ICE bit in TCSR1.  Select rising edge, falling edge, or both edges as the input edge(s) for the input capture signal (TMIO ) with bits OIS3 and OIS2 in TCSR1.
Page 447: Interrupts
Section 10 8-Bit Timers 10.5 Interrupts 10.5.1 Interrupt Sources The 8-bit timer unit can generate three types of interrupt: compare match A and B (CMIA and CMIB) and overflow (OVI). Table 10.3 shows the interrupt sources and their priority order. Each interrupt source is enabled or disabled by the corresponding interrupt enable bit in TCR.
Page 448: A/D Converter Activation
Section 10 8-Bit Timers 10.5.2 A/D Converter Activation The A/D converter can only be activated by channel 0 compare match A. If the ADTE bit setting is 1 when the CMFA flag in TCSR0 is set to 1 by generation of channel 0 compare match A, an A/D conversion start request will be issued to the A/D converter.
Page 449: Usage Notes
Section 10 8-Bit Timers 10.7 Usage Notes Note that the following kinds of contention can occur in 8-bit timer operation. 10.7.1 Contention between TCNT Write and Clear If a timer counter clear signal occurs in the T state of a TCNT write cycle, clearing of the counter takes priority and the write is not performed.
Page 450: Contention Between Tcnt Write And Increment
Section 10 8-Bit Timers 10.7.2 Contention between TCNT Write and Increment If an increment pulse occurs in the T state of a TCNT write cycle, writing takes priority and TCNT is not incremented. Figure 10.19 shows the timing in this case. TCNT write cycle φ...
Page 451: Contention Between Tcor Write And Compare Match
Section 10 8-Bit Timers 10.7.3 Contention between TCOR Write and Compare Match If a compare match occurs in the T state of a TCOR write cycle, writing takes priority and the compare match signal is inhibited. Figure 10.20 shows the timing in this case. TCOR write cycle φ...
Page 452: Contention Between Tcor Read And Input Capture
Section 10 8-Bit Timers 10.7.4 Contention between TCOR Read and Input Capture If an input capture signal occurs in the T state of a TCOR read cycle, the value before input capture is read. Figure 10.21 shows the timing in this case. TCORB read cycle φ...
Page 453: Contention Between Counter Clearing By Input Capture And Counter Increment
Section 10 8-Bit Timers 10.7.5 Contention between Counter Clearing by Input Capture and Counter Increment If an input capture signal and counter increment signal occur simultaneously, counter clearing by the input capture signal takes priority and the counter is not incremented. The value before the counter is cleared is transferred to TCORB.
Page 454: Contention Between Tcor Write And Input Capture
Section 10 8-Bit Timers 10.7.6 Contention between TCOR Write and Input Capture If an input capture signal occurs in the T state of a TCOR write cycle, input capture takes priority and the write to TCOR is not performed. Figure 10.23 shows the timing in this case. TCOR write cycle φ...
Page 455: Contention Between Tcnt Byte Write And Increment In 16-Bit Count Mode (Cascaded Connection)
Section 10 8-Bit Timers 10.7.7 Contention between TCNT Byte Write and Increment in 16-Bit Count Mode (Cascaded Connection) If an increment pulse occurs in the T or T state of a TCNT byte write cycle in 16-bit count mode, writing takes priority and TCNT is not incremented. The TCNT byte that was not written retains its previous value.
Page 456: Contention Between Compare Matches A And B
Section 10 8-Bit Timers 10.7.8 Contention between Compare Matches A and B If compare matches A and B occur at the same time, the 8-bit timer operates according to the relative priority of the output states set for compare match A and compare match B, as shown in Table 10.5.
Page 457 Section 10 8-Bit Timers Table 10.6 Internal Clock Switchover and TCNT Operation CKS1 and CKS0 Write Timing TCNT Operation High → high switchover * Old clock source New clock source TCNT clock TCNT CKS bits rewritten High → low switchover * Old clock source New clock source TCNT clock...
Page 458 Section 10 8-Bit Timers CKS1 and CKS0 Write Timing TCNT Operation Low → low switchover Old clock source New clock source TCNT clock TCNT CKS bits rewritten Notes: 1. Including switchovers from a high clock source to the halted state, and from the halted state to a high clock source.
Page 459: Section 11 Programmable Timing Pattern Controller (Tpc)
Section 11 Programmable Timing Pattern Controller (TPC) Section 11 Programmable Timing Pattern Controller (TPC) 11.1 Overview The H8/3067 Group has a built-in programmable timing pattern controller (TPC) that provides pulse outputs by using the 16-bit timer as a time base. The TPC pulse outputs are divided into 4- bit groups (group 3 to group 0) that can operate simultaneously and independently.
Page 460: Block Diagram
Section 11 Programmable Timing Pattern Controller (TPC) 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the TPC. 16-bit timer compare match signals PADDR PBDDR NDERA NDERB Control logic TPMR TPCR Internal data bus Pulse output pins, group 3 PBDR NDRB Pulse output...
Page 461: Tpc Pins
Section 11 Programmable Timing Pattern Controller (TPC) 11.1.3 TPC Pins Table 11.1 summarizes the TPC output pins. Table 11.1 TPC Pins Name Symbol Function TPC output 0 Output Group 0 pulse output TPC output 1 Output TPC output 2 Output TPC output 3 Output TPC output 4...
Page 462: Registers
Section 11 Programmable Timing Pattern Controller (TPC) 11.1.4 Registers Table 11.2 summarizes the TPC registers. Table 11.2 TPC Registers Address * Name Abbreviation Function H'EE009 Port A data direction register PADDR H'00 R/(W) * H'FFFD9 Port A data register PADR H'00 H'EE00A Port B data direction register...
Page 463: Register Descriptions
Section 11 Programmable Timing Pattern Controller (TPC) 11.2 Register Descriptions 11.2.1 Port A Data Direction Register (PADDR) PADDR is an 8-bit write-only register that selects input or output for each pin in port A. PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR...
Page 464: Port B Data Direction Register (Pbddr)
Section 11 Programmable Timing Pattern Controller (TPC) 11.2.3 Port B Data Direction Register (PBDDR) PBDDR is an 8-bit write-only register that selects input or output for each pin in port B. Initial value Read/Write Port B direction 7 to 0 These bits select input or output for port B pins Port B is multiplexed with pins TP...
Page 465: Next Data Register A (Ndra)
Section 11 Programmable Timing Pattern Controller (TPC) 11.2.5 Next Data Register A (NDRA) NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups 1 and 0 (pins TP to TP ). During TPC output, when an 16-bit timer compare match event specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR.
Page 466 Section 11 Programmable Timing Pattern Controller (TPC) Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFFA5 and the address of the lower 4 bits (group 0) is H'FFFA7.
Page 467: Next Data Register B (Ndrb)
Section 11 Programmable Timing Pattern Controller (TPC) 11.2.6 Next Data Register B (NDRB) NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups 3 and 2 (pins TP to TP ). During TPC output, when an 16-bit timer compare match event specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR.
Page 468 Section 11 Programmable Timing Pattern Controller (TPC) Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFFA4 and the address of the lower 4 bits (group 2) is H'FFFA6.
Page 469: Next Data Enable Register A (Ndera)
Section 11 Programmable Timing Pattern Controller (TPC) 11.2.7 Next Data Enable Register A (NDERA) NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0 to TP ) on a bit-by-bit basis. NDER7 NDER6 NDER5 NDER4 NDER3 NDER2...
Page 470: Next Data Enable Register B (Nderb)
Section 11 Programmable Timing Pattern Controller (TPC) 11.2.8 Next Data Enable Register B (NDERB) NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2 to TP ) on a bit-by-bit basis. NDER15 NDER14 NDER13 NDER12 NDER11 NDER10...
Page 471: Tpc Output Control Register (Tpcr)
Section 11 Programmable Timing Pattern Controller (TPC) 11.2.9 TPC Output Control Register (TPCR) TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a group-by-group basis. G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 3 compare match select 1 and 0...
Page 472 Section 11 Programmable Timing Pattern Controller (TPC) Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits select the compare match event that triggers TPC output group 3 (TP to TP Bit 7 Bit 6 G3CMS1 G3CMS0 Description...
Page 473 Section 11 Programmable Timing Pattern Controller (TPC) Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match event that triggers TPC output group 1 (TP to TP Bit 3 Bit 2 G1CMS1 G1CMS0 Description...
Page 474: Tpc Output Mode Register (Tpmr)
Section 11 Programmable Timing Pattern Controller (TPC) 11.2.10 TPC Output Mode Register (TPMR) TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for each group.     G3NOV G2NOV G1NOV G0NOV Initial value  ...
Page 475 Section 11 Programmable Timing Pattern Controller (TPC) Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for group 3 (TP to TP Bit 3 G3NOV Description Normal TPC output in group 3 (output values change at (Initial value) compare match A in the selected 16-bit timer channel) Non-overlapping TPC output in group 3 (independent 1 and 0 output at compare match A and B in the selected 16-bit timer channel)
Page 476: Operation
Section 11 Programmable Timing Pattern Controller (TPC) 11.3 Operation 11.3.1 Overview When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents. When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit contents are transferred to PADR or PBDR to update the output values.
Page 477: Output Timing
Section 11 Programmable Timing Pattern Controller (TPC) 11.3.2 Output Timing If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output when the selected compare match event occurs. Figure 11.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. φ...
Page 478: Normal Tpc Output
Section 11 Programmable Timing Pattern Controller (TPC) 11.3.3 Normal TPC Output Sample Setup Procedure for Normal TPC Output: Figure 11.4 shows a sample procedure for setting up normal TPC output. Normal TPC output Select GR functions Set TIOR to make GRA an output compare register (with output inhibited).
Page 479 Section 11 Programmable Timing Pattern Controller (TPC) Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 11.5 shows an example in which the TPC is used for cyclic five-phase pulse output. TCNT value Compare match TCNT H'0000 Time NDRB PBDR •...
Page 480: Non-Overlapping Tpc Output
Section 11 Programmable Timing Pattern Controller (TPC) 11.3.4 Non-Overlapping TPC Output Sample Setup Procedure for Non-Overlapping TPC Output: Figure 11.6 shows a sample procedure for setting up non-overlapping TPC output. Non-overlapping TPC output Select GR functions Set TIOR to make GRA and GRB output compare registers (with output inhibited).
Page 481 Section 11 Programmable Timing Pattern Controller (TPC) Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non- Overlapping Output): Figure 11.7 shows an example of the use of TPC output for four-phase complementary non-overlapping pulse output. TCNT value TCNT H'0000 Time NDRB PBDR...
Page 482: Tpc Output Triggering By Input Capture
Section 11 Programmable Timing Pattern Controller (TPC) 11.3.5 TPC Output Triggering by Input Capture TPC output can be triggered by 16-bit timer input capture as well as by compare match. If GRA functions as an input capture register in the 16-bit timer channel selected in TPCR, TPC output will be triggered by the input capture signal.
Page 483: Usage Notes
Section 11 Programmable Timing Pattern Controller (TPC) 11.4 Usage Notes 11.4.1 Operation of TPC Output Pins to TP are multiplexed with 16-bit timer, DMAC, address bus, and other pin functions. When 16-bit timer, DMAC, or address output is enabled, the corresponding pins cannot be used for TPC output.
Page 484 Section 11 Programmable Timing Pattern Controller (TPC) Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin).
Page 485: Section 12 Watchdog Timer
Section 12 Watchdog Timer Section 12 Watchdog Timer 12.1 Overview The H8/3067 has an on-chip watchdog timer (WDT). The WDT has two selectable functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an interval timer.
Page 486: Block Diagram
Section 12 Watchdog Timer 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the WDT. Overflow Internal TCNT data bus Read/ Interrupt Interrupt signal write control (interval timer) control TCSR Internal clock sources φ/2 RSTCSR φ/32 φ/64 Reset Reset control Clock φ/128 (internal, external)
Page 487: Register Configuration
Section 12 Watchdog Timer 12.1.4 Register Configuration Table 12.2 summarizes the WDT registers. Table 12.2 WDT Registers Address * Write * Read Name Abbreviation Initial Value R/(W) * H'FFF8C H'FFF8C Timer control/status register TCSR H'18 H'FFF8D Timer counter TCNT H'00 R/(W) * H'FFF8E H'FFF8F Reset control/status register RSTCSR...
Page 488: Register Descriptions
Section 12 Watchdog Timer 12.2 Register Descriptions 12.2.1 Timer Counter (TCNT) TCNT is an 8-bit readable and writable up-counter. Initial value Read/Write Note: TCNT is write-protected by a password. For details see section 12.2.4, Notes on Register Access. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal clock source selected by bits CKS2 to CKS0 in TCSR.
Page 489: Timer Control/Status Register (Tcsr)
Section 12 Watchdog Timer 12.2.2 Timer Control/Status Register (TCSR) TCSR is an 8-bit readable and writable register. Its functions include selecting the timer mode and clock source.   WT/IT CKS2 CKS1 CKS0 Initial value   Read/Write R/(W) Clock select These bits select the TCNT clock source Reserved bits...
Page 490 Section 12 Watchdog Timer Bit 7—Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed from H'FF to H'00. Bit 7 Description [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 in OVF (Initial value) [Setting condition] Set when TCNT changes from H'FF to H'00...
Page 491: Reset Control/Status Register (Rstcsr)
Section 12 Watchdog Timer Bits 2 to 0—Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock sources, obtained by prescaling the system clock (φ), for input to TCNT. Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 Description...
Page 492 Section 12 Watchdog Timer Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3067 chip internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to initialize external system devices.
Page 493: Notes On Register Access
Section 12 Watchdog Timer 12.2.4 Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write. The procedures for writing and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte instructions.
Page 494 Section 12 Watchdog Timer Writing to RSTCSR: RSTCSR must be written by a word transfer instruction. It cannot be written by byte transfer instructions. Figure 12.3 shows the format of data written to RSTCSR. To write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte.
Page 495: Operation
Section 12 Watchdog Timer 12.3 Operation Operations when the WDT is used as a watchdog timer and as an interval timer are described below. 12.3.1 Watchdog Timer Operation Figure 12.4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1 in TCSR.
Page 496: Interval Timer Operation
Section 12 Watchdog Timer WDT overflow H'FF TME set to 1 TCNT count value H'00 OVF = 1 Start H'00 written Reset H'00 written in TCNT in TCNT Internal reset signal 518 states RESO 132 states Figure 12.4 Operation in Watchdog Timer Mode 12.3.2 Interval Timer Operation Figure 12.5 illustrates interval timer operation.
Page 497: Timing Of Setting Of Overflow Flag (Ovf)
Section 12 Watchdog Timer 12.3.3 Timing of Setting of Overflow Flag (OVF) Figure 12.6 shows the timing of setting of the OVF flag. The OVF flag is set to 1 when TCNT overflows. At the same time, a reset signal is generated in watchdog timer operation, or an interval timer interrupt is generated in interval timer operation.
Page 498: Timing Of Setting Of Watchdog Timer Reset Bit (Wrst)
Section 12 Watchdog Timer 12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR. Figure 12.7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is set to 1 when TCNT overflows and OVF is set to 1.
Page 499: Interrupts
Section 12 Watchdog Timer 12.4 Interrupts During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR. 12.5 Usage Notes Contention between TCNT Write and Increment: If a timer counter clock pulse is generated during the T state of a write cycle to TCNT, the write takes priority and the timer count is not incremented.
Page 500 Section 12 Watchdog Timer Rev. 4.00 Jan 26, 2006 page 476 of 938 REJ09B0276-0400...
Page 501: Section 13 Serial Communication Interface
Section 13 Serial Communication Interface Section 13 Serial Communication Interface 13.1 Overview The H8/3067 Group has a serial communication interface (SCI) with three independent channels. All three channels have identical functions. The SCI can communicate in both asynchronous and synchronous mode. It also has a multiprocessor communication function for serial communication among two or more processors.
Page 502 Section 13 Serial Communication Interface  Data length: 8 bits  Receive error detection: overrun errors • Full-duplex communication The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. The transmitting and receiving sections are both double-buffered, so serial data can be transmitted and received continuously.
Page 503: Block Diagram
Section 13 Serial Communication Interface 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the SCI. Module data bus Internal data bus φ Baud rate φ/ 4 SCMR generator φ/16 Transmit/receive φ/64 control Parity generate Clock Parity check External clock T E I T X I R X I...
Page 504: Input/Output Pins
Section 13 Serial Communication Interface 13.1.3 Input/Output Pins The SCI has serial pins for each channel as listed in table 13.1. Table 13.1 SCI Pins Channel Name Abbreviation Function Serial clock pin Input/output clock input/output Receive data pin Input receive data input Transmit data pin Output transmit data output...
Page 505: Register Configuration
Section 13 Serial Communication Interface 13.1.4 Register Configuration The SCI has internal registers as listed in table 13.2. These registers select asynchronous or synchronous mode, specify the data format and bit rate, control the transmitter and receiver sections, and specify switching between the serial communication interface and smart card interface.
Page 506: Register Descriptions
Section 13 Serial Communication Interface 13.2 Register Descriptions 13.2.1 Receive Shift Register (RSR) RSR is the register that receives serial data. Read/Write The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first, thereby converting the data to parallel data.
Page 507: Transmit Shift Register (Tsr)
Section 13 Serial Communication Interface 13.2.3 Transmit Shift Register (TSR) TSR is the register that transmits serial data. Read/Write The SCI loads transmit data from TDR to TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from TDR into TSR and starts transmitting it.
Page 508: Serial Mode Register (Smr)
Section 13 Serial Communication Interface 13.2.5 Serial Mode Register (SMR) SMR is an 8-bit register that specifies the SCI's serial communication format and selects the clock source for the baud rate generator. STOP CKS1 CKS0 Initial value Read/Write Clock select 1/0 These bits select the baud rate generator's clock source...
Page 509 Section 13 Serial Communication Interface Bit 7—Communication Mode (C/A A A A )/GSM Mode (GM): The function of this bit differs for the normal serial communication interface and for the smart card interface. Its function is switched with the SMIF bit in SCMR. For serial communication interface (SMIF bit in SCMR cleared to 0): Selects whether the SCI operates in asynchronous or synchronous mode.
Page 510 Section 13 Serial Communication Interface Bit 5—Parity Enable (PE): In asynchronous mode, this bit enables or disables the addition of a parity bit to transmit data, and the checking of the parity bit in receive data. In synchronous mode, the parity bit is neither added nor checked, regardless of the PE bit setting. Bit 5 Description Parity bit not added or checked...
Page 511 Section 13 Serial Communication Interface In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit. If the second stop bit is 0, it is treated as the start bit of the next incoming character.
Page 512: Serial Control Register (Scr)
Section 13 Serial Communication Interface 13.2.6 Serial Control Register (SCR) SCR register enables or disables the SCI transmitter and receiver, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source. MPIE TEIE CKE1 CKE0...
Page 513 Section 13 Serial Communication Interface Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from TDR to TSR. Bit 7 Description Transmit-data-empty interrupt request (TXI) is disabled* (Initial value)
Page 514 Section 13 Serial Communication Interface Bit 4—Receive Enable (RE): Enables or disables the start of SCI serial receiving operations. Bit 4 Description Receiving disabled * (Initial value) Receiving enabled * Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These flags retain their previous values.
Page 515 Section 13 Serial Communication Interface Bit 2—Transmit-End interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted. Bit 2 TEIE Description Transmit-end interrupt requests (TEI) are disabled* (Initial value) Transmit-end interrupt requests (TEI) are enabled* Note: * TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in SSR,...
Page 516 Section 13 Serial Communication Interface For smart card interface (SMIF bit in SCMR set to 1): These bits, together with the GM bit in SMR, determine whether the SCK pin is used for generic input/output or as the serial clock output pin.
Page 517: Serial Status Register (Ssr)
Section 13 Serial Communication Interface 13.2.7 Serial Status Register (SSR) SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate the operating status of the SCI. TDRE RDRF ORER FER/ERS TEND MPBT Initial value R/(W)* R/(W)* R/(W)* Read/Write R/(W)*...
Page 518 Section 13 Serial Communication Interface The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER, and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The TEND and MPB flags are read-only bits that cannot be written.
Page 519 Section 13 Serial Communication Interface Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error. Bit 5 ORER Description Receiving is in progress or has ended normally * (Initial value) Clearing conditions The chip is reset or enters standby mode Read ORER when ORER = 1, then write 0 in ORER A receive overrun error occurred * Setting condition...
Page 520 Section 13 Serial Communication Interface For smart card interface (SMIF bit in SCMR set to 1): Indicates the status of the error signal sent back from the receiving side during transmission. Framing errors are not detected in smart card interface mode. Bit 4 Description Normal reception, no error signal*...
Page 521 Section 13 Serial Communication Interface Bit 2—Transmit End (TEND): The function of this bit differs for the normal serial communication interface and for the smart card interface. Its function is switched with the SMIF bit in SCMR. For serial communication interface (SMIF bit in SCMR cleared to 0): Indicates that when the last bit of a serial character was transmitted TDR did not contain valid transmit data, so transmission has ended.
Page 522 Section 13 Serial Communication Interface Bit 1—Multiprocessor bit (MPB): Stores the value of the multiprocessor bit in the receive data when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit, and cannot be written. Bit 1 Description Multiprocessor bit value in receive data is 0* (Initial value)
Page 523: Bit Rate Register (Brr)
Section 13 Serial Communication Interface 13.2.8 Bit Rate Register (BRR) BRR is an 8-bit register that., together with the CKS1 and CKS0 bits in SMR that select the baud rate generator clock source, determines the serial communication bit rate. Initial value Read/Write The CPU can always read and write BRR.
Page 524 Section 13 Serial Communication Interface φ φ φ φ (MHz) 3.6864 4.9152 Bit Rate Error (%) n Error (%) n Error (%) n Error (%) (bit/s) 0.07 0.03 0.31 –0.25 191 0.00 207 0.16 255 0.00 0.16 0.00 103 0.16 127 0.00 129 0.16 191 0.00...
Page 525 Section 13 Serial Communication Interface φ φ φ φ (MHz) 9.8304 12.288 Bit Rate Error (%) n Error (%) n Error (%) n Error (%) (bit/s) 174 –0.26 177 –0.25 212 0.03 217 0.08 127 0.00 129 0.16 155 0.16 159 0.00 255 0.00 0.16...
Page 526 Section 13 Serial Communication Interface Table 13.4 Examples of Bit Rates and BRR Settings in Synchronous Mode φ φ φ φ (MHz) Rate (bit/s) n — — — — — — — — — — — — — — — —...
Page 527 Section 13 Serial Communication Interface The BRR setting is calculated as follows: Asynchronous mode: φ × 10 − 1 64 × 2 × B 2n−1 Synchronous mode: φ × 10 − 1 8 × 2 × B 2n−1 B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 ≤...
Page 528 Section 13 Serial Communication Interface Table 13.5 shows the maximum bit rates in asynchronous mode for various system clock frequencies. Table 13.6 and 13.7 shows the maximum bit rates with external clock input. Table 13.5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode) Settings φ...
Page 529 Section 13 Serial Communication Interface Table 13.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) φ φ φ φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000...
Page 530 Section 13 Serial Communication Interface Table 13.7 Maximum Bit Rates with External Clock Input (Synchronous Mode) φ φ φ φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 0.3333 333333.3 0.6667 666666.7 1.0000 1000000.0 1.3333 1333333.3 1.6667 1666666.7 2.0000 2000000.0 2.3333 2333333.3...
Page 531: Operation
Section 13 Serial Communication Interface 13.3 Operation 13.3.1 Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. A smart card interface is also supported as a serial communication function for an IC card interface.
Page 532 Section 13 Serial Communication Interface Smart Card Interface • One frame consists of 8-bit data and a parity bit. • In transmitting, a guard time of at least two elementary time units (2 etu) is provided between the end of the parity bit and the start of he next frame. (An elementary time unit is the time required to transmit one bit.) •...
Page 533: Operation In Asynchronous Mode
Section 13 Serial Communication Interface Table 13.9 SMR and SCR Settings and SCI Clock Source Selection SCR Setting SCI Transmit/Receive clock Bit 7 Bit 1 Bit 0 C/A A A A CKE1 CKE0 Mode Clock Source SCK Pin Function Asynchronous Internal SCI does not use the SCK pin mode...
Page 534 Section 13 Serial Communication Interface Idle (mark) state (LSB) (MSB) Serial data Start Parity Stop bit(s) Transmit or receive data 1 bit 7 or 8 bits 1 bit, 1 or 2 bits One unit of data (character or frame) none Figure 13.2 Data Format in Asynchronous Communication (Example: 8-Bit Data with Parity and 2 Stop Bits) Communication Formats: Table 13.10 shows the 12 communication formats that can be selected...
Page 535 Section 13 Serial Communication Interface Table 13.10 Serial Communication Formats (Asynchronous Mode) SMR Settings Serial Communication Format and Frame Length STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data STOP 8-bit data STOP STOP 7-bit data STOP 7-bit data STOP STOP 7-bit data STOP...
Page 536 Section 13 Serial Communication Interface Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in SMR and bits CKE1 and CKE0 in SCR. For details of SCI clock source selection, see table 13.9.
Page 537 Section 13 Serial Communication Interface Figure 13.4 shows a sample flowchart for initializing the SCI. Start of initialization Clear TE and RE bits to 0 in SCR Set CKE1 and CKE0 bits in SCR Set the clock source in SCR. Clear the (leaving TE and RE bits RIE, TIE, TEIE, MPIE, TE, and RE bits to cleared to 0)
Page 538 Section 13 Serial Communication Interface • Transmitting Serial Data (Asynchronous Mode): Figure 13.5 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. SCI initialization: Initialize the transmit data output function of the TxD pin is selected automatically.
Page 539 Section 13 Serial Communication Interface In transmitting serial data, the SCI operates as follows: • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 540 Section 13 Serial Communication Interface • Receiving Serial Data (Asynchronous Mode): Figure 13.7 shows a sample flowchart for receiving serial data and indicates the procedure to follow. Initialize SCI initialization: the receive data input function of the RxD pin is selected automatically. Start receiving (2)(3) Receive error handling and break detection:...
Page 541 Section 13 Serial Communication Interface Error handling ORER = 1 Overrun error handling FER = 1 Break? Framing error handling Clear RE bit to 0 in SCR PER = 1 Parity error handling Clear ORER, PER, and FER flags to 0 in SSR <End>...
Page 542 Section 13 Serial Communication Interface In receiving, the SCI operates as follows: • The SCI monitors the communication line. When it detects a start bit (0 bit), the SCI synchronizes internally and starts receiving. • Receive data is stored in RSR in order from LSB to MSB. •...
Page 543: Multiprocessor Communication
Section 13 Serial Communication Interface Figure 13.8 shows an example of SCI receive operation in asynchronous mode. Start Parity Stop Start Stop Parity Stop Data Data Idle (mark) state RDRF RXI request RXI interrupt handler Framing error, reads data in RDR and clears RDRF flag to 0 ERI request 1 frame...
Page 544 Section 13 Serial Communication Interface Communication Formats: Four formats are available. Parity bit settings are ignored when a multiprocessor format is selected. For details see table 13.10. Clock: See the description of asynchronous mode. Transmitting processor Serial communication line Receiving Receiving Receiving Receiving...
Page 545 Section 13 Serial Communication Interface SCI initialization: Initialize the transmit data output function of the TxD pin is selected automatically. Start transmitting SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit data in TDR. Also set the MPBT Read TDRE flag in SSR flag to 0 or 1 in SSR.
Page 546 Section 13 Serial Communication Interface In transmitting serial data, the SCI operates as follows: • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 547 Section 13 Serial Communication Interface SCI initialization: Initialize the receive data input function of the RxD pin is selected automatically. Start receiving ID receive cycle: set the MPIE bit to 1 in SCR. Set MPIE bit to 1 in SCR SCI status check and ID check: read SSR, check that the RDRF flag Read ORER and FER flags...
Page 548 Section 13 Serial Communication Interface Error handling ORER = 1 Overrun error handling FER = 1 Break? Clear RE bit to 0 in SCR Framing error handling Clear ORER, PER, and FER flags to 0 in SSR <End> Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (2) Rev.
Page 549 Section 13 Serial Communication Interface Figure 13.13 shows an example of SCI receive operation using a multiprocessor format. Start Stop Start Stop Data (ID1) Data (data1) Idle (mark) state MPIE RDRF RDR value MPB detection RXI interrupt RXI interrupt handler reads Not own ID, so MPIE No RXI interrupt MPIE = 0...
Page 550: Synchronous Operation
Section 13 Serial Communication Interface 13.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full- duplex communication is possible.
Page 551 Section 13 Serial Communication Interface Transmitting and Receiving Data: • SCI Initialization (Synchronous Mode): Before transmitting or receiving data, clear the TE and RE bits to 0 in SCR, then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below.
Page 552 Section 13 Serial Communication Interface • Transmitting Serial Data (Synchronous Mode): Figure 13.16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. SCI initialization: the transmit data output Initialize function selected automatically. Start transmitting SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then Read TDRE flag in SSR write transmit data in TDR and clear the...
Page 553 Section 13 Serial Communication Interface In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 554 Section 13 Serial Communication Interface • Receiving Serial Data (Synchronous Mode): Figure 13.18 shows a sample flowchart for receiving serial data and indicates the procedure to follow. When switching from asynchronous to synchronous mode. make sure that the ORER, PER, and FER flags are cleared to 0. If the FER or PER flag is set to 1 the RDRF flag will not be set and both transmitting and receiving will be disabled.
Page 555 Section 13 Serial Communication Interface Error handling Overrun error handling Clear ORER flag to 0 in SSR <End> Figure 13.18 Sample Flowchart for Serial Receiving (2) In receiving, the SCI operates as follows: • The SCI synchronizes with serial clock input or output and synchronizes internally. •...
Page 556 Section 13 Serial Communication Interface Figure 13.19 shows an example of SCI receive operation. Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt RXI interrupt handler RXI interrupt Overrun error, request reads data in RDR and...
Page 557 Section 13 Serial Communication Interface • Transmitting and Receiving Data Simultaneously (Synchronous Mode): Figure 13.20 shows a sample flowchart for transmitting and receiving serial data simultaneously and indicates the procedure to follow. Initialize SCI initialization: the transmit data output function of the TxD pin and the read data input function of the RxD pin are selected, enabling simultaneous transmitting and Start of transmitting and receiving...
Page 558: Sci Interrupts
Section 13 Serial Communication Interface 13.4 SCI Interrupts The SCI has four interrupt request sources: the transmit-end interrupt (TEI), receive-error interrupt (ERI), receive-data-full interrupt (RXI), and transmit-data-empty interrupt (TXI). Table 13.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled or disabled by the TIE, RIE, and TEIE bits in SCR.
Page 559: Usage Notes
Section 13 Serial Communication Interface 13.5 Usage Notes 13.5.1 Notes on Use of SCI Note the following points when using the SCI. TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of transmit data from TDR to TSR.
Page 560 Section 13 Serial Communication Interface Sending a Break Signal: The input/output condition and level of the TxD pin are determined by DR and DDR bits. This feature can be used to send a break signal. After the serial transmitter is initialized, the DR value substitutes for the mark state until the TE bit is set to 1 (the TxD pin function is not selected until the TE bit is set to 1).
Page 561 Section 13 Serial Communication Interface The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). D − 0.5 × 100% ) − (L − 0.5) F − (0.5 − (1 + F) ..(1) Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (L = 0 to 1.0)
Page 562 Section 13 Serial Communication Interface TDRE Note: In operation with an external clock source, be sure that t >4 states. Figure 13.22 Example of Synchronous Transmission Using DMAC Switching from SCK Pin Function to Port Pin Function: • Problem in Operation: When switching the SCK pin function to the output port function (high- level output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle.
Page 563 Section 13 Serial Communication Interface • Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown.
Page 564 Section 13 Serial Communication Interface Rev. 4.00 Jan 26, 2006 page 540 of 938 REJ09B0276-0400...
Page 565: Section 14 Smart Card Interface
Section 14 Smart Card Interface Section 14 Smart Card Interface 14.1 Overview An IC card (smart card) interface conforming to the ISO/IEC 7816-3 (Identification Card) standard is supported as an extension of the serial communication interface (SCI) functions. Switchover between the normal serial communication interface and the smart card interface is controlled by a register setting.
Page 566: Block Diagram
Section 14 Smart Card Interface 14.1.2 Block Diagram Figure 14.1 shows a block diagram of the smart card interface. Internal Module data bus data bus SCMR φ φ/4 Baud rate generator φ/16 Transmission/ φ/64 reception control Parity generation Clock Parity check External clock Legend SCMR: Smart card mode register...
Page 567: Pin Configuration
Section 14 Smart Card Interface 14.1.3 Pin Configuration Table 14.1 shows the smart card interface pins. Table 14.1 Smart Card Interface Pins Pin Name Abbreviation Function Serial clock pin Clock input/output Receive data pin Input Receive data input Transmit data pin Output Transmit data output Rev.
Page 568: Register Configuration
Section 14 Smart Card Interface 14.1.4 Register Configuration The smart card interface has the internal registers listed in table 14.2. The BRR, TDR, and RDR registers have their normal serial communication interface functions, as described in section 13, Serial Communication Interface. Table 14.2 Smart Card Interface Registers Address * Channel...
Page 569: Register Descriptions
Section 14 Smart Card Interface 14.2 Register Descriptions This section describes the new or modified registers and bit functions in the smart card interface. 14.2.1 Smart Card Mode Register (SCMR) SCMR is an 8-bit readable/writable register that selects smart card interface functions. ...
Page 570 Section 14 Smart Card Interface Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used in combination with the SDIR bit to communicate with inverse-convention cards. * The SINV bit does not affect the logic level of the parity bit. For parity settings, see section 14.3.4, Register Settings.
Page 571: Serial Status Register (Ssr)
Section 14 Smart Card Interface 14.2.2 Serial Status Register (SSR) The function of SSR bit 4 is modified in smart card interface mode. This change also causes a modification to the setting conditions for bit 2 (TEND). TDRE RDRF ORER TEND MPBT Initial value...
Page 572 Section 14 Smart Card Interface Bits 3 to 0: These bits operate as in normal serial communication. For details see section 13.2.7, Serial Status Register (SSR). The setting conditions for transmit end (TEND), however, are modified as follows. Bit 2 TEND Description Transmission is in progress...
Page 573: Serial Mode Register (Smr)
Section 14 Smart Card Interface 14.2.3 Serial Mode Register (SMR) The function of SMR bit 7 is modified in smart card interface mode. This change also causes a modification to the function of bits 1 and 0 in the serial control register (SCR). STOP CKS1 CKS0...
Page 574: Serial Control Register (Scr)
Section 14 Smart Card Interface 14.2.4 Serial Control Register (SCR) The function of SCR bits 1 and 0 is modified in smart card interface mode MPIE TEIE CKE1 CKE0 Initial value Read/Write Bits 7 to 2: These bits operate as in normal serial communication. For details see section 13.2.6, Serial Control Register (SCR).
Page 575: Operation
Section 14 Smart Card Interface 14.3 Operation 14.3.1 Overview The main features of the smart card interface are as follows. • One frame consists of 8-bit data plus a parity bit. • In transmission, a guard time of at least 2 etu (elementary time units: the time for transfer of one bit) is provided between the end of the parity bit and the start of the next frame.
Page 576 Section 14 Smart Card Interface Data line Clock line H8/3067 Group Px (port) chip Reset line Smart card Card-processing device Figure 14.2 Smart Card Interface Connection Diagram Note: A loop-back test can be performed by setting both RE and TE to 1 without connecting a smart card.
Page 577: Data Format
Section 14 Smart Card Interface 14.3.3 Data Format Figure 14.3 shows the smart card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting device to request retransmission of the data.
Page 578: Register Settings
Section 14 Smart Card Interface the receiving device places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. 5. If the transmitting device does not receive an error signal, it proceeds to transmit the next data frame.
Page 579 Section 14 Smart Card Interface output, set these bits to 01. Clock output is not performed when the GM bit is set to 1 in SMR. Clock output can also be fixed low or high. Smart Card Mode Register (SCMR) Settings: Clear both the SDIR bit and SINV bit cleared to 0 if the smart card is of the direct convention type, and set both to 1 if of the inverse convention type.
Page 580: Clock
Section 14 Smart Card Interface 14.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register (BRR) and the CKS1 and CKS0 bits in the serial mode register (SMR).
Page 581 Section 14 Smart Card Interface The following equation calculates the bit rate register (BRR) setting from the operating frequency and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error. φ × 10 −...
Page 582: Transmitting And Receiving Data
Section 14 Smart Card Interface 14.3.6 Transmitting and Receiving Data Initialization: Before transmitting or receiving data, the smart card interface must be initialized as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1.
Page 583 Section 14 Smart Card Interface If the TXI interrupt activates the DMAC, the number of bytes designated in the DMAC can be transmitted automatically, including automatic retransmission. For details, see Interrupt Operations and Data Transfer by DMAC in this section. Serial data Guard time (1) GM = 0...
Page 584 Section 14 Smart Card Interface Start Initialization Start transmitting FER/ERS = 0? Error handling TEND = 1? Write transmit data in TDR, and clear TDRE flag to 0 in SSR All data transmitted? FER/ERS = 0? Error handling TEND = 1? Clear TE bit to 0 Figure 14.5 Sample Transmission Processing Flowchart Rev.
Page 585 Section 14 Smart Card Interface (shift register) 1. Data write Data 1 2. Transfer from TDR to TSR Data 1 Data 1 Data remains in TDR Data 1 I/O signal 3. Serial data output Data 1 output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps 2 and 3 above are repeated until the...
Page 586 Section 14 Smart Card Interface 6. To end reception, clear the RE bit to 0. Start Initialization Start receiving ORER = 0 and PER = 0? Error handling RDRF = 1? Read RDR and clear RDRF flag to 0 in SSR All data received? Clear RE bit to 0 Figure 14.8 Sample Reception Processing Flowchart...
Page 587 Section 14 Smart Card Interface If a parity error occurs during reception and the PER flag is set to 1, the received data is transferred to RDR, so the erroneous data can be read. Switching Modes: When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE to 0 and setting TE to 1.
Page 588 Section 14 Smart Card Interface Table 14.8 Smart Card Interface Mode Operating States and Interrupt Sources Interrupt DMAC Operating State Flag Enable Bit Source Activation Transmit Mode Normal operation TEND Available Error Not available Receive Mode Normal operation RDRF Available Error PER, ORER RIE Not available...
Page 589 Section 14 Smart Card Interface 3. Write 0 in the CKE0 bit in SCR to stop the clock. 4. Wait for one serial clock cycle. During this period, the duty cycle is preserved and clock output is fixed at the specified level. 5.
Page 590: Usage Notes
Section 14 Smart Card Interface 14.4 Usage Notes The following points should be noted when using the SCI as a smart card interface. Receive Data Sampling Timing and Receive Margin in Smart Card Interface Mode: In smart card interface mode, the SCI operates on a base clock with a frequency of 372 times the transfer rate.
Page 591 Section 14 Smart Card Interface The receive margin can therefore be expressed as follows. Receive margin in smart card interface mode: D − 0.5 (1 + F) × 100% ) − (L − 0.5) F − M = (0.5 − M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 372) D: Clock duty cycle (L = 0 to 1.0)
Page 592 Section 14 Smart Card Interface Frame n+1 Frame n Retransmitted frame (DE) D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 RDRF Figure 14.12 Retransmission in SCI Receive Mode •...
Page 593: Section 15 A/D Converter
Section 15 A/D Converter Section 15 A/D Converter 15.1 Overview The H8/3067 Group includes a 10-bit successive-approximations A/D converter with a selection of up to eight analog input channels. When the A/D converter is not used, it can be halted independently to conserve power. For details see section 20.6, Module Standby Function.
Page 594: Block Diagram
Section 15 A/D Converter 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the A/D converter. On-chip Module data bus data bus 10-bit D/A – φ/4 Comparator Analog Control circuit multi- plexer Sample-and- φ/8 hold circuit ADTRG interrupt signal Compare match A0 ADTE 8-bit timer...
Page 595: Input Pins
Section 15 A/D Converter 15.1.3 Input Pins Table 15.1 summarizes the A/D converter’s input pins. The eight analog input pins are divided into two groups: group 0 (AN to AN ), and group 1 (AN to AN ). AV and AV are the power supply for the analog circuits in the A/D converter.
Page 596: Register Configuration
Section 15 A/D Converter 15.1.4 Register Configuration Table 15.2 summarizes the A/D converter’s registers. Table 15.2 A/D Converter Registers Address * Name Abbreviation Initial Value H'FFFE0 A/D data register A H ADDRAH H'00 H'FFFE1 A/D data register A L ADDRAL H'00 H'FFFE2 A/D data register B H...
Page 597: Register Descriptions
Section 15 A/D Converter 15.2 Register Descriptions 15.2.1 A/D Data Registers A to D (ADDRA to ADDRD)       ADDRn Initial value Read/Write (n = A to D) A/D conversion data Reserved bits 10-bit data giving an A/D conversion result The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion.
Page 598: A/D Control/Status Register (Adcsr)
Section 15 A/D Converter 15.2.2 A/D Control/Status Register (ADCSR) ADIE ADST SCAN Initial value Read/Write R/(W) Channel select 2 to 0 These bits select analog input channels Clock select Selects the A/D conversion time Scan mode Selects single mode or scan mode A/D start Starts or stops A/D conversion A/D interrupt enable...
Page 599 Section 15 A/D Converter Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7 Description [Clearing condition] (Initial value) Read ADF when ADF =1, then write 0 in ADF. DMAC activated by ADI interrupt. [Setting conditions] Single mode: A/D conversion ends Scan mode: A/D conversion ends in all selected channels Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the end of A/D conversion.
Page 600 Section 15 A/D Converter Bit 4—Scan Mode (SCAN): Selects single mode or scan mode. For further information on operation in these modes, see section 15.4, Operation. Clear the ADST bit to 0 before switching the conversion mode. Bit 4 SCAN Description Single mode (Initial value)
Page 601: A/D Control Register (Adcr)
Section 15 A/D Converter 15.2.3 A/D Control Register (ADCR)        TRGE Initial value       Read/Write Reserved bits Trigger enable Enables or disables starting of A/D conversion by an external trigger or 8-bit timer compare match ADCR is an 8-bit readable/writable register that enables or disables starting of A/D conversion by external trigger input or an 8-bit timer compare match signal.
Page 602: Cpu Interface
Section 15 A/D Converter 15.3 CPU Interface ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read through an 8-bit temporary register (TEMP).
Page 603 Section 15 A/D Converter Upper-byte read Module data bus Bus interface (H'AA) TEMP (H'40) ADDRnH ADDRnL (H'AA) (H'40) (n = A to D) Lower-byte read Module data bus Bus interface (H'40) TEMP (H'40) ADDRnH ADDRnL (H'AA) (H'40) (n = A to D) Figure 15.2 A/D Data Register Access Operation (Reading H'AA40) Rev.
Page 604: Operation
Section 15 A/D Converter 15.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 15.4.1 Single Mode (SCAN = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input.
Page 605 Section 15 A/D Converter Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) Rev. 4.00 Jan 26, 2006 page 581 of 938 REJ09B0276-0400...
Page 606: Scan Mode (Scan = 1)
Section 15 A/D Converter 15.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN when CH2 = 0, AN when CH2 = 1).
Page 607 Section 15 A/D Converter Figure 15.4 Example of A/D Converter Operation (Scan Mode, Channels AN to AN Selected) Rev. 4.00 Jan 26, 2006 page 583 of 938 REJ09B0276-0400...
Page 608: Input Sampling And A/D Conversion Time
Section 15 A/D Converter 15.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time t after the ADST bit is set to 1, then starts conversion. Figure 15.5 shows the A/D conversion timing.
Page 609 Section 15 A/D Converter φ Address bus Write signal Input sampling timing CONV Legend (1): ADCSR write cycle (2): ADCSR address Synchronization delay Input sampling time A/D conversion time CONV Figure 15.5 A/D Conversion Timing Table 15.4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Symbol...
Page 610: External Trigger Input Timing
Section 15 A/D Converter 15.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR and the 8-bit timer's ADTE bit is cleared to 0, external trigger input is enabled at the ADTRG pin. A high-to- low transition at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion.
Page 611: Interrupts
Section 15 A/D Converter 15.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. The ADI interrupt request can be designated as a DMAC activation source.
Page 612 Section 15 A/D Converter 100 Ω to AN 0.1 µF Notes: 1. 10 µF 0.01 µF 2. Rin: input impedance Figure 15.7 Example of Analog Input Protection Circuit Table 15.5 Analog Input Pin Ratings Item Unit Analog input capacitance — Allowable signal-source impedance —...
Page 613 Section 15 A/D Converter 6. A/D Conversion Accuracy Definitions: A/D conversion accuracy in the H8/3067 Group is defined as follows: • Resolution:....Digital output code length of A/D converter • Offset error: ....Deviation from ideal A/D conversion characteristic of analog input voltage required to raise digital output from minimum voltage value 0000000000 to 0000000001 (figure 15.10) •...
Page 614 Section 15 A/D Converter Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog input Offset error voltage Figure 15.10 A/D Converter Accuracy Definitions (2) 7. Allowable Signal-Source Impedance: The analog inputs of the H8/3067 Group are designed to assure accurate conversion of input signals with a signal-source impedance not exceeding 10 kΩ.
Page 615 Section 15 A/D Converter If a filter circuit is used, be careful of interference with digital signals on the same board, and make sure the circuit does not act as an antenna. H8/3067 Group Equivalent circuit of A/D converter Sensor output impedance 10 kΩ...
Page 616 Section 15 A/D Converter Rev. 4.00 Jan 26, 2006 page 592 of 938 REJ09B0276-0400...
Page 617: Section 16 D/A Converter
Section 16 D/A Converter Section 16 D/A Converter 16.1 Overview The H8/3067 Group includes a D/A converter with two channels. 16.1.1 Features D/A converter features are listed below. • Eight-bit resolution • Two output channels • Conversion time: maximum 10 µs (with 20-pF capacitive load) •...
Page 618: Block Diagram
Section 16 D/A Converter 16.1.2 Block Diagram Figure 16.1 shows a block diagram of the D/A converter. On-chip Module data bus data bus 8-bit D/A Control circuit Legend DACR: D/A control register DADR0: D/A data register 0 DADR1: D/A data register 1 DASTCR: D/A standby control register Figure 16.1 D/A Converter Block Diagram...
Page 619: Register Configuration
Section 16 D/A Converter 16.1.4 Register Configuration Table 16.2 summarizes the D/A converter's registers. Table 16.2 D/A Converter Registers Address* Name Abbreviation Initial Value H'FFF9C D/A data register 0 DADR0 H'00 H'FFF9D D/A data register 1 DADR1 H'00 H'FFF9E D/A control register DACR H'1F H'EE01A...
Page 620: Register Descriptions
Section 16 D/A Converter 16.2 Register Descriptions 16.2.1 D/A Data Registers 0 and 1 (DADR0/1) Initial value Read/Write The D/A data registers (DADR0 and DADR1) are 8-bit readable/writable registers that store the data to be converted. When analog output is enabled, the D/A data register values are constantly converted and output at the analog output pins.
Page 621 Section 16 D/A Converter Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output. Bit 7 DAOE1 Description analog output is disabled Channel-1 D/A conversion and DA analog output are enabled Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6 DAOE0 Description...
Page 622: D/A Standby Control Register (Dastcr)
Section 16 D/A Converter 16.2.3 D/A Standby Control Register (DASTCR) DASTCR is an 8-bit readable/writable register that enables or disables D/A output in software standby mode.        DASTE Initial value     ...
Page 623: Operation
Section 16 D/A Converter 16.3 Operation The D/A converter has two built-in D/A conversion circuits that can perform conversion independently. D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value is modified, conversion of the new data begins immediately. The conversion results are output when bits DAOE0 and DAOE1 are set to 1.
Page 624: D/A Output Control
Section 16 D/A Converter DADR0 DACR DADR0 DACR write cycle write cycle write cycle write cycle φ Address DADR0 Conversion data 1 Conversion data 2 DAOE0 Conversion result 2 Conversion High-impedance state result 1 DCONV DCONV Legend : D/A conversion time DCONV Figure 16.2 Example of D/A Converter Operation 16.4...
Page 625: Section 17 Ram
Section 17 RAM Section 17 RAM 17.1 Overview The H8/3067 and H8/3066 have 4 kbytes of high-speed static RAM on-chip. The H8/3065 has 2 kbytes. The RAM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states, making the RAM useful for rapid data transfer.
Page 626: Block Diagram
Section 17 RAM 17.1.1 Block Diagram Figure 17.1 shows a block diagram of the on-chip RAM. On-chip data bus (upper 8 bits) On-chip data bus (lower 8 bits) Bus interface SYSCR H'FEF20* H'FEF21* H'FEF22* H'FEF23* On-chip RAM H'FFF1E* H'FFF1F* Even addresses Odd addresses Legend SYSCR: System control register...
Page 627: Register Configuration
Section 17 RAM 17.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 17.1 gives the address and initial value of SYSCR. Table 17.1 System Control Register Address* Name Abbreviation Initial Value H'EE012 System control register SYSCR H'09 Note: * Lower 20 bits of the address in advanced mode. Rev.
Page 628: System Control Register (Syscr)
Section 17 RAM 17.2 System Control Register (SYSCR) SSBY STS2 STS1 STS0 NMIEG SSOE RAME Initial value Read/Write RAM enable bit Enables or disables on-chip RAM Software standby output port enable NMI edge select User bit enable Standby timer select 2 to 0 Software standby One function of SYSCR is to enable or disable access to the on-chip RAM.
Page 629: Operation
Section 17 RAM 17.3 Operation When the RAME bit is set to 1, the on-chip RAM is enabled. Accesses to addresses H'FEF20 to H'FFF1F in the H8/3067 and H8/3066 in modes 1, 2, and 7, and to addresses H'FFEF20 to H'FFFF1F in the H8/3067 and H8/3066 in modes 3, 4, and 5, and to addresses H'EF20 to H'FF1F in mode 6, are directed to the on-chip RAM.
Page 630 Section 17 RAM Rev. 4.00 Jan 26, 2006 page 606 of 938 REJ09B0276-0400...
Page 631: Section 18 Rom
Section 18 ROM Section 18 ROM 18.1 Overview The H8/3067 has 128 kbytes of on-chip ROM (flash memory or mask ROM), the H8/3066 has 96 kbytes, and H8/3065 has 64 kbytes. The ROM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte and word data in two states, enabling rapid data transfer.
Page 632: Overview Of Flash Memory
Section 18 ROM 18.2 Overview of Flash Memory 18.2.1 Features The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode  Erase-verify mode • Programming/erase methods The flash memory is programmed 32 bytes at a time.
Page 633: Block Diagram
Section 18 ROM 18.2.2 Block Diagram Figure 18.1 shows a block diagram of the flash memory. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) FLMCR Operating FWE pin* Bus interface/controller mode Mode pins RAMCR FLMSR H'00000 H'00001 H'00002 H'00003...
Page 634: Pin Configuration
Section 18 ROM 18.2.3 Pin Configuration The flash memory is controlled by means of the pins shown in table 18.2. Table 18.2 Flash Memory Pins Pin Name Abbreviation Function Reset Input Reset Flash write enable FWE* Input Flash program/erase protection by hardware Mode 2 Input Sets this LSI operating mode...
Page 635: Register Descriptions
Section 18 ROM 18.3 Register Descriptions 18.3.1 Flash Memory Control Register (FLMCR) FLMCR is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1. Program mode is entered by setting SWE to 1 when FWE = 1, then setting the PSU bit, and finally setting the P bit.
Page 636 Section 18 ROM Modes 1 Initial value to 4, and 6 Modes 5 Initial value and 7 Program mode Designates transition to or exit from program mode Erase mode Designates transition to or exit from erase mode Program-verify mode Designates transition to or exit from program-verify mode Erase-verify mode...
Page 637 Section 18 ROM Bit 6—Software Write Enable Bit (SWE) * : This bit enables/disables flash memory programming/erasing. This bit should be set before setting FLMCR bits 5 to 0, and EBR bits 7 to 0. Do not set the ESU, PSU, EV, PV, E, or P bits at the same time. Bit 6: Description Program/erase disabled...
Page 638 Section 18 ROM Bit 3—Erase-Verify (EV) * : Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3: Description Erase-verify mode cleared (Initial value) Transition to erase-verify mode [Setting condition] When FWE = 1, and SWE = 1 Bit 2—Program-Verify (PV) *...
Page 639: Erase Block Register (Ebr)
Section 18 ROM Bit 0—Program (P) * : Selects program mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or E bit at the same time. Bit 0: Description Program mode cleared (Initial value) Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 Notes: 1.
Page 640 Section 18 ROM Bits 7 to 0—Block 7 to 0 (EB7 to EB0): These bits select blocks (EB7 to EB0) to be erased. Bits 7 to 0: EB7 to EB0 Description Block EB7 to EB0 is not selected. (Initial value) Block EB7 to EB0 is selected.
Page 641: Ram Control Register (Ramcr)
Section 18 ROM 18.3.3 RAM Control Register (RAMCR) RAMCR selects the RAM area used when emulating real-time reprogramming of the flash memory.      RAMS RAM2 RAM1 Modes 1 Initial value      to 4 Modes 5 Initial value ...
Page 642 Section 18 ROM Bit 0—Reserved: This bit cannot be modified and is always read as 1. Note: * Flash memory emulation by RAM is not supported for Mode 6 (single chip normal mode), so programming is possible, but do not set 1. When performing flash memory emulation by RAM, the RAME bit in SYSCR must be set to 1.
Page 643: Flash Memory Status Register
Section 18 ROM 18.3.4 Flash Memory Status Register The flash memory status register (FLMSR) detects flash memory errors.        FLER Initial value        Reserved bits Flash memory error Status flag indicating that an error was detected during programming or erasing...
Page 644 Section 18 ROM Bit 7—Flash Memory Error (FLER): Indicates that an error occurred while flash memory was being programmed or erased. When bit 7 is set, flash memory is placed in an error-protect mode. Bit 7 FLER Description Flash memory program/erase protection (error protection * ) is disabled (Initial value) [Clearing conditions] WDT reset, reset by RES pin, or hardware standby mode...
Page 645: On-Board Programming Modes
Section 18 ROM 18.4 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 18.6.
Page 646 Section 18 ROM On-Board Programming Modes • Boot mode 1. Initial state 2. Programming control program transfer The flash memory is in the erased state when the When boot mode is entered, the boot program in device is shipped. The description here applies to the H8/3067 Group chip (originally incorporated the case where the old program version or data in the chip) is started, an SCI communication...
Page 647 Section 18 ROM • User program mode 1. Initial state 2. Programming/erase control program transfer (1) The program that will transfer the When the FWE pin is driven high, user software programming/ erase control program to on-chip confirms this fact, executes the transfer program RAM should be written into the flash memory by in the flash memory, and transfers the the user beforehand.
Page 648: Boot Mode
Section 18 ROM 18.4.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. In reset start, after setting this LSI pin to the boot mode, start the microcomputer boot program, measure the Low period of the data sent from the host, and select the bit rate register (BRR) value beforehand.
Page 649 Section 18 ROM Start Set pins to boot program mode Set the H8/3067 to the boot mode and reset starts the LSI. and execute reset-start Set the host to the prescribed bit rate (4800, 9600) Host transfers data (H'00) and consecutively send H'00 data in 8-bit data, continuously at prescribed bit rate 1 stop bit format.
Page 650 Section 18 ROM Automatic SCI Bit Rate Adjustment Start Stop Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 18.7 Measuring the low period of the communication data from the host When boot mode is initiated, this LSI measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host (figure 18.7).
Page 651 Section 18 ROM On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the user program is transferred via the SCI, as shown in figure 18.8.
Page 652 Section 18 ROM (5) This LSI terminates transmit and receive operations by the on-chip SCI(channel 1) (by clearing the RE and TE bits in serial control register (SCR)) before branching to the user program. However, the adjusted bit rate is held in the bit rate register (BRR). At this time, the TXD is in the high level output state (P9DDR P9 DDR=1, P9DR P9 DR=1).
Page 653: User Program Mode
Section 18 ROM flash memory and flash memory R versions of the H8/3037 requires a minimum of 20 system clocks. 18.4.2 User Program Mode When set to the user program mode, this LSI can erase and program its flash memory by executing a user program.
Page 654 Section 18 ROM <Procedure> The user writes a program that executes steps 3 to 8 in advance - MD =101, 111 as shown below. Sets the mode pin to an on-chip ROM enable mode (mode 5 or 7). Reset start Starts the CPU via reset.
Page 655: Programming/Erasing Flash Memory
Section 18 ROM 18.5 Programming/Erasing Flash Memory A software method, using the CPU, is employed to program and erase flash memory in the on- board programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU, P, E, PV, and EV bits in FLMCR.
Page 656: Program Mode
Section 18 ROM Erase setup state Erase mode Normal mode FWE=1 FWE=0 Erase-verify mode On-board SWE=1 Software programming mode reprogramming software reprogramming enable state disable state SWE=0 Program setup state Programming mode Program-verify mode Notes: : Normal mode : On-board programming mode 1.
Page 657: Program-Verify Mode
Section 18 ROM (The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0.) 32 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 32-byte data transfer must be performed even if writing fewer than 32 bytes;...
Page 658 Section 18 ROM Start Set SWE bit in FLMCR Wait (x) µs Store 32-byte write data in write data area and reprogram data area Programming operation counter n ← 1 Notes: 1. Programming should be performed in the erased state. Consecutively write 32-byte data in (Perform 32-byte programming on memory after all 32 bytes reprogram data area in RAM to flash memory...
Page 659: Erase Mode
Section 18 ROM 18.5.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 18.12. For the wait time (x, y, z, α, β, γ, ε, η) after setting or clearing of each bit in the flash memory control register (FLMCR and the maximum erase count (N)), see table 21.19 of section 21.2.6, Flash Memory Characteristics.
Page 660 Section 18 ROM Start Set SWE bit in FLMCR Wait (x) µs Erase counter n ← 1 Set EBR Enable WDT Set ESU bit in FLMCR Wait (y) µs Set E bit in FLMCR Start of erase Wait (z) ms Clear E bit in FLMCR End of erase Wait (α) µs...
Page 661: Flash Memory Protection
Section 18 ROM 18.6 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 18.6.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted.
Page 662 Section 18 ROM Table 18.8 Hardware Protection Function Verify * Item Description Program Erase FWE pin protection • No * No * When a low level is input to the FWE pin, FLMCR and EBR are initialized, and the program/erase-protected state is entered.
Page 663: Software Protection
Section 18 ROM 18.6.2 Software Protection Software protection can be implemented by setting the RAMS bit in RAM control register (RAMCR) and erase block register (EBR). When software protection is in effect, setting the P or E bit in flash memory control register (FLMCR) does not cause a transition to program mode or erase mode.
Page 664 Section 18 ROM Error protection is released only by a reset via the RES pin or a WDT reset, or in the hardware standby mode. Figure 18.13 shows the flash memory state transition diagram. Notes: 1. This is the state in which the P or E bit in FLMCR is set to 1. In this state, NMI input is disabled.
Page 665 Section 18 ROM Memory read verify mode RD VF PR ER FLER=0 P=1 or E=1 P=0 and E=0 Reset or standby mode Program mode (hardware protection) Erase mode Reset or hardware standby mode RD VF PR ER FLER=0 RD VF PR ER INIT FLER=0 Error occurrence Reset or hardware standby mode...
Page 666: Nmi Input Disable Conditions
Section 18 ROM programming and erasing. In such cases, always forcibly return (reprogram) by boot mode. However, overprogramming and overerasing may prevent the boot mode from starting normally. 18.6.4 NMI Input Disable Conditions While flash memory is being programed/erased and the boot program is executing in the boot mode (however, period up to branching to on-chip RAM area) * , NMI input is disabled because the programming/erasing operations have priority.
Page 667: Flash Memory Emulation By Ram
Section 18 ROM 18.7 Flash Memory Emulation by RAM Erasing and programming the flash memory takes time, which can make it difficult to tune parameters and other data in real time. In this case, overlapping part (H'FFF000 to H'FFF3FF) of RAM onto a small block area of flash memory can be performed to emulate real-time reprogramming of flash memory.
Page 668 Section 18 ROM Notes on use of the RAM emulation function (1) Notes on flash write enable (FWE) high/low Care is necessary to prevent erroneous programming/erasing at FWE=high/low, the same as in the on-board programming mode. To prevent erroneous programming and erasing due to program runaway, etc., during FWE application, in particular, the watchdog timer should be set when the PSU, P, ESU, or E bit is set to 1 in FLMCR, even while the emulation function is being used.
Page 669: Flash Memory Prom Mode
This LSI has a PROM mode, besides an on-board programming mode, as a flash memory program/erase mode. In the PROM mode, a program can be freely written to the on-chip ROM using a PROM writer that supports the Renesas 128kbytes flash memory on-chip microcomputer device type.
Page 670 Section 18 ROM • Status Read Mode Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the I/O 6 signal. In status read mode, error information is output if an error occurs. Table 18.10 Settings for Each Operating Mode in PROM Mode Pin Names * Mode to D...
Page 671 Section 18 ROM Table 18.12 DC Characteristics in Memory Read Mode (Conditions: V = 5.0 V ± 10%, V = 0 V, T = 25°C ± 5°C) Item Symbol Unit Test Conditions Input high –0 –A — Vcc + 0.3 voltage Input low –0...
Page 672: Memory Read Mode
Section 18 ROM 18.8.4 Memory Read Mode AC Characteristics Table 18.13 AC Characteristics in Memory Read Mode Transition (Conditions: V = 5.0 V ±10%, V = 0 V, T = 25°C ±5°C) Item Symbol Unit Notes Command write cycle — µs nxtc CE hold time...
Page 673 Section 18 ROM Table 18.14 AC Characteristics in Memory Contents Read (Conditions: V = 5.0 V ±10%, V = 0 V, T = 25°C ±5°C) Item Symbol Unit Notes Access time — µs CE output delay time — OE output delay time —...
Page 674 Section 18 ROM Table 18.15 AC Characteristics in Transition from Memory Read Mode to Another Mode (Conditions: V = 5.0 V ±10%, V = 0 V, T = 25°C ±5°C) Item Symbol Unit Notes Command write cycle — µs nxtc CE hold time —...
Page 675: Auto-Program Mode
Section 18 ROM 18.8.5 Auto-Program Mode AC Characteristics Table 18.16 AC Characteristics in Auto-Program Mode (Conditions: V = 5.0 V ±10%, V = 0 V, T = 25°C ±5°C) Item Symbol Unit Notes Command write cycle — µs nxtc CE hold time —...
Page 676 Section 18 ROM ADDRESS STABLE A16-0 nxtc nxtc wsts Data transfer 1byte to 128bytes write I/O7 Programming operation end identification signal I/O6 Programming normal end identification signal H'00 H'40 I/O5-0 Figure 18.20 Auto-Program Mode Timing Waveforms Cautions on Use of Auto-Program Mode •...
Page 677: Auto-Erase Mode
Section 18 ROM 18.8.6 Auto-Erase Mode AC Characteristics Table 18.17 AC Characteristics in Auto-Erase Mode (Conditions: V = 5.0 V ±10%, V = 0 V, T = 25°C ±5°C) Item Symbol Unit Notes Command write cycle — µs nxtc CE hold time —...
Page 678 Section 18 ROM A16-0 nxtc nxtc ests erase I/O7 Erase end identification signal I/O6 Erase normal and confirmation signal H'00 H'20 H'20 I/O5-0 Figure 18.21 Auto-Erase Mode Timing Waveforms Caution on Use of Erase-Program Mode • Auto-erase mode supports only entire memory erasing. •...
Page 679: Status Read Mode
Section 18 ROM 18.8.7 Status Read Mode Table 18.18 AC Characteristics in Status Read Mode (Conditions: V = 5.0 V ±10%, V = 0 V, T = 25°C ±5°C) Item Symbol Unit Notes Command write cycle — µs nxtc CE hold time —...
Page 680: Prom Mode Transition Time
Section 18 ROM Table 18.19 Status Read Mode Return Commands Pin Name I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Attribute Normal Command Program- Erase — — Program- Effective error ming error error ming or address identifica- erase error tion count exceeded Initial...
Page 681: Notes On Memory Programming
Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas. For other chips for which the erasure history is unknown, it is recommended that auto- erasing be executed to check and supplement the initialization (erase) level.
Page 682: Notes On Flash Memory Programming/Erasing
(1) Program/erase with the specified voltage and timing. Applied voltages in excess of the rating can permanently damage the device. Use a PROM writer that supports the Renesas 128kbytes flash memory on-board microcomputer device type. Do not set the PROM writer at the HN28F101. If the PROM writer is set to the HN28F101 by mistake, a high level can be input to the FWE pin and the LSI can be destroyed.
Page 683 Section 18 ROM • In the boot mode, perform FWE pin High/Low switching during reset. In transition to the boot mode, input FWE=High level and set MD to MD while the RES input is low. At this time, the FWE and MD to MD inputs must satisfy the mode programming setup time (t...
Page 684 Section 18 ROM (7) Do not use an interrupt during flash memory programming or erasing. Since programming/erase operations (including emulation by RAM) have priority when a high level is input to the FWE pin, disable all interrupt requests, including NMI. (8) Do not perform additional programming.
Page 685 Section 18 ROM Programming and erase possible Wait time: x φ min 0µs OSC1 to MD clear SWE bit Flash memory access disabled period (x: Wait time after SWE setting)* Flash memory reprogrammable period (Flash memory program execution and data read, other than verify, are disabled.) Always fix the level by pulling down or pulling up the mode pins (MD to MD Notes:...
Page 686 Section 18 ROM Programming Programming Programming and Wait Programming and Wait erase erase Wait time: x erase possible Wait time: x possible time: x erase possible time: x possible φ OSC1 min 0µs to MD RESW SWE set SWE clear SWE bit User Boot mode...
Page 687: Mask Rom Overview
Section 18 ROM 18.10 Mask ROM Overview 18.10.1 Block Diagram Figure 18.28 shows a block diagram of the ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000001 H'000002 H'000003 On-chip ROM H'01FFFE H'01FFFF Even addresses Odd addresses Figure 18.28 ROM Block Diagram (H8/3067) Rev.
Page 688: Notes On Ordering Mask Rom Version Chip
Section 18 ROM 18.11 Notes on Ordering Mask ROM Version Chip When ordering the H8/3067 Group chips with a mask ROM, note the following. • When ordering through an EPROM, use a 128-kbyte one. • Fill all the unused addresses with H'FF as shown in figure18.27 to make the ROM data size 128 kbytes for all H8/3067 Group chips, which incorporate different sizes of ROM.
Page 689: Section 19 Clock Pulse Generator
Section 19 Clock Pulse Generator Section 19 Clock Pulse Generator 19.1 Overview The H8/3067 Group has a built-in clock pulse generator (CPG) that generates the system clock (φ) and other internal clock signals (φ/2 to φ/4096). After duty adjustment, a frequency divider divides the clock frequency to generate the system clock (φ).
Page 690: Block Diagram
Section 19 Clock Pulse Generator 19.1.1 Block Diagram Figure 19.1 shows a block diagram of the clock pulse generator. XTAL φ Duty Frequency Oscillator adjustment Prescalers divider circuit EXTAL Division control register Data bus φ pin φ/2 to φ/4096 Figure 19.1 Block Diagram of Clock Pulse Generator Rev.
Page 691: Oscillator Circuit
Section 19 Clock Pulse Generator 19.2 Oscillator Circuit Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock signal. 19.2.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as in the example in figure 19.2. The damping resistance Rd should be selected according to table 19.1.
Page 692 Section 19 Clock Pulse Generator XTAL EXTAL AT-cut parallel-resonance type Figure 19.3 Crystal Resonator Equivalent Circuit Table 19.2 Crystal Resonator Parameters Frequency (MHz) Rs max (Ω) Co (pF) 7 pF max Use a crystal resonator with a frequency equal to the system clock frequency (φ). Notes on Board Design: When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from...
Page 693: External Clock Input
Section 19 Clock Pulse Generator 19.2.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 19.5. If the XTAL pin is left open, the stray capacitance should not exceed 10 pF. If the stray capacitance at the XTAL pin exceeds 10 pF in configuration a, use configuration b instead and hold the clock high in standby mode.
Page 694 Section 19 Clock Pulse Generator External Clock: The external clock frequency should be equal to the system clock frequency when not divided by the on-chip frequency divider. Table 19.3 shows the clock timing, figure 19.6 shows the external clock input timing, and figure 19.7 shows the external clock output settling delay timing.
Page 695 Section 19 Clock Pulse Generator × 0.7 EXTAL × 0.5 0.3 V Figure 19.6 External Clock Input Timing 2.7 V STBY EXTAL φ (internal or external) DEXT Figure 19.7 External Clock Output Settling Delay Timing Rev. 4.00 Jan 26, 2006 page 671 of 938 REJ09B0276-0400...
Page 696: Duty Adjustment Circuit
Section 19 Clock Pulse Generator 19.3 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate φ. 19.4 Prescalers The prescalers divide the system clock (φ) to generate internal clocks (φ/2 to φ/4096). 19.5 Frequency Divider The frequency divider divides the duty-adjusted clock signal to generate the system clock (φ).
Page 697: Division Control Register (Divcr)
Section 19 Clock Pulse Generator 19.5.2 Division Control Register (DIVCR) DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency divider.       DIV1 DIV0 Initial value      ...
Page 698 Section 19 Clock Pulse Generator Rev. 4.00 Jan 26, 2006 page 674 of 938 REJ09B0276-0400...
Page 699: Section 20 Power-Down State
Section 20 Power-Down State Section 20 Power-Down State 20.1 Overview The H8/3067 Group has a power-down state that greatly reduces power consumption by halting the CPU, and a module standby function that reduces power consumption by selectively halting on-chip modules. The power-down state includes the following three modes: •...
Page 700 Section 20 Power-Down State Table 20.1 Power-Down State and Module Standby Function Rev. 4.00 Jan 26, 2006 page 676 of 938 REJ09B0276-0400...
Page 701: Register Configuration
Section 20 Power-Down State 20.2 Register Configuration The H8/3067 Group has a system control register (SYSCR) that controls the power-down state, and module standby control registers H (MSTCRH) and L (MSTCRL) that control the module standby function. Table 20.2 summarizes these registers. Table 20.2 Control Register Address* Name...
Page 702 Section 20 Power-Down State Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal operation. To clear this bit, write 0. Bit 7 SSBY Description...
Page 703: Module Standby Control Register H (Mstcrh)
Section 20 Power-Down State 20.2.2 Module Standby Control Register H (MSTCRH) MSTCRH is an 8-bit readable/writable register that controls output of the system clock (φ). It also controls the module standby function, which places individual on-chip supporting modules in the standby state.
Page 704: Module Standby Control Register L (Mstcrl)
Section 20 Power-Down State Bit 1—Module Standby H1 (MSTPH1): Selects whether to place the SCI1 in standby. Bit 1 MSTPH1 Description SCI1 operates normally (Initial value) SCI1 is in standby state Bit 0—Module Standby H0 (MSTPH0): Selects whether to place the SCI0 in standby. Bit 0 MSTPH0 Description...
Page 705 Section 20 Power-Down State Bit 7—Module Standby L7 (MSTPL7): Selects whether to place the DMAC in standby. Bit 7 MSTPL7 Description DMAC operates normally (Initial value) DMAC is in standby state Bit 6—Reserved: This bit can be written and read. Bit 5—Module Standby L5 (MSTPL5): Selects whether to place the DRAM interface in standby.
Page 706 Section 20 Power-Down State Bit 2—Module Standby L2 (MSTPL2): Selects whether to place 8-bit timer channels 2 and 3 in standby. Bit 2 MSTPL2 Description 8-bit timer channels 2 and 3 operate normally (Initial value) 8-bit timer channels 2 and 3 are in standby state Bit 1—Reserved: This bit can be written and read.
Page 707: Sleep Mode
Section 20 Power-Down State 20.3 Sleep Mode 20.3.1 Transition to Sleep Mode When the SSBY bit is cleared to 0 in SYSCR, execution of the SLEEP instruction causes a transition from the program execution state to sleep mode. Immediately after executing the SLEEP instruction the CPU halts, but the contents of its internal registers are retained.
Page 708: Software Standby Mode
Section 20 Power-Down State 20.4 Software Standby Mode 20.4.1 Transition to Software Standby Mode To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in SYSCR. In software standby mode, current dissipation is reduced to an extremely low level because the CPU, clock, and on-chip supporting modules all halt.
Page 709: Selection Of Waiting Time For Exit From Software Standby Mode
Section 20 Power-Down State 20.4.3 Selection of Waiting Time for Exit from Software Standby Mode Bits STS2 to STS0 in SYSCR and bits DIV1 and DIV0 in DIVCR should be set as follows. Crystal Resonator: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time (for the clock to stabilize) is at least 7 ms.
Page 710 Section 20 Power-Down State Table 20.3 Clock Frequency and Waiting Time for Clock to Settle DIV1 DIV0 STS2 STS1 STS0 Waiting Time 20 MHz 18 MHz 16 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz 1 MHz Unit 8192 states 0.46...
Page 711: Sample Application Of Software Standby Mode
Section 20 Power-Down State 20.4.4 Sample Application of Software Standby Mode Figure 20.1 shows an example in which software standby mode is entered at the fall of NMI and exited at the rise of NMI. With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an NMI interrupt occurs.
Page 712: Cautions On Clearing The Software Standby Mode Of F-Ztat Version
Section 20 Power-Down State 20.4.6 Cautions on Clearing the Software Standby Mode of F-ZTAT Version (1) Operation phenomena When using operating mode 5, 6, or 7* (on-chip flash memory enabled), the first read of on- chip flash memory after exiting software standby mode may not be carried out correctly. Software standby mode is exited by means of an external interrupt (via the NMI, IRQ , IRQ or IRQ...
Page 713: Hardware Standby Mode
Section 20 Power-Down State 20.5 Hardware Standby Mode 20.5.1 Transition to Hardware Standby Mode Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin goes low. Hardware standby mode reduces power consumption drastically by halting all functions of the CPU, DMAC, DRAM interface, and on-chip supporting modules.
Page 714: Timing For Hardware Standby Mode
Section 20 Power-Down State 20.5.3 Timing for Hardware Standby Mode Figure 20.2 shows the timing relationships for hardware standby mode. To enter hardware standby mode, first drive RES low, then drive STBY low. To exit hardware standby mode, first drive STBY high, wait for the clock to settle, then bring RES from low to high.
Page 715: Module Standby Function
Section 20 Power-Down State 20.6 Module Standby Function 20.6.1 Module Standby Timing The module standby function can halt several of the on-chip supporting modules (SCI2, SCI1, SCI0, the DMAC, 16-bit timer, 8-bit timer, DRAM interface, and A/D converter) independently in the power-down state.
Page 716 Section 20 Power-Down State Register Resetting: When an on-chip supporting module is halted by the module standby function, all its registers are initialized. To restart the module, after its MSTCR bit is cleared to 0, its registers must be set up again. It is not possible to write to the registers while the MSTCR bit is set to 1.
Page 717: System Clock Output Disabling Function
Section 20 Power-Down State 20.7 System Clock Output Disabling Function Output of the system clock (φ) can be controlled by the PSTOP bit in MSTCRH. When the PSTOP bit is set to 1, output of the system clock halts and the φ pin is placed in the high- impedance state.
Page 718 Section 20 Power-Down State Rev. 4.00 Jan 26, 2006 page 694 of 938 REJ09B0276-0400...
Page 719: Section 21 Electrical Characteristics
Section 21 Electrical Characteristics Section 21 Electrical Characteristics 21.1 Electrical Characteristics of Mask ROM Version 21.1.1 Absolute Maximum Ratings Table 21.1 lists the absolute maximum ratings. Table 21.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +7.0 Input voltage (except for port 7) –0.3 to V +0.3...
Page 720: Dc Characteristics
Section 21 Electrical Characteristics 21.1.2 DC Characteristics Table 21.2 lists the DC characteristics. Table 21.3 lists the permissible output currents. Table 21.2 DC Characteristics (1) Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = 4.5 V to AV = 0 V * = AV = –20°C to +75°C (regular specifications),...
Page 721 Section 21 Electrical Characteristics Item Symbol Unit Test Conditions Three-state Ports 1 to 6 — — µA = 0.5 V to leakage Ports 8 to B – 0.5 V current RESO — — 10.0 µA = 0 V Input pull-up Ports 2, 4, –I —...
Page 722 Section 21 Electrical Characteristics max. (under normal operations) = 1.0 (mA) + 0.90 (mA/(MHz × V)) × V × f 3. I = 1.0 (mA) + 0.65 (mA/(MHz × V)) × V × f max. (when using the sleeve) max. (when the sleeve + module are standing by) = 1.0 (mA) + 0.45 (mA/(MHz ×...
Page 723 Section 21 Electrical Characteristics Table 21.2 DC Characteristics (2) Conditions: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 V to AV = 0 V * = AV = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol...
Page 724 Section 21 Electrical Characteristics Item Symbol Unit Test Conditions Three-state Ports 1 to 6 — — µA = 0.5 V to leakage Ports 8 to B – 0.5 V current RESO — — 10.0 µA = 0 V Input pull-up Ports 2, 4, –I —...
Page 725 Section 21 Electrical Characteristics max. (under normal operations) = 1.0 (mA) + 0.90 (mA/(MHz × V)) × V × f 3. I = 1.0 (mA) + 0.65 (mA/(MHz × V)) × V × f max. (when using the sleeve) max. (when the sleeve + module are standing by) = 1.0 (mA) + 0.45 (mA/(MHz ×...
Page 726 Section 21 Electrical Characteristics Table 21.2 DC Characteristics (3) Conditions: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, V = 3.0 V to AV = 0 V * = AV = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol...
Page 727 Section 21 Electrical Characteristics Item Symbol Unit Test Conditions Three-state Ports 1 to 6 — — µA = 0.5 V to leakage Ports 8 to B – 0.5 V current RESO — — 10.0 µA = 0 V Input pull-up Ports 2, 4, –I —...
Page 728 Section 21 Electrical Characteristics max. (under normal operations) = 1.0 (mA) + 0.90 (mA/(MHz × V)) × V × f 3. I = 1.0 (mA) + 0.65 (mA/(MHz × V)) × V × f max. (when using the sleeve) max. (when the sleeve + module are standing by) = 1.0 (mA) + 0.45 (mA/(MHz ×...
Page 729 Section 21 Electrical Characteristics H8/3067 Group 600 Ω Ports 1, 2, 5 Figure 21.2 Sample LED Circuit Rev. 4.00 Jan 26, 2006 page 705 of 938 REJ09B0276-0400...
Page 730: Ac Characteristics
Section 21 Electrical Characteristics 21.1.3 AC Characteristics Clock timing parameters are listed in table 21.4, control signal timing parameters in table 21.5, and bus timing parameters in table 21.6. Timing parameters of the on-chip supporting modules are listed in table 21.7. Table 21.4 Clock Timing Condition: = –20°C to +75°C (regular specifications), T...
Page 731 Section 21 Electrical Characteristics Table 21.5 Control Signal Timing Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 to AV = AV = 0 V Condition B: V...
Page 732 Section 21 Electrical Characteristics Table 21.6 Bus Timing Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 to AV = AV = 0 V Condition B: V...
Page 733 Section 21 Electrical Characteristics Condition Test Item Symbol Min Unit Conditions Write data hold 0.5 t — 0.5 t — 0.5 t — Figure 21.11, time – 30 – 25 – 15 figure 21.12, figure 21.14, Read data access — 2.0 t —...
Page 734 Section 21 Electrical Characteristics Condition Test Item Symbol Min Unit Conditions CAS delay time 1 — — — Figure 21.17 CASD1 CAS delay time 2 — — — CASD2 figure 21.19 WE delay time — — — CAS pulse width 1 t 1.5 t —...
Page 735 Section 21 Electrical Characteristics Table 21.7 Timing of On-Chip Supporting Modules Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 to AV = AV = 0 V...
Page 736 Section 21 Electrical Characteristics Condition Test Item Symbol Min Unit Conditions Input Asyn- — — — Figure 21.23 Scyc clock chronous cycle Syn- — — — chronous Input clock rise — — — SCKr time Input clock fall — — —...
Page 737 Section 21 Electrical Characteristics C = 90 pF: ports 4, 6, 8, A to A to D H8/3067 Group C = 30 pF: ports 9, A, B, RESO output pin Ω R = 2.4 k Ω R = 12 k Input/output timing measurement levels •...
Page 738: A/D Conversion Characteristics
Section 21 Electrical Characteristics 21.1.4 A/D Conversion Characteristics Table 21.8 lists the A/D conversion characteristics. Table 21.8 A/D Conversion Characteristics Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 to AV = AV...
Page 739 Section 21 Electrical Characteristics Condition Item Min Typ Max Min Typ Max Min Typ Max Unit Conver- Resolution bits sion time: Conversion time (single — — — — — — 70 states mode) Analog input capacitance — — — — —...
Page 740: D/A Conversion Characteristics
Section 21 Electrical Characteristics 21.1.5 D/A Conversion Characteristics Table 21.9 lists the D/A conversion characteristics. Table 21.9 D/A Conversion Characteristics Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 to AV = AV...
Page 741: Electrical Characteristics Of Flash Memory And Flash Memory R Versions
Section 21 Electrical Characteristics 21.2 Electrical Characteristics of Flash Memory and Flash Memory R Versions 21.2.1 Absolute Maximum Ratings Table 21.10 lists the absolute maximum ratings. Table 21.10 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +7.0 Programming voltage (FWE) * –0.3 to V +0.3...
Page 742: Dc Characteristics
Section 21 Electrical Characteristics 21.2.2 DC Characteristics Tables 21.11 lists the DC characteristics. Table 21.12 lists the permissible output currents. Table 21.11 DC Characteristics (1) Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = 4.5 V to AV = 0 V * = AV = –20°C to +75°C (regular specifications),...
Page 743 Section 21 Electrical Characteristics Item Symbol Unit Test Conditions Three-state Ports 1 to 6 — — µA = 0.5 V to leakage Ports 8 to B – 0.5 V current Input pull-up Ports 2, 4, –I — µA = 0 V MOS current and 5 Input...
Page 744 Section 21 Electrical Characteristics 2. Given current consumption values are when all the output pins are made to unloaded state and, furthermore, when the on-chip pull-up MOS is turned off under conditions that V min = V – 0.5 V and V max = 0.5 V.
Page 745 Section 21 Electrical Characteristics Table 21.11 DC Characteristics (2) Conditions: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, V = 3.0 V to AV = 0 V * = AV = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) [Programming/erasing conditions: V = 3.0 to 3.6 V, T...
Page 746 Section 21 Electrical Characteristics Item Symbol Unit Test Conditions Three-state Ports 1 to 6 — — µA = 0.5 V to leakage Ports 8 to B – 0.5 V current Input pull-up Ports 2, 4, –I — µA = 0 V MOS current and 5 Input...
Page 747 Section 21 Electrical Characteristics 2. Given current consumption values are when all the output pins are made to unloaded state and, furthermore, when the on-chip pull-up MOS is turned off under conditions that V min = V – 0.5 V and V max = 0.5 V.
Page 748 Section 21 Electrical Characteristics H8/3067 Group 2 kΩ Port Darlington pair Figure 21.4 Darlington Pair Drive Circuit (Example) H8/3067 Group 600 Ω Ports 1, 2, 5 Figure 21.5 Sample LED Circuit Rev. 4.00 Jan 26, 2006 page 724 of 938 REJ09B0276-0400...
Page 749: Ac Characteristics
Section 21 Electrical Characteristics 21.2.3 AC Characteristics Clock timing parameters are listed in table 21.13, control signal timing parameters in table 21.14, and bus timing parameters in table 21.15. Timing parameters of the on-chip supporting modules are listed in table 21.16. Table 21.13 Clock Timing Condition: = –20°C to +75°C (regular specifications), T...
Page 750 Section 21 Electrical Characteristics Table 21.14 Control Signal Timing Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, V = 3.0 to AV = AV = 0 V, fmax = 13 MHz...
Page 751 Section 21 Electrical Characteristics Table 21.15 Bus Timing Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, V = 3.0 to AV = AV = 0 V, fmax = 13 MHz...
Page 752 Section 21 Electrical Characteristics Condition Test Item Symbol Min Unit Conditions Read data access time 1 — 2.0 t — 2.0 t Figure 21.11, ACC1 – 80 – 45 figure 21.12, figure 21.14, Read data access time 2 — 3.0 t —...
Page 753 Section 21 Electrical Characteristics Condition Test Item Symbol Min Unit Conditions RAS access time — 2.5 t — 2.5 t Figure 21.17 – 70 – 40 figure 21.19 Address access time — 2.0 t — 2.0 t – 80 – 50 CAS access time —...
Page 754 Section 21 Electrical Characteristics Table 21.16 Timing of On-Chip Supporting Modules Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, V = 3.0 to AV = AV = 0 V, fmax = 13 MHz...
Page 755 Section 21 Electrical Characteristics Condition Test Item Symbol Min Unit Conditions DMAC TEND delay time 1 — — Figure 21.25, TED1 figure 21.26 TEND delay time 2 — — TED2 DREQ setup time — — Figure 21.27 DRQS DREQ hold time —...
Page 756: A/D Conversion Characteristics
Section 21 Electrical Characteristics 21.2.4 A/D Conversion Characteristics Table 21.17 lists the A/D conversion characteristics. Table 21.17 A/D Conversion Characteristics Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, V = 3.0 to AV = AV...
Page 757 Section 21 Electrical Characteristics Condition Item Unit Conversion Resolution bits time: 70 states Conversion time (single mode) — — — — Analog input capacitance — — — — φ ≤ 13 MHz Permissible — — — — — kΩ signal-source φ...
Page 758: D/A Conversion Characteristics
Section 21 Electrical Characteristics 21.2.5 D/A Conversion Characteristics Table 21.18 lists the D/A conversion characteristics. Table 21.18 D/A Conversion Characteristics Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, V = 3.0 to AV = AV...
Page 759: Flash Memory Characteristics
Section 21 Electrical Characteristics 21.2.6 Flash Memory Characteristics Table 21.19 shows the flash memory characteristics. Table 21.19 Flash Memory Characteristics (1) Conditions: V =4.5 to 5.5V, AV =4.5 to 5.5V, V =0 to +75°C (Programming/erasing operating temperature range: regular specification) =0 to +85°C (Programming/erasing operating temperature range: wide-range specification) Test...
Page 760 Section 21 Electrical Characteristics Table 21.19 Flash Memory Characteristics (2) Conditions: V =3.0 to 3.6 V, AV =3.0 to 3.6 V, V =0 to +75°C (Programming/erasing operating temperature range: regular specification) =0 to +85°C (Programming/erasing operating temperature range: wide-range specification) Test Item Symbol...
Page 761: Operational Timing
Section 21 Electrical Characteristics 21.3 Operational Timing This section shows timing diagrams. 21.3.1 Clock Timing Clock timing is shown as follows: • Oscillator settling timing Figure 21.7 shows the oscillator settling timing. φ STBY OSC1 OSC1 Figure 21.7 Oscillator Settling Timing Rev.
Page 762: Control Signal Timing
Section 21 Electrical Characteristics 21.3.2 Control Signal Timing Control signal timing is shown as follows: • Reset input timing Figure 21.8 shows the reset input timing. • Reset output timing* Figure 21.9 shows the reset output timing. • Interrupt input timing Figure 21.10 shows the interrupt input timing for NMI and IRQ to IRQ φ...
Page 763: Bus Timing
Section 21 Electrical Characteristics φ NMIS NMIH NMIS NMIH NMIS IRQ : Edge-sensitive IRQ : Level-sensitive IRQ (i = 0 to 5) NMIW (j = 0 to 5) Figure 21.10 Interrupt Input Timing 21.3.3 Bus Timing Bus timing is shown as follows: •...
Page 764 Section 21 Electrical Characteristics φ to A PCH1 ACC3 ACC3 PCH2 (read) ACC1 to D (read) PCH1 HWR, LWR (write) WSW1 WDS1 to D (write) Note: Specification from the earliest negation timing of A to A , CSn, and RD. Figure 21.11 Basic Bus Cycle: Two-State Access Rev.
Page 765 Section 21 Electrical Characteristics φ to A ACC4 ACC4 (read) ACC2 to D (read) WSW2 HWR, LWR (write) WDS2 to D (write) Figure 21.12 Basic Bus Cycle: Three-State Access Rev. 4.00 Jan 26, 2006 page 741 of 938 REJ09B0276-0400...
Page 766 Section 21 Electrical Characteristics φ to A RD (read) to D (read) HWR, LWR (write) to D (write) WAIT Figure 21.13 Basic Bus Cycle: Three-State Access with One Wait State Rev. 4.00 Jan 26, 2006 page 742 of 938 REJ09B0276-0400...
Page 767 Section 21 Electrical Characteristics φ to A to A ACC4 ACC4 ACC1 ACC2 to D Note: Specification from the earliest negation timing of A to A , CSn, and RD. Figure 21.14 Burst ROM Access Timing: Two-State Access Rev. 4.00 Jan 26, 2006 page 743 of 938 REJ09B0276-0400...
Page 768 Section 21 Electrical Characteristics φ to A to A ACC4 ACC4 ACC2 ACC2 to D Note: Specification from the earliest negation timing of A to A , CSn, and RD. Figure 21.15 Burst ROM Access Timing: Three-State Access φ BRQS BRQS BREQ BACD2...
Page 769: Dram Interface Bus Timing
Section 21 Electrical Characteristics 21.3.4 DRAM Interface Bus Timing DRAM interface bus timing is shown as follows: • DRAM bus timing: read and write access Figure 21.17 shows the timing of the read and write access. • DRAM bus timing: CAS before RAS refresh Figure 21.18 shows the timing of the CAS before RAS refresh.
Page 770 Section 21 Electrical Characteristics φ to A RAD2 to CS (RAS to RAS RAD1 CASD2 CAS1 UCAS, LCAS (read) RD (WE) High (read) RDH* to D (read) CASD2 CASD1 CAS2 UCAS, LCAS (write) RD (WE) (write) to D (write) RFSH High Note: * Specification from the earliest negation timing of RAS and CAS.
Page 771 Section 21 Electrical Characteristics φ RAD1 RAD2 to CS (RAS CASD1 CASD2 CSR1 UCAS, CAS3 LCAS RD (WE) (high) RAD2 RAD1 CSR1 RFSH Figure 21.18 DRAM Bus Timing (CAS Before RAS Refresh) Rev. 4.00 Jan 26, 2006 page 747 of 938 REJ09B0276-0400...
Page 772: Tpc And I/O Port Timing
Section 21 Electrical Characteristics φ CSR2 to CS (RAS UCAS, LCAS RD (WE) (high) CSR2 RFSH Figure 21.19 DRAM Bus Timing (Self-Refresh) 21.3.5 TPC and I/O Port Timing Figure 21.20 shows the TPC and I/O port input/output timing. φ Port 1 to B (read) Port 1 to 6, 8 to B...
Page 773: Timer Input/Output Timing
Section 21 Electrical Characteristics 21.3.6 Timer Input/Output Timing 16-bit timer and 8-bit timer timing is shown as follows: • Timer input/output timing Figure 21.21 shows the timer input/output timing. • Timer external clock input timing Figure 21.22 shows the timer external clock input timing. φ...
Page 774: Sci Input/Output Timing
Section 21 Electrical Characteristics 21.3.7 SCI Input/Output Timing SCI timing is shown as follows: • SCI input clock timing Figure 21.23 shows the SCI input clock timing. • SCI input/output timing (synchronous mode) Figure 21.24 shows the SCI input/output timing in synchronous mode. SCKW SCKr SCKf...
Page 775: Dmac Timing
Section 21 Electrical Characteristics 21.3.8 DMAC Timing DMAC timing is shown as follows. • DMAC TEND output timing for 2 state access Figure 21.25 shows the DMAC TEND output timing for 2 state access. • DMAC TEND output timing for 3 state access Figure 21.26 shows the DMAC TEND output timing for 3 state access.
Page 776 Section 21 Electrical Characteristics Rev. 4.00 Jan 26, 2006 page 752 of 938 REJ09B0276-0400...
Page 777: Appendix A Instruction Set
Appendix A Instruction Set Appendix A Instruction Set Instruction List Operand Notation Symbol Description General destination register General source register General register General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) (EAd) Destination operand (EAs)
Page 778 Appendix A Instruction Set Condition Code Notation Symbol Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes Rev.
Page 779 Appendix A Instruction Set Table A.1 Instruction Set 1. Data transfer instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z #xx:8 → Rd8   0  MOV.B #xx:8, Rd Rs8 → Rd8 ...
Page 780 Appendix A Instruction Set Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z @aa:24 → Rd16   0  MOV.W @aa:24, Rd Rs16 → @ERd   0  MOV.W Rs, @ERd Rs16 →...
Page 781 Appendix A Instruction Set Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation SP−2 → SP   0  PUSH.W Rn Rn16 → @SP SP−4 → SP   0  PUSH.L ERn ERn32 → @SP MOVFPE @aa:16, Cannot be used in the Cannot be used in the...
Page 782 Appendix A Instruction Set Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z ERd32+1 → ERd32    INC.L #1, ERd ERd32+2 → ERd32    INC.L #2, ERd  * * ...
Page 783 Appendix A Instruction Set Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z ERd32 ÷ Rs16 → ERd32   (6) (7)   DIVXU. W Rs, ERd (Ed: remainder, Rd: quotient) (unsigned division) Rd16 ÷...
Page 784 Appendix A Instruction Set 3. Logic instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z Rd8∧#xx:8 → Rd8   0  AND.B #xx:8, Rd Rd8∧Rs8 → Rd8   0  AND.B Rs, Rd Rd16∧#xx:16 →...
Page 785 Appendix A Instruction Set 4. Shift instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z   SHAL.B Rd   SHAL.W Rd   SHAL.L ERd   SHAR.B Rd   SHAR.W Rd ...
Page 786 Appendix A Instruction Set 5. Bit manipulation instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z (#xx:3 of Rd8) ← 1       BSET #xx:3, Rd (#xx:3 of @ERd) ← 1 ...
Page 787 Appendix A Instruction Set Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z (#xx:3 of @ERd) → C      BLD #xx:3, @ERd (#xx:3 of @aa:8) → C      BLD #xx:3, @aa:8 ¬...
Page 788 Appendix A Instruction Set 6. Branching instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Branch Mnemonic Operation Condition H N Z        BRA d:8 (BT d:8) If condition Always is true then ...
Page 789 Appendix A Instruction Set Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Branch Mnemonic Operation Operation Condition H N Z  Z ∨ (N⊕V) = 1       BLE d:8 If condition is true then ...
Page 790 Appendix A Instruction Set 7. System control instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z PC → @ÐSP 1      TRAPA #x:2 — 14 16 CCR → @ÐSP <vector>...
Page 791 Appendix A Instruction Set 8. Block transfer instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z if R4L ≠ 0       EEPMOV. B — repeat @R5 → @R6 R5+1 →...
Page 792: Operation Code Maps
Appendix A Instruction Set Operation Code Maps Table A.2 Operation Code Map (1) Rev. 4.00 Jan 26, 2006 page 768 of 938 REJ09B0276-0400...
Page 793 Appendix A Instruction Set Table A.2 Operation Code Map (2) Rev. 4.00 Jan 26, 2006 page 769 of 938 REJ09B0276-0400...
Page 794 Appendix A Instruction Set Table A.2 Operation Code Map (3) Rev. 4.00 Jan 26, 2006 page 770 of 938 REJ09B0276-0400...
Page 795: Number Of States Required For Execution
Appendix A Instruction Set Number of States Required for Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8/300H CPU. Table A.4 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction.
Page 796 Appendix A Instruction Set Table A.3 Number of States per Cycle Access Conditions External Device On-Chip Sup- 8-Bit Bus 16-Bit Bus porting Module Execution State On-Chip 8-Bit 16-Bit 2-State 3-State 2-State 3-State (Cycle) Memory Access Access Access Access Instruction fetch 6 + 2m 3 + m Branch address read S...
Page 797 Appendix A Instruction Set Table A.4 Number of Cycles per Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS...
Page 798 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16...
Page 799 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BNOT BNOT #xx:3, Rd BNOT #xx:3, @ERd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @ERd BNOT Rn, @aa:8 BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8...
Page 800 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic DEC.B Rd DEC.W #1/2, Rd DEC.L #1/2, ERd DIVXS DIVXS.B Rs, Rd DIVXS.W Rs, ERd DIVXU DIVXU.B Rs, Rd DIVXU.W Rs, ERd 2n + 2 * EEPMOV EEPMOV.B...
Page 801 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd...
Page 802 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOVFPE MOVFPE @aa:16, Rd * MOVTPE Rs, @aa:16 * MOVTPE MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd MULXU MULXU.B Rs, Rd MULXU.W Rs, ERd NEG.B Rd NEG.W Rd...
Page 803 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic Normal Advanced 2 SHAL SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR.B Rd...
Page 804: Appendix B Internal I/O Registers
Appendix B Internal I/O Registers Appendix B Internal I/O Registers Addresses Data Bit Names Address Register Module (Low) Name Width Bit 7 Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'EE000 P1DDR DDR P1 DDR P1 DDR P1 DDR P1...
Page 805 Appendix B Internal I/O Registers Data Bit Names Address Register Module (Low) Name Width Bit 7 Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'EE020 ABWCR ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Bus controller H'EE021...
Page 806 Appendix B Internal I/O Registers Data Bit Names Address Register Module (Low) Name Width Bit 7 Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'EE040 — — — — — — — — —...
Page 807 Appendix B Internal I/O Registers Data Bit Names Address Register Module (Low) Name Width Bit 7 Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'EE060 — — — — — — — — —...
Page 808 Appendix B Internal I/O Registers Data Bit Names Address Register Module (Low) Name Width Bit 7 Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFF20 MAR0AR DMAC channel 0A H'FFF21 MAR0AE H'FFF22 MAR0AH H'FFF23 MAR0AL H'FFF24...
Page 809 Appendix B Internal I/O Registers Data Bit Names Address Register Module (Low) Name Width Bit 7 Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFF40 — — — — — — — — —...
Page 810 Appendix B Internal I/O Registers Data Bit Names Address Register Module (Low) Name Width Bit 7 Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFF60 TSTR — — — — — STR2 STR1 STR0 16-bit timer, (all channels)
Page 811 Appendix B Internal I/O Registers Data Bit Names Address Register Module (Low) Name Width Bit 7 Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 8-bit timer H'FFF80 TCR0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0...
Page 812 Appendix B Internal I/O Registers Data Bit Names Module Address Register Name (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFFA0 TPMR — — — — G3NOV G2NOV G1NOV G0NOV H'FFFA1 TPCR G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0...
Page 813 Appendix B Internal I/O Registers Data Bit Names Address Register Module (Low) Name Width Bit 7 Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFFC0 STOP CKS1 CKS0 channel 2 H'FFFC1 H'FFFC2 MPIE TEIE CKE1 CKE0...
Page 814 Appendix B Internal I/O Registers Data Bit Names Address Register Module (Low) Name Width Bit 7 Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFFE0 ADDRAH 8 A/D converter H'FFFE1 ADDRAL 8 — —...
Page 815: Functions
Appendix B Internal I/O Registers Functions Register abbreviation Address to which register is mapped Register name Name of on-chip supporting module TIERTimer Interrupt Enable Register H' 90 Bit numbers  ICIAE ICIBE ICICE OCIDE OCIAE OCIBE OVIE Initial bit values Names of the bits.
Page 816 Appendix B Internal I/O Registers P1DDR—Port 1 Data Direction Register H’EE000 Port 1 Initial value Modes 1 to 4         Read/Write Initial value Modes 5 to 7 Read/Write Port 1 input/output select Generic input Generic output P2DDR—Port 2 Data Direction Register H’EE001...
Page 817 Appendix B Internal I/O Registers P3DDR—Port 3 Data Direction Register H’EE002 Port 3 Initial value Read/Write Port 3 input/output select Generic input Generic output P4DDR—Port 4 Data Direction Register H’EE003 Port 4 Initial value Read/Write Port 4 input/output select Generic input Generic output P5DDR—Port 5 Data Direction Register H’EE004...
Page 818 Appendix B Internal I/O Registers P6DDR—Port 6 Data Direction Register H’EE005 Port 6  Initial value  Read/Write Port 6 input/output select Generic input Generic output P8DDR—Port 8 Data Direction Register H’EE007 Port 8    Initial value Modes 1 to 4 ...
Page 819 Appendix B Internal I/O Registers P9DDR—Port 9 Data Direction Register H’EE008 Port 9   Initial value   Read/Write Port 9 input/output select Generic input Generic output PADDR—Port A Data Direction Register H’EE009 Port A Initial value Modes 3, 4 ...
Page 820 Appendix B Internal I/O Registers MDCR—Mode Control Register H’EE011 System control      MDS2 MDS1 MDS0 * * * Initial value      Read/Write Mode select 2 to 0 Bit 2 Bit 1 Bit 0 Operating Mode ...
Page 821 Appendix B Internal I/O Registers SYSCR—System Control Register H’EE012 System control SSBY STS2 STS1 STS0 NMIEG SSOE RAME Initial value Read/Write RAM enable On-chip RAM is disabled On-chip RAM is enabled Software standby output port enable In software standby mode, all address bus and bus control signals are high- impedance...
Page 822 Appendix B Internal I/O Registers BRCR—Bus Release Control Register H’EE013 Bus controller    A23E A22E A21E A20E BRLE Modes Initial value        1, 2, 6, 7 Read/Write Modes Initial value   ...
Page 823 Appendix B Internal I/O Registers IER—IRQ Enable Register H’EE015 Interrupt Controller   IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value Read/Write to IRQ enable to IRQ interrupts are disabled to IRQ interrupts are enabled ISR—IRQ Status Register H’EE016 Interrupt Controller ...
Page 824 Appendix B Internal I/O Registers IPRA—Interrupt Priority Register A H’EE018 Interrupt Controller IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 Initial value Read/Write Priority level A7 to A0 Priority level 0 (low priority) Priority level 1 (high priority) • Interrupt sources controlled by each bit Bit 7 Bit 6 Bit 5...
Page 825 Appendix B Internal I/O Registers DASTCR—D/A Standby Control Register H’EE01A        DASTE Initial value        Read/Write D/A standby enable D/A output is disabled in software standby mode (Initial value) D/A output is enabled in software standby mode DIVCR—Division Control Register H’EE01B...
Page 826 Appendix B Internal I/O Registers MSTCRH—Module Standby Control Register H H’EE01C System control     PSTOP MSTPH2 MSTPH1 MSTPH0 Initial value     Read/Write Module standby H2 to H0 Selection bits for placing modules in standby state. Reserved bits φ...
Page 827 Appendix B Internal I/O Registers ADRCR—Address Control Register H’EE01E Bus controller        ADRCTL Initial value        Read/Write Reserved bits Address control Selects address update mode 1 or address update mode 2.
Page 828 Appendix B Internal I/O Registers ABWCR—Bus Width Control Register H’EE020 Bus controller ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Modes 1, 3, 5, 6, 7 Initial value Modes 2, 4 Initial value Read/Write Area 7 to 0 bus width control Bits 7 to 0 Bus Width of Access Area ABW7...
Page 829 Appendix B Internal I/O Registers WCRH—Wait Control Register H H’EE022 Bus controller Initial value Read/Write Area 4 wait control 1 and 0 No program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted Area 5 wait control 1 and 0 No program wait is inserted 1 program wait state is inserted...
Page 830 Appendix B Internal I/O Registers WCRL—Wait Control Register L H’EE023 Bus controller Initial value Read/Write Area 0 wait control 1 and 0 No program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted Area 1 wait control 1 and 0 No program wait is inserted 1 program wait state is inserted...
Page 831 Appendix B Internal I/O Registers BCR—Bus Control Register H’EE024 Bus controller  ICIS1 ICIS0 BROME BRSTS1 BRSTS0 RDEA WAITE Initial value  Read/Write Wait pin enable WAIT pin wait input is disabled WAIT pin wait input is enabled Area division unit select Area divisions are as follows: Area 0: 2 MB Area 4: 1.93 MB...
Page 832 Appendix B Internal I/O Registers DRCRA—DRAM Control Register A H’EE026 DRAM interface  DRAS2 DRAS1 DRAS0 SRFMD RFSHE Initial value  Read/Write Refresh pin enable RFSH pin refresh signal output is disabled RFSH pin refresh signal output is enabled Self-refresh mode DRAM self-refreshing is disabled in software standby mode DRAM self-refreshing is enabled...
Page 833 Appendix B Internal I/O Registers DRCRB—DRAM Control Register B H’EE027 DRAM interface  MXC1 MXC0 CSEL RCYCE Initial value  Read/Write Refresh cycle wait control Wait state (T ) insertion is disabled 1 wait state (T ) is inserted RAS-CAS wait Wait state (T ) insertion is disabled 1 wait state (T...
Page 834 Appendix B Internal I/O Registers RTMCSR—Refresh Timer Control/Status Register H’EE028 DRAM interface    CMIE CKS2 CKS1 CKS0 Initial value    Read/Write R/(W)* Refresh counter clock select CKS0 Description CKS2 CKS1 Count operation halted φ/2 used as counter clock φ/8 used as counter clock φ/32 used as counter clock φ/128 used as counter clock...
Page 835 Appendix B Internal I/O Registers RTCNT—Refresh Timer Counter H’EE029 DRAM interface Initial value Read/Write Incremented by internal clock selected by bits CKS2 to CKS0 in RTMCSR RTCOR—Refresh Time Constant Register H’EE02A DRAM interface Initial value Read/Write RTCNT compare match period Note: Only byte access can be used on this register.
Page 836 Appendix B Internal I/O Registers FLMCR-Flash Memory Control Register H'EE030 Flash Memory Modes 1 to Initial value 4, and 6 Read/Write Modes 5 Initial value and 7 Read/Write Program mode Program mode cleared (Initial value) Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 Erase mode Erase mode cleared (Initial value)
Page 837 Appendix B Internal I/O Registers EBR-Erase Block Register H'EE032 Flash Memory Modes 1 to Initial value 4, and 6 Read/Write Modes 5 Initial value and 7 Read/Write Block 7 to 0 Block EB7 to EB0 is not selected (Initial value) Block EB7 to EB0 is selected Note: When not erasing flash memory, EBR should be cleared to H'00.
Page 838 Appendix B Internal I/O Registers P4PCR—Port 4 Input Pull-Up Control Register H’EE03E Port 4 Initial value Read/Write Port 4 input pull-up control 7 to 0 Input pull-up transistor is off Input pull-up transistor is on Note: Valid when the corresponding P4DDR bit is cleared to 0 (designating generic input).
Page 839 Appendix B Internal I/O Registers RAM Control Register RAMCR H'EE077 Flash Memory  — — — RAMS RAM2 RAM1 — Modes Initial value      1 to 4 Modes Initial value      5 to 7 R/W* R/W* R/W*...
Page 840 Appendix B Internal I/O Registers FLMSR-Flash Memory Status Register H'EE07D Flash Memory        FLER Initial value        Reserved bits RAM select, RAM2, RAM1 Bit 7 Description FLER Flash memory program/erase protection (error protection) is disabled (Initial value) [Clearing condition] WDT reset, reset via the RES pin or hardware standby mode An error has occurred during flash memory programming/erasing, and error pro-...
Page 841 Appendix B Internal I/O Registers MAR0A R/E/H/L—Memory Address Register 0A R/E/H/L H’FFF20 H’FFF21 DMAC0 H’FFF22 H’FFF23 Undetermined Initial value         Read/Write R/W R/W R/W R/W R/W R/W MAR0AR MAR0AE Undetermined Undetermined Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...
Page 842 Appendix B Internal I/O Registers ETCR0A H/L—Execute Transfer Count Register 0A H/L H’FFF24 H’FFF25 DMAC0 • Short address mode  I/O mode and idle mode Undetermined Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter ...
Page 843 Appendix B Internal I/O Registers IOAR0A—I/O Address Register 0A H’FFF26 DMAC0 Undetermined Initial value Read/Write Short address mode : source or destination address Full address mode : not used Rev. 4.00 Jan 26, 2006 page 819 of 938 REJ09B0276-0400...
Page 844 Appendix B Internal I/O Registers DTCR0A—Data Transfer Control Register 0A H’FFF27 DMAC0 • Short address mode DTSZ DTID DTIE DTS2 DTS1 DTS0 Initial value Read/Write Data transfer select Bit 2 Bit 1 Bit 0 Data Transfer Activation Source DTS2 DTS1 DTS0 Compare match/input capture A interrupt from 16-bit timer channel 0...
Page 845 Appendix B Internal I/O Registers DTCR0A—Data Transfer Control Register 0A (cont) H’FFF27 DMAC0 • Full address mode DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A Initial value Read/Write Data transfer select 0A Normal mode Block transfer mode Data transfer select 2A and 1A Set both bits to 1 Data transfer interrupt enable Interrupt requested by DTE bit is disabled...
Page 846 Appendix B Internal I/O Registers MAR0B R/E/H/L—Memory Address Register 0B R/E/H/L H’FFF28 H’FFF29 DMAC0 H’FFF2A H’FFF2B Undetermined Initial value         Read/Write R/W R/W R/W R/W R/W R/W MAR0BR MAR0BE Undetermined Undetermined Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...
Page 847 Appendix B Internal I/O Registers ETCR0B H/L—Execute Transfer Count Register 0B H/L H’FFF2C, DMAC0 H’FFF2D • Short address mode  I/O mode and idle mode Undetermined Initial value R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Read/Write Transfer counter ...
Page 848 Appendix B Internal I/O Registers IOAR0B—I/O Address Register 0B H’FFF2E DMAC0 Undetermined Initial value Read/Write Short address mode : source or destination address Full address mode : not used Rev. 4.00 Jan 26, 2006 page 824 of 938 REJ09B0276-0400...
Page 849 Appendix B Internal I/O Registers DTCR0B—Data Transfer Control Register 0B H’FFF2F DMAC0 • Short address mode DTSZ DTID DTIE DTS2 DTS1 DTS0 Initial value Read/Write Data transfer select Bit 2 Bit 1 Bit 0 Data Transfer Activation Source DTS2 DTS1 DTS0 Compare match/input capture A interrupt from 16-bit timer channel 0...
Page 850 Appendix B Internal I/O Registers DTCR0B—Data Transfer Control Register 0B (cont) H’FFF2F DMAC0 • Full address mode  DTME DAID DAIDE DTS2B DTS1B DTS0B Initial value Read/Write Data transfer select 2B to 0B Data transfer master enable Bit 2 Bit 1 Bit 0 Data Transfer Activation Source Data transfer is disabled...
Page 851 Appendix B Internal I/O Registers MAR1A R/E/H/L—Memory Address Register 1A R/E/H/L H’FFF30 H’FFF31 DMAC1 H’FFF32 H’FFF33 Undetermined Initial value         Read/Write R/W R/W R/W R/W R/W R/W MAR1AR MAR1AE Undetermined Undetermined Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...
Page 852 Appendix B Internal I/O Registers IOAR1A—I/O Address Register 1A H’FFF36 DMAC1 Undetermined Initial value Read/Write Note: Bit functions are the same as for DMAC0. DTCR1A—Data Transfer Control Register 1A H’FFF37 DMAC1 • Short address mode DTSZ DTID DTIE DTS2 DTS1 DTS0 Initial value Read/Write...
Page 853 Appendix B Internal I/O Registers MAR1B R/E/H/L—Memory Address Register 1B R/E/H/L H’FFF38 H’FFF39 DMAC1 H’FFF3A H’FFF3B Undetermined Initial value         Read/Write R/W R/W R/W R/W R/W R/W MAR1BR MAR1BE Undetermined Undetermined Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...
Page 854 Appendix B Internal I/O Registers IOAR1B—I/O Address Register 1B H’FFF3E DMAC1 Undetermined Initial value Read/Write Note: Bit functions are the same as for DMAC0. DTCR1B—Data Transfer Control Register 1B H’FFF3F DMAC1 • Short address mode DTSZ DTID DTIE DTS2 DTS1 DTS0 Initial value Read/Write...
Page 855 Appendix B Internal I/O Registers TSTR—Timer Start Register H’FFF60 16-bit timer (all channels)      STR2 STR1 STR0 Initial value      Read/Write Reserved bits Counter start 0 TCNT0 is halted (Initial value) TCNT0 is counting Counter start 1 TCNT1 is halted (Initial value)
Page 856 Appendix B Internal I/O Registers TSNC—Timer Synchro Register H’FFF61 16-bit timer (all channels)      SYNC2 SYNC1 SYNC0 Initial value      Read/Write Reserved bits Timer synchronization 0 Channel 0 timer counter (TCNT0) operates independently (TCNT0 presetting/clearing is unrelated to other channels) (Initial value)
Page 857 Appendix B Internal I/O Registers TMDR—Timer Mode Register H’FFF62 16-bit timer (all channels)    FDIR PWM2 PWM1 PWM0 Initial value    Read/Write PWM mode 0 Channel 0 operates normally (Initial value) Channel 0 operates in PWM mode PWM mode 1 Channel 1 operates normally (Initial value) Channel 1 operates in PWM mode...
Page 858 Appendix B Internal I/O Registers TOLR—Timer Output Level Setting Register H’FFF63 16-bit timer (all channels)   TOB2 TOA2 TOB1 TOA1 TOB0 TOA0 Initial value   Read/Write Output level setting A0 TIOCA is 0 (Initial value) TIOCA is 1 Output level setting B0 TIOCB is 0...
Page 859 Appendix B Internal I/O Registers TISRA—Timer Interrupt Status Register A H’FFF64 16-bit timer (all channels) Bit:   IMIEA2 IMIEA1 IMIEA0 IMFA2 IMFA1 IMFA0 Initial value:   Read/Write: R/(W)* R/(W)* R/(W)* Input capture/compare match flag A0 [Clearing conditions] (Initial value) Read IMFA0 when IMFA0=1, then write 0 in IMFA0 DMAC activated by IMIA0 interrupt.
Page 860 Appendix B Internal I/O Registers TISRB—Timer Interrupt Status Register B H’FFF65 16-bit timer (all channels) Bit:   IMIEB2 IMIEB1 IMIEB0 IMFB2 IMFB1 IMFB0 Initial value:   Read/Write: R/(W)* R/(W)* R/(W)* Input capture/compare match flag B0 [Clearing condition] (Initial value) Read IMFB0 when IMFB0=1, then write 0 in IMFB0.
Page 861 Appendix B Internal I/O Registers TISRC—Timer Interrupt Status Register C H’FFF66 16-bit timer (all channels) Bit:   OVIE2 OVIE1 OVIE0 OVF2 OVF1 OVF0 Initial value:   Read/Write: R/(W)* R/(W)* R/(W)* Overflow flag 0 [Clearing condition] (Initial value) Read OVF0 when OVF0 = 1, then write 0 in OVF0. [Setting condition] TCNT0 overflowed from H'FFFF to H'0000.
Page 862 Appendix B Internal I/O Registers TCR0—Timer Control Register H’FFF68 16-bit timer channel 0  CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value  Read/Write Timer prescaler 2 to 0 Bit 2 Bit 1 Bit 0 TCNT Clock Source TPSC2 TPSC1 TPSC0 Internal clock : φ...
Page 863 Appendix B Internal I/O Registers TIOR0—Timer I/O Control Register 0 H’FFF69 16-bit timer channel 0 Bit:   IOB2 IOB1 IOB0 IOA2 IOA1 IOA0 Initial value:   Read/Write: I/O control A2 to A0 Bit 2 Bit 1 Bit 0 GRA Functions IOA2 IOA1...
Page 864 Appendix B Internal I/O Registers TCNT0 H/L—Timer Counter 0 H/L H’FFF6A, H’FFF6B 16-bit timer channel 0 Initial value Read/Write Up - counter GRA0 H/L—General Register A0 H/L H’FFF6C, H’FFF6D 16-bit timer channel 0 Initial value Read/Write Output compare or input capture register GRB0 H/L—General Register B0 H/L H’FFF6E, H’FFF6F 16-bit timer channel 0...
Page 865 Appendix B Internal I/O Registers TCR1 Timer Control Register 1 H’FFF70 16-bit timer channel 1  CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value  Read/Write * Bit functions are the same as for 16-bit timer channel 0. TIOR1—Timer I/O Control Register 1 H’FFF71 16-bit timer channel 1 ...
Page 866 Appendix B Internal I/O Registers GRA1 H/L—General Register A1 H/L H’FFF74, H’FFF75 16-bit timer channel 1 Initial value Read/Write * Bit functions are the same as for 16-bit timer channel 0. GRB1 H/L—General Register B1 H/L H’FFF76, H’FFF77 16-bit timer channel 1 Initial value Read/Write * Bit functions are the same as for 16-bit timer channel 0.
Page 867 Appendix B Internal I/O Registers TIOR2—Timer I/O Control Register 2 H’FFF79 16-bit timer channel 2   IOB2 IOB1 IOB0 IOA2 IOA1 IOA0 Initial value   Read/Write * Bit functions are the same as for 16-bit timer channel 0. TCNT2 H/L—Timer Counter 2 H/L H’FFF7A, H’FFF7B 16-bit timer channel 2...
Page 868 Appendix B Internal I/O Registers GRB2 H/L—General Register B2 H/L H’FFF7E, H’FFF7F 16-bit timer channel 2 Initial value Read/Write * Bit functions are the same as for 16-bit timer channel 0. Rev. 4.00 Jan 26, 2006 page 844 of 938 REJ09B0276-0400...
Page 869 Appendix B Internal I/O Registers TCR0—Timer Control Register 0 H’FFF80 8-bit timer channel 0 TCR1—Timer Control Register 1 H’FFF81 8-bit timer channel 1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value Read/Write Clock select 2 to 0 Clock input is disabled Internal clock, counted on rising edge of φ/8 Internal clock, counted on rising...
Page 870 Appendix B Internal I/O Registers TCSR0—Timer Control/Status Register 0 H’FFF82 8-bit timer channel 0 CMFB CMFA ADTE OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* Output select A1 and A0 Bit 1 Bit 0 Description No change at compare match A 0 output at compare match A 1 output at compare match A Output toggles at compare...
Page 871 Appendix B Internal I/O Registers TCSR1—Timer Control/Status Register 1 H’FFF83 8-bit timer channel 1 CMFB CMFA OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* Output select A1 and A0 Bit 1 Bit 0 Description No change at compare match A 0 output at compare match A 1 output at compare match A Output toggles at compare...
Page 872 Appendix B Internal I/O Registers TCORA0—Time Constant Register A0 H’FFF84 8-bit timer channel 0 TCORA1—Time Constant Register A1 H’FFF85 8-bit timer channel 1 TCORA0 TCORA1 Initial value Read/Write TCORB0—Time Constant Register B0 H’FFF86 8-bit timer channel 0 TCORB1—Time Constant Register B1 H’FFF87 8-bit timer channel 1 TCORB0...
Page 873 Appendix B Internal I/O Registers TCSR—Timer Control/Status Register H’FFF8C   WT/IT CKS2 CKS1 CKS0 Initial value   Read/Write R/(W)* Clock select 2 to 0 CKS2 CKS1 CKS0 Description φ/2 φ/32 φ/64 φ/128 φ/256 φ/512 φ/2048 φ/4096 Timer enable Timer disabled •...
Page 874 Appendix B Internal I/O Registers TCNT—Timer Counter H'FFF8D (read), H'FFF8C (write) Initial value Read/Write Count value RSTCSR—Reset Control/Status Register H'FFF8F (read), H'FFF8E (write)       WRST RSTOE Initial value       Read/Write R/(W)* Reset output enable External output of reset signal is disabled...
Page 875 Appendix B Internal I/O Registers TCR2—Timer Control Register 2 H’FFF90 8-bit timer channel 2 TCR3—Timer Control Register 3 H’FFF91 8-bit timer channel 3 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value Read/Write Clock select 2 to 0 CSK2 CSK1 CSK0 Description Clock input is disabled Internal clock, counted on rising edge...
Page 876 Appendix B Internal I/O Registers TCSR2—Timer Control/Status Register 2 H’FFF92 8-bit timer channel 2 TCSR3—Timer Control/Status Register 3 H’FFF93 8-bit timer channel 3 TCSR2  CMFB CMFA OIS3 OIS2 Initial value  Read/Write R/(W)* R/(W)* R/(W)* TCSR3 CMFB CMFA OIS3 OIS2 Initial value Read/Write...
Page 877 Appendix B Internal I/O Registers TCORA2—Time Constant Register A2 H’FFF94 8-bit timer channel 2 TCORA3—Time Constant Register A3 H’FFF95 8-bit timer channel 3 TCORA2 TCORA3 Initial value Read/Write TCORB2—Time Constant Register B2 H’FFF96 8-bit timer channel 2 TCORB3—Time Constant Register B3 H’FFF97 8-bit timer channel 3 TCORB2...
Page 878 Appendix B Internal I/O Registers DADR0—D/A Data Register 0 H’FFF9C Initial value Read/Write D/A conversion data DADR1—D/A Data Register 1 H’FFF9D Initial value Read/Write D/A conversion data Rev. 4.00 Jan 26, 2006 page 854 of 938 REJ09B0276-0400...
Page 879 Appendix B Internal I/O Registers DACR—D/A Control Register H’FFF9E      DAOE1 DAOE0 Initial value      Read/Write D/A enable Bit 7 Bit 6 Bit 5 Description DAOE1 DAOE0  D/A conversion is disabled in channels 0 and 1 D/A conversion is enabled in channel 0...
Page 880 Appendix B Internal I/O Registers TPMR—TPC Output Mode Register H’FFFA0     G3NOV G2NOV G1NOV G0NOV Initial value     Read/Write Group 0 non-overlap Normal TPC output in group 0. Output values change at compare match A in the selected 16-bit timer channel Non-overlapping TPC output in group 0, controlled by compare match A and B in the...
Page 881 Appendix B Internal I/O Registers TPCR—TPC Output Control Register H’FFFA1 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 0 compare match select 1 and 0 Bit 1 Bit 0 16-Bit Timer Channel Selected as Output Trigger G0CMS1 G0CMS0 TPC output group 0 (TP...
Page 882 Appendix B Internal I/O Registers NDERB—Next Data Enable Register B H’FFFA2 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value Read/Write Next data enable 15 to 8 Bits 7 to 0 Description NDER15 to NDER8 TPC outputs TP to TP are disabled (NDR15 to NDR8 are not transferred to PB to PB...
Page 883 Appendix B Internal I/O Registers NDRB—Next Data Register B H’FFFA4/H’FFFA6 • Same trigger for TPC output groups 2 and 3  Address H'FFFA4 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value Read/Write Store the next output data for TPC output group 3 Store the next output data for TPC output group 2 ...
Page 884 Appendix B Internal I/O Registers NDRA—Next Data Register A H’FFFA5/H’FFFA7 • Same trigger for TPC output groups 0 and 1  Address H'FFFA5 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value Read/Write Store the next output data for TPC output group 1 Store the next output data for TPC output group 0 ...
Page 885 Appendix B Internal I/O Registers SMR—Serial Mode Register H’FFFB0 SCI0 STOP CKS1 CKS0 Initial value Read/Write Clock select 1 and 0 Bit 1 Bit 0 Clock Source CKS1 CKS0 φ clock φ/4 clock φ/16 clock φ/64 clock Multiprocessor mode Multiprocessor function disabled Multiprocessor format selected Stop bit length One stop bit...
Page 886 Appendix B Internal I/O Registers BRR—Bit Rate Register H’FFFB1 SCI0 Initial value Read/Write Serial communication bit rate setting Rev. 4.00 Jan 26, 2006 page 862 of 938 REJ09B0276-0400...
Page 887 Appendix B Internal I/O Registers SCR—Serial Control Register H’FFFB2 SCI0 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock enable 1 and 0 Receive enable (for serial communication interface) Receiving is Bit 1 Bit 0 Description disabled CKE1 CKE0 Receiving is Internal clock, SCK pin Asynchronous mode enabled...
Page 888 Appendix B Internal I/O Registers TDR—Transmit Data Register H’FFFB3 SCI0 Initial value Read/Write Serial transmit data Rev. 4.00 Jan 26, 2006 page 864 of 938 REJ09B0276-0400...
Page 889 Appendix B Internal I/O Registers SSR—Serial Status Register H’FFFB4 SCI0 TDRE RDRF ORER FER/ERS TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Multiprocessor bit transfer Multiprocessor bit value in transmit data is 0 Multiprocessor bit value in transmit data is 1 Multiprocessor bit Multiprocessor bit value in receive data is 0 Multiprocessor bit value in receive data is 1...
Page 890 Appendix B Internal I/O Registers RDR—Receive Data Register H’FFFB5 SCI0 Initial value Read/Write Serial receive data Rev. 4.00 Jan 26, 2006 page 866 of 938 REJ09B0276-0400...
Page 891 Appendix B Internal I/O Registers SCMR—Smart Card Mode Register H’FFFB6 SCI0      SDIR SINV SMIF Initial value      Read/Write Smart card interface mode select Smart card interface function is disabled (Initial value) Smart card interface function is enabled Smart card data invert Unmodified TDR contents are transmitted...
Page 892 Appendix B Internal I/O Registers SMR—Serial Mode Register H’FFFB8 SCI1 STOP CKS1 CKS0 Initial value Read/Write Note: Bit functions are the same as for SCI0. BRR—Bit Rate Register H’FFFB9 SCI1 Initial value Read/Write Note: Bit functions are the same as for SCI0. SCR—Serial Control Register H’FFFBA SCI1...
Page 893 Appendix B Internal I/O Registers TDR—Transmit Data Register H’FFFBB SCI1 Initial value Read/Write Note: Bit functions are the same as for SCI0. SSR—Serial Status Register H’FFFBC SCI1 TDRE RDRF ORER FER/ERS TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: Bit functions are the same as for SCI0.
Page 894 Appendix B Internal I/O Registers SCMR—Smart Card Mode Register H’FFFBE SCI1      SDIR SINV SMIF Initial value      Read/Write Note: Bit functions are the same as for SCI0. SMR—Serial Mode Register H’FFFC0 SCI2 STOP CKS1...
Page 895 Appendix B Internal I/O Registers SCR—Serial Control Register H’FFFC2 SCI2 MPIE TEIE CKE1 CKE0 Initial value Read/Write Note: Bit functions are the same as for SCI0. TDR—Transmit Data Register H’FFFC3 SCI2 Initial value Read/Write Note: Bit functions are the same as for SCI0. SSR—Serial Status Register H’FFFC4 SCI2...
Page 896 Appendix B Internal I/O Registers RDR—Receive Data Register H’FFFC5 SCI2 Initial value Read/Write Note: Bit functions are the same as for SCI0. SCMR—Smart Card Mode Register H’FFFC6 SCI2      SDIR SINV SMIF Initial value   ...
Page 897 Appendix B Internal I/O Registers P2DR—Port 2 Data Register H’FFFD1 Port 2 Initial value Read/Write Data for port 2 pins P3DR—Port 3 Data Register H’FFFD2 Port 3 Initial value Read/Write Data for port 3 pins P4DR—Port 4 Data Register H’FFFD3 Port 4 Initial value Read/Write...
Page 898 Appendix B Internal I/O Registers P5DR—Port 5 Data Register H’FFFD4 Port 5     Initial value     Read/Write Data for port 5 pins P6DR—Port 6 Data Register H’FFFD5 Port 6 Initial value Read/Write Data for port 6 pins P7DR—Port 7 Data Register H’FFFD6 Port 7...
Page 899 Appendix B Internal I/O Registers P8DR—Port 8 Data Register H’FFFD7 Port 8    Initial value    Read/Write Data for port 8 pins P9DR—Port 9 Data Register H’FFFD8 Port 9   Initial value   Read/Write Data for port 9 pins PADR—Port A Data Register H’FFFD9...
Page 900 Appendix B Internal I/O Registers PBDR—Port B Data Register H’FFFDA Port B Initial value Read/Write Data for port B pins ADDRA H/L—A/D Data Register A H/L H’FFFE0, H’FFFE1       Initial value Read/Write ADDRAH ADDRAL A/D conversion data 10-bit data giving an A/D conversion result ADDRB H/L—A/D Data Register B H/L H’FFFE2, H’FFFE3...
Page 901 Appendix B Internal I/O Registers ADDRC H/L—A/D Data Register C H/L H’FFFE4, H’FFFE5       Initial value Read/Write ADDRCH ADDRCL A/D conversion data 10-bit data giving an A/D conversion result ADDRD H/L—A/D Data Register D H/L H’FFFE6, H’FFFE7 ...
Page 902 Appendix B Internal I/O Registers ADCSR—A/D Control/Status Register H’FFFE8 ADIE ADST SCAN Initial value Read/Write R/(W)* Channel select 2 to 0 Clock select Conversion time = Description Group Selection Channel Selection 134 states (maximum) CH1 CH0 Single Mode Scan Mode Conversion time = 70 states (maximum) to AN...
Page 903: Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams Port 1 Block Diagram Software SSOE standby Mode 6/7 Hardware standby External bus released Reset Mode 1 to 4 P1 DDR WP1D Reset Mode 6/7 P1 DR Mode 1 to 5 WP1D: Write to P1DDR...
Page 904: Port 2 Block Diagram
Appendix C I/O Port Block Diagrams Port 2 Block Diagram Software Reset standby SSOE P2 PCR RP2P WP2P Mode 6/7 Hardware standby Reset External bus Mode 1 to 4 released P2 DDR WP2D Reset Mode 6/7 P2 DR Mode 1 to 5 WP2P: Write to P2PCR RP2P:...
Page 905: Port 3 Block Diagram
Appendix C I/O Port Block Diagrams Port 3 Block Diagram Reset Hardware standby External Mode 6/7 bus released P3 DDR Write to external address WP3D Reset Mode 6/7 P3 DR Mode 1 to 5 Read external address WP3D: Write to P3DDR WP3: Write to port 3 RP3:...
Page 906: Port 4 Block Diagram
Appendix C I/O Port Block Diagrams Port 4 Block Diagram 8-bit bus 16-bit bus mode mode Mode Mode 6/7 1 to 5 Reset P4 PCR RP4P WP4P Reset Hardware standby Write to external P4 DDR address External bus release WP4D Reset P4 DR Read external...
Page 907: Port 5 Block Diagram
Appendix C I/O Port Block Diagrams Port 5 Block Diagram Software standby SSOE Reset P5 PCR RP5P WP5P Mode 6/7 Hardware standby External bus released Mode 1 to 4 Reset P5 DDR WP5D Reset Mode 6/7 P5 DR Mode 1 to 5 WP5P: Write to P5PCR RP5P:...
Page 908: Port 6 Block Diagrams
Appendix C I/O Port Block Diagrams Port 6 Block Diagrams Reset Hardware standby P6 DDR Bus controller WAIT WP6D Mode 6/7 input Reset enable P6 DR Bus controller WAIT WP6D: Write to P6DDR input WP6: Write to port 6 RP6: Read port 6 Figure C.6 (a) Port 6 Block Diagram (Pin P6 Rev.
Page 909 Appendix C I/O Port Block Diagrams Reset controller Hardware standby P6 DDR Mode 6/7 WP6D Bus release enable Reset P6 DR BREQ input WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C.6 (b) Port 6 Block Diagram (Pin P6 Rev.
Page 910 Appendix C I/O Port Block Diagrams Reset Hardware standby P6 DDR WP6D Reset P6 DR Bus controller Mode 6/7 Bus release enable BACK output WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C.6 (c) Port 6 Block Diagram (Pin P6 Rev.
Page 911 Appendix C I/O Port Block Diagrams SSOE Software standby Mode 6/7 Hardware standby External bus released Reset P6 DDR Mode 6/7 WP6D Reset Mode 6/7 P6 DR Mode 1 to 5 Bus controller AS output WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6...
Page 912 Appendix C I/O Port Block Diagrams SSOE Software standby Mode 6/7 Hardware standby External bus released Reset P6 DDR Mode 6/7 WP6D Reset Mode 6/7 Bus controller Mode P6 DR 1 to 5 WE output enable RD output WE output WP6D: Write to P6DDR WP6:...
Page 913 Appendix C I/O Port Block Diagrams SSOE Software standby Mode 6/7 Hardware standby External bus released Reset P6 DDR Mode 6/7 WP6D Reset Mode 6/7 Bus controller Mode P6 DR 1 to 5 CAS output enable HWR output LWR output UCAS output LCAS output WP6D:...
Page 914 Appendix C I/O Port Block Diagrams Hardware standby φ output enable φ output RP6: Read port 6 Figure C.6 (g) Port 6 Block Diagram (Pin P6 Rev. 4.00 Jan 26, 2006 page 890 of 938 REJ09B0276-0400...
Page 915: Port 7 Block Diagrams
Appendix C I/O Port Block Diagrams Port 7 Block Diagrams A/D converter Analog input Input enable RP7: Read port 7 Channel select signal n = 0 to 5 Figure C.7 (a) Port 7 Block Diagram (Pins P7 to P7 A/D converter Analog input Input enable Channel select signal...
Page 916: Port 8 Block Diagrams
Appendix C I/O Port Block Diagrams Port 8 Block Diagrams Hardware standby SSOE Reset Software standby External bus released P8 DDR WP8D Reset Bus controller Self-refresh P8 DR output enable Mode 6/7 RFSH output enable RFSH output Interrupt controller WP8D: Write to P8DDR WP8: Write to port 8...
Page 917 Appendix C I/O Port Block Diagrams SSOE Software standby External bus release Reset Hardware standby P8 DDR WP8D Mode Reset Mode 1 to 5 P8 DR Bus controller output output output enable Area 3 DRAM connection enable Interrupt controller input WP8D: Write to P8DDR WP8:...
Page 918 Appendix C I/O Port Block Diagrams SSOE Software standby External bus release Reset Hardware standby P8 DDR WP8D Reset Mode 6/7 Mode 1 to 5 P8 DR Bus controller output output output enable Interrupt controller input WP8D: Write to P8DDR WP8: Write to port 8 RP8:...
Page 919 Appendix C I/O Port Block Diagrams Mode Software standby SSOE External bus release Reset Hardware standby Bus controller WP8D output Reset Mode 6/7 Mode 1 to 5 Interrupt controller input A/D converter ADTRG input WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 SSOE:...
Page 920 Appendix C I/O Port Block Diagrams Reset Mode 1 to 4 Mode Software standby SSOE External bus release Bus controller P8 DDR Hardware standby WP8D output Reset Mode 6/7 P8 DR Mode 1 to 5 WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8...
Page 921: Port 9 Block Diagrams
Appendix C I/O Port Block Diagrams Port 9 Block Diagrams Reset Hardware standby P9 DDR WP9D Reset P9 DR Output enable Serial transmit data Guard time WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.9 (a) Port 9 Block Diagram (Pin P9 Rev.
Page 922 Appendix C I/O Port Block Diagrams Reset Hardware standby P9 DDR WP9D Reset P9 DR Output enable Serial transmit data Guard time WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.9 (b) Port 9 Block Diagram (Pin P9 Rev.
Page 923 Appendix C I/O Port Block Diagrams Reset Hardware standby P9 DDR WP9D Input enable Reset P9 DR Serial receive data WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.9 (c) Port 9 Block Diagram (Pin P9 Rev.
Page 924 Appendix C I/O Port Block Diagrams Reset Hardware standby WP9D Input enable Reset Serial receive data WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.9 (d) Port 9 Block Diagram (Pin P9 Rev. 4.00 Jan 26, 2006 page 900 of 938 REJ09B0276-0400...
Page 925 Appendix C I/O Port Block Diagrams Reset Hardware standby P9 DDR WP9D Clock input Reset enable P9 DR Clock output enable Clock output Clock input WP9D: Write to P9DDR Interrupt WP9: Write to port 9 controller RP9: Read port 9 input Figure C.9 (e) Port 9 Block Diagram (Pin P9 Rev.
Page 926 Appendix C I/O Port Block Diagrams Reset Hardware standby WP9D Clock input enable Reset Clock output enable Clock output Clock input Interrupt controller input WP9D : Write to P9DDR : Write to port 9 : Read port 9 Figure C.9 (f) Port 9 Block Diagram (Pin P9 Rev.
Page 927 Appendix C I/O Port Block Diagrams C.10 Port A Block Diagrams Reset Hardware standby PA DDR WPAD Reset output enable PA DR Next data Output trigger DMA controller Output enable Transfer end output 16-bit timer Counter clock input WPAD: Write to PADDR WPA: Write to port A RPA:...
Page 928 Appendix C I/O Port Block Diagrams Reset Hardware standby PA DDR WPAD Reset output enable PA DR Next data Output trigger 16-bit timer Output enable Compare match output Input capture Counter clock WPAD: Write to PADDR input WPA: Write to port A RPA: Read port A 8-bit timer...
Page 929 Appendix C I/O Port Block Diagrams Software standby SSOE Bus released Address output enable Mode 3/4 Reset Hardware standby WPAD Reset TPC output enable Next data Output trigger 16-bit timer Output enable Compare match output Input capture WPAD: Write to PADDR WPA: Write to port A RPA:...
Page 930 Appendix C I/O Port Block Diagrams C.11 Port B Block Diagrams Software standby Reset SSOE Hardware standby PB DDR Bus controller WPBD output Bus released CS output enable Reset Mode TPC output 1 to 5 enable PB DR Next data Output trigger 8-bit timer Output enable...
Page 931 Appendix C I/O Port Block Diagrams Software standby Reset SSOE Hardware standby Bus controller CS6 output WPBD Bus released CS output enable Reset Mode 1 to 5 TPC output enable Next data Output trigger 8-bit timer Output enable Compare match output TMO2 TMO3 input DMAC...
Page 932 Appendix C I/O Port Block Diagrams SSOE Software standby External bus release Reset Hardware standby WPBD Bus controller output enable Area 5 DRAM connection output enable output output Mode Reset output enable TPC output enable Next data Output trigger 8-bit timer Output enable Compare match output WPBD:...
Page 933 Appendix C I/O Port Block Diagrams SSOE Software standby External bus release Reset Hardware standby WPBD Bus controller output enable Area 5 DRAM connection output enable output output Mode Reset output enable TPC output enable Next data Output trigger 8-bit timer Output enable Compare match output TMIO...
Page 934 Appendix C I/O Port Block Diagrams Hardware standby External bus release SSOE Software standby Reset PB DDR WPBD Reset TPC output enable PB DR Next data Output trigger Bus controller Output enable CAS output Note: In modes 6 and 7, CAS output enable is fixed at 0. WPBD: Write to PBDDR WPB:...
Page 935 Appendix C I/O Port Block Diagrams External bus release Software standby SSOE Hardware Reset standby Clock input WPBD enable Reset TPC output enable Next data Output trigger Bus controller CAS output enable CAS output Clock output enable Clock output Clock input Note: In modes 6 and 7, CAS output enable is fixed at 0.
Page 936 Appendix C I/O Port Block Diagrams Reset Hardware standby PB DDR WPBD Reset output enable PB DR Next data Output trigger Output enable Serial transmit data Guard time WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C.11 (g) Port B Block Diagram (Pin PB Rev.
Page 937 Appendix C I/O Port Block Diagrams Reset Hardware standby PB DDR WPBD Input enable Reset output enable PB DR Next data Output trigger Serial receive WPBD: Write to PBDDR data WPB: Write to port B RPB: Read port B Figure C.11 (h) Port B Block Diagram (Pin PB Rev.
Page 938 Appendix D Pin States Appendix D Pin States Port States in Each Mode Table D.1 Port States Hardware Standby Software Standby Bus-Released Program Execution Name Mode Reset Mode Mode Mode Mode RESO * 1 to 4 L (SSOE=0) to A (SSOE=1) Keep (DDR = 0)
Page 939 Appendix D Pin States Hardware Standby Software Standby Bus-Released Program Execution Name Mode Reset Mode Mode Mode Mode 1 to 4 L (SSOE=0) to A (SSOE=1) Keep (DDR=0) (DDR=0) Keep Input port (DDR=1, SSOE=0) (DDR=1) to A (DDR=1, SSOE=1) Keep 6, 7 Keep —...
Page 940 Appendix D Pin States Hardware Standby Software Standby Bus-Released Program Execution Name Mode Reset Mode Mode Mode Mode 1 to 5 T When DRAM space When DRAM space (RFSHE=0) is not selected * is selected * I/O port (RFSHE=0) (RFSHE=0) (RFSHE=1) RFSH Keep...
Page 941 Appendix D Pin States Hardware Standby Software Standby Bus-Released Program Execution Name Mode Reset Mode Mode Mode Mode output * output * 1 to 5 T output (SSOE=0) Otherwise * Otherwise (SSOE=1) (DDR=0) (DDR=0) Keep I/O port Otherwise * (DDR=1) (DDR=1) (DDR=0) (DDR=1, SSOE=0)
Page 942 Appendix D Pin States Hardware Standby Software Standby Bus-Released Program Execution Name Mode Reset Mode Mode Mode Mode Address output * Address output * 3 to 5 T Address output (SSOE=0) to A Otherwise * Otherwise (SSOE=1) Keep I/O port Keep Otherwise * Keep...
Page 943 Appendix D Pin States Hardware Standby Software Standby Bus-Released Program Execution Name Mode Reset Mode Mode Mode Mode RAS4 output * RAS4 output * 1 to 5 T RAS4 output RAS4 (SSOE=0) CS output * CS output (SSOE=1) Otherwise * Otherwise CS output * Keep...
Page 944 Appendix D Pin States 7. When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is set to 1. 8. When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is cleared to 0. 9. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) is 101.
Page 945 Appendix D Pin States Pin States at Reset Modes 1 and 2: Figure D.1 is a timing diagram for the case in which RES goes low during an external memory access in mode 1 or 2. As soon as RES goes low, all ports are initialized to the input state.
Page 946 Appendix D Pin States Modes 3 and 4: Figure D.2 is a timing diagram for the case in which RES goes low during an external memory access in mode 3 or 4. As soon as RES goes low, all ports are initialized to the input state.
Page 947 Appendix D Pin States Mode 5: Figure D.3 is a timing diagram for the case in which RES goes low during an external memory access in mode 5. As soon as RES goes low, all ports are initialized to the input state. AS, RD, HWR, and LWR go high, and the address bus and D to D go to the high-impedance state.
Page 948 Appendix D Pin States Modes 6 and 7: Figure D.4 is a timing diagram for the case in which RES goes low during an operation in mode 6 or 7. As soon as RES goes low, all ports are initialized to the input state. /φ...
Page 949 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode 1. To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown below.
Page 950 Appendix F Product Code Lineup Appendix F Product Code Lineup Product Type Product Code Mark Code Package (Package Code) H8/3067 On-chip 5 VR HD64F3067RF HD64F3067RF 100-pin QFP flash (PRQP0100KA-A) memory HD64F3067RTE HD64F3067RTE 100-pin TQFP (PTQP0100KA-A) HD64F3067RFP HD64F3067RFP 100-pin QFP (PRQP0100JE-B) 3 VR HD64F3067RVF HD64F3067RVF 100-pin QFP...
Page 951 Appendix F Product Code Lineup Product Type Product Code Mark Code Package (Package Code) H8/3066 On-chip HD6433066F HD6433066(***)F 100-pin QFP mask (PRQP0100KA-A) HD6433066TE HD6433066(***)TE 100-pin TQFP (PTQP0100KA-A) HD6433066FP HD6433066(***)FP 100-pin QFP (PRQP0100JE-B) HD6433066VF HD6433066(***)VF 100-pin QFP (PRQP0100KA-A) HD6433066VTE HD6433066(***)VTE 100-pin TQFP (PTQP0100KA-A) HD6433066VFP HD6433066(***)VFP 100-pin QFP...
Page 952 Appendix G Package Dimensions Figures G.1 show the PRQP0100KA-A package dimensions of the H8/3067 Group. Figure G.2 shows the PTQP0100KA-A package dimensions. Figure G.3 shows the PRQP0100JE-B package dimensions. JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-QFP100-14x14-0.50 PRQP0100KA-A FP-100B/FP-100BV 1.2g...
Page 953 Appendix G Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-TQFP100-14x14-0.50 PTQP0100KA-A TFP-100B/TFP-100BV 0.5g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. Dimension in Millimeters Terminal cross section Reference Symbol 1.00 15.8 16.0...
Page 954 Appendix G Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-QFP100-14x20-0.65 PRQP0100JE-B FP-100A/FP-100AV 1.7g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. Terminal cross section Dimension in Millimeters Reference Symbol Nom Max 2.70...
Page 955 Appendix H Comparison of H8/300H Series Product Specifications Appendix H Comparison of H8/300H Series Product Specifications Differences between H8/3067 and H8/3062 Group, H8/3048 Group, H8/3007 and H8/3006, and H8/3002 H8/3067, H8/3062 H8/3048 Item Group Group H8/3006, 3007 H8/3002 Operating Mode 5 16 MB ROM enabled 1 MB ROM mode...
Page 956 Appendix H Comparison of H8/300H Series Product Specifications H8/3067, H8/3062 H8/3048 Item Group Group H8/3006, 3007 H8/3002 Timer functions 16-bit 8-bit 16-bit 8-bit timers timers timers timers 16 bits × 3 8 bits × 4 16 bits × 5 16 bits × 3 8 bits ×...
Page 957 Appendix H Comparison of H8/300H Series Product Specifications H8/3067, H8/3062 H8/3048 Item Group Group H8/3006, 3007 H8/3002 Conversion start External trigger/8-bit External External trigger/8-bit External converter trigger input timer compare match trigger timer compare match trigger φ pin φ/input port multiplexing φ output φ/input port multiplexing φ...
Page 958 Appendix H Comparison of H8/300H Series Product Specifications Comparison of Pin Functions of 100-Pin Package Products (PRQP0100KA-A, PTQP0100KA-A) Table H.1 Pin Arrangement of Each Product (PRQP0100KA-A, PTQP0100KA-A) On-chip-ROM Products ROMless Products H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group H8/3006, 3007 H8/3002 /TMO /TMO...
Page 959 Appendix H Comparison of H8/300H Series Product Specifications On-chip-ROM Products ROMless Products H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group H8/3006, 3007 H8/3002 Rev. 4.00 Jan 26, 2006 page 935 of 938 REJ09B0276-0400...
Page 960 Appendix H Comparison of H8/300H Series Product Specifications On-chip-ROM Products ROMless Products H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group H8/3006, 3007 H8/3002 /WAIT /WAIT /WAIT /WAIT /WAIT /WAIT /BREQ /BREQ /BREQ /BREQ /BREQ /BREQ /BACK /BACK /BACK /BACK /BACK /BACK φ...
Page 961 Appendix H Comparison of H8/300H Series Product Specifications On-chip-ROM Products ROMless Products H8/3067 Group H8/3062 Group H8/3048 Group H8/3042 Group H8/3006, 3007 H8/3002 /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ /IRQ ADTRG ADTRG ADTRG /TCLKA PA TEND TEND TEND...
Page 962 Appendix H Comparison of H8/300H Series Product Specifications Rev. 4.00 Jan 26, 2006 page 938 of 938 REJ09B0276-0400...
Page 963 Publication Date: 1st Edition, March 1998 Rev.4.00, January 26, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 964 Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Page 965 H8/3067 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0276-0400...

This manual is also suitable for:

H8/3067H8/3066 H8/3065 H8/3067rf

Renesas H8/3067 Series User Manual

Quick Links

Related Manuals for Renesas H8/3067 Series

Summary of Contents for Renesas H8/3067 Series