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20.2.2
Module Standby Control Register H (MSTCRH)
MSTCRH is an 8-bit readable/writable register that controls output of the system clock (φ). It also
controls the module standby function, which places individual on-chip supporting modules in the
standby state. Module standby can be designated for the SCI0, SCI1, SCI2.
Bit
7
PSTOP
Initial value
0
Read/Write
R/W
φ clock stop
Enables or disables
output of the system clock
MSTCRH is initialized to H'78 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ φ φ φ Clock Stop (PSTOP): Enables or disables output of the system clock (φ).
Bit 1
PSTOP
Description
0
System clock output is enabled
1
System clock output is disabled
Bits 6 to 3—Reserved: These bits cannot be modified and are always read as 1.
Bit 2—Module Standby H2 (MSTPH2): Selects whether to place the SCI2 in standby.
Bit 2
MSTPH2
Description
0
SCI2 operates normally
1
SCI2 is in standby state
6
5
4
1
1
1
Reserved bit
Section 20 Power-Down State
3
2
MSTPH2
MSTPH1
1
0
R/W
Module standby H2 to 0
These bits select modules
to be placed in standby
Rev. 4.00 Jan 26, 2006 page 679 of 938
1
0
MSTPH0
0
0
R/W
R/W
(Initial value)
(Initial value)
REJ09B0276-0400
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