Renesas H8 Series Hardware Manual
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Renesas H8 Series Hardware Manual

16-bit single-chip microcomputer
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  • Page 1 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
  • Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
  • Page 3 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8/36912 Group, H8/36902 Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series H8/36912F HD64F36912G H8/36902F HD64F36902G H8/36912...
  • Page 4 Rev. 3.00 Sep. 14, 2006 Page ii of xxviii...
  • Page 5 (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp.
  • Page 6 General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
  • Page 7 Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
  • Page 8 The H8/36912 Group and H8/36902 Group are single-chip microcomputers made up of the high- speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU.
  • Page 9 5. When the E7 or E8 is used, NMI is an input/output pin (open-drain in output mode). Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ H8/36912 Group and H8/36902 Group manuals: Document Title Document No.
  • Page 10 Rev. 3.00 Sep. 14, 2006 Page viii of xxviii...

  • Page 11: Table Of Contents

    Contents Section 1 Overview....................1 Features..........................1 Internal Block Diagram......................3 Pin Arrangement ........................5 Pin Functions ........................9 Section 2 CPU......................11 Address Space and Memory Map ..................12 Register Configuration......................14 2.2.1 General Registers....................15 2.2.2 Program Counter (PC) ..................16 2.2.3 Condition-Code Register (CCR).................
  • Page 12 3.2.4 Interrupt Enable Register 2 (IENR2) ..............51 3.2.5 Interrupt Flag Register 1 (IRR1)................. 52 3.2.6 Interrupt Flag Register 2 (IRR2)................. 53 3.2.7 Wakeup Interrupt Flag Register (IWPR) ............53 Reset Exception Handling ....................54 Interrupt Exception Handling ..................... 55 3.4.1 External Interrupts ....................
  • Page 13 Usage Notes ........................84 5.7.1 Note on Resonators..................... 84 5.7.2 Notes on Board Design ..................84 Section 6 Power-Down Modes ................85 Register Descriptions......................85 6.1.1 System Control Register 1 (SYSCR1) ..............86 6.1.2 System Control Register 2 (SYSCR2) ..............88 6.1.3 Module Standby Control Register 1 (MSTCR1) ..........
  • Page 14 Section 9 I/O Ports..................... 117 Port 1..........................117 9.1.1 Port Mode Register 1 (PMR1) ................118 9.1.2 Port Control Register 1 (PCR1) ................ 119 9.1.3 Port Data Register 1 (PDR1) ................119 9.1.4 Port Pull-Up Control Register 1 (PUCR1)............120 9.1.5 Pin Functions ....................
  • Page 15 10.3 Operation .......................... 142 10.3.1 Interval Timer Operation .................. 142 10.3.2 Auto-Reload Timer Operation ................142 10.4 Timer B1 Operating Modes ....................143 Section 11 Timer V....................145 11.1 Features..........................145 11.2 Input/Output Pins......................147 11.3 Register Descriptions......................147 11.3.1 Timer Counter V (TCNTV) ................147 11.3.2 Time Constant Registers A and B (TCORA, TCORB) ........
  • Page 16 12.5.4 Timing of Counter Clearing by Compare Match ..........183 12.5.5 Buffer Operation Timing .................. 184 12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match ......185 12.5.7 Timing of IMFA to IMFD Setting at Input Capture ......... 186 12.5.8 Timing of Status Flag Clearing.................
  • Page 17 14.6.1 Multiprocessor Serial Data Transmission ............229 14.6.2 Multiprocessor Serial Data Reception .............. 231 14.7 Interrupts........................... 235 14.8 Usage Notes ........................236 14.8.1 Break Detection and Processing ............... 236 14.8.2 Mark State and Break Sending................236 14.8.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)..............
  • Page 18 Section 16 A/D Converter ................. 273 16.1 Features..........................273 16.2 Input/Output Pins......................275 16.3 Register Description ......................275 16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .......... 275 16.3.2 A/D Control/Status Register (ADCSR) ............276 16.3.3 A/D Control Register (ADCR) ................. 278 16.4 Operation ..........................
  • Page 19 20.2.1 Power Supply Voltage and Operating Ranges ..........314 20.2.2 DC Characteristics .................... 316 20.2.3 AC Characteristics .................... 321 20.2.4 A/D Converter Characteristics ................325 20.2.5 Watchdog Timer Characteristics............... 326 20.2.6 Power-Supply-Voltage Detection Circuit Characteristics......... 327 20.2.7 LVDI External Voltage Detection Circuit Characteristics........ 327 20.2.8 Power-On Reset Characteristics................
  • Page 20 Rev. 3.00 Sep. 14, 2006 Page xviii of xxviii...
  • Page 21 Figures Section 1 Overview Figure 1.1 Internal Block Diagram of H8/36912 Group..............3 Figure 1.2 Internal Block Diagram of H8/36902 Group..............4 Figure 1.3 Pin Arrangement of H8/36912 Group (FP-32A) ............5 Figure 1.4 Pin Arrangement of H8/36902 Group (FP-32A) ............6 Figure 1.5 Pin Arrangement of H8/36912 Group (FP-32D, 32P4B) ..........
  • Page 22 Section 5 Clock Pulse Generators Figure 5.1 Block Diagram of Clock Pulse Generators..............69 Figure 5.2 State Transition of System Clock ................75 Figure 5.3 Flowchart of Clock Switching On-chip Oscillator Clock to External Clock (1) ..76 Figure 5.4 Flowchart of Clock Switching External Clock to On-chip Oscillator Clock (2) ..77 Figure 5.5 Timing Chart of Switching On-chip Oscillator Clock to External Clock....
  • Page 23 Figure 11.6 TMOV Output Timing .................... 154 Figure 11.7 Clear Timing by Compare Match................154 Figure 11.8 Clear Timing by TMRIV Input ................155 Figure 11.9 Pulse Output Example ..................... 155 Figure 11.10 Example of Pulse Output Synchronized to TRGV Input........156 Figure 11.11 Contention between TCNTV Write and Clear ............
  • Page 24 Section 13 Watchdog Timer Figure 13.1 Block Diagram of Watchdog Timer ................ 191 Figure 13.2 Watchdog Timer Operation Example..............195 Section 14 Serial Communication Interface 3 (SCI3) Figure 14.1 Block Diagram of SCI3................... 198 Figure 14.2 Block Diagram of Noise Filter Circuit ..............211 Figure 14.3 Data Format in Asynchronous Communication ............
  • Page 25 Figure 15.8 Master Receive Mode Operation Timing (2)............259 Figure 15.9 Slave Transmit Mode Operation Timing (1) ............260 Figure 15.10 Slave Transmit Mode Operation Timing (2) ............261 Figure 15.11 Slave Receive Mode Operation Timing (1)............262 Figure 15.12 Slave Receive Mode Operation Timing (2)............262 Figure 15.13 Clocked Synchronous Serial Transfer Format............
  • Page 26 Figure 20.5 SCK3 Input Clock Timing ..................347 Figure 20.6 SCI3 Input/Output Timing in Clocked Synchronous Mode ........348 Figure 20.7 Output Load Circuit ....................348 Appendix Figure B.1 Port 1 Block Diagram (P17) ..................379 Figure B.2 Port 1 Block Diagram (P14) ..................380 Figure B.3 Port 2 Block Diagram (P22) ..................
  • Page 27 Tables Section 1 Overview Table 1.1 Pin Functions ......................9 Section 2 CPU Table 2.1 Operation Notation ....................21 Table 2.2 Data Transfer Instructions..................22 Table 2.3 Arithmetic Operations Instructions (1) ..............23 Table 2.3 Arithmetic Operations Instructions (2) ..............24 Table 2.4 Logic Operations Instructions.................
  • Page 28 Table 7.4 Reprogram Data Computation Table ..............109 Table 7.5 Additional-Program Data Computation Table ............109 Table 7.6 Programming Time ....................109 Section 10 Timer B1 Table 10.1 Timer B1 Operating Modes .................. 143 Section 11 Timer V Table 11.1 Pin Configuration....................
  • Page 29 Table 20.5 Serial Interface (SCI3) Timing ................324 Table 20.6 A/D Converter Characteristics ................325 Table 20.7 Watchdog Timer Characteristics................326 Table 20.8 Power-Supply-Voltage Detection Circuit Characteristics........327 Table 20.9 LVDI External Voltage Detection Circuit Characteristics........327 Table 20.10 Power-On Reset Circuit Characteristics............328 Table 20.11 Flash Memory Characteristics ................
  • Page 30 Rev. 3.00 Sep. 14, 2006 Page xxviii of xxviii...

  • Page 31: Section 1 Overview

    4 kbytes 256 bytes H8/36902 HD64336902G 8 kbytes 512 bytes H8/36901 HD64336901G 4 kbytes 256 bytes H8/36900 HD64336900G 2 kbytes 256 bytes Note: F-ZTAT is a trademark of Renesas Technology Corp. Rev. 3.00 Sep. 14, 2006 Page 1 of 408 REJ09B0105-0300...

  • Page 32: Section 1 Overview

    Section 1 Overview • General I/O ports  Eighteen I/O pins, including five large-current ports (I = 20 mA, @V = 1.5 V, −I = Vcc − 1.0 V) = 4 mA, @V  Four input only pins (also used for analog input) •...

  • Page 33: Internal Block Diagram

    Section 1 Overview Internal Block Diagram E10T_0* E10T_1* E10T_2* System On-chip clock oscillator H8/300H generator Data bus (lower) P17/IRQ3/TRGV P14/IRQ0 P76/TMOV P75/TMCIV P74/TMRIV SCI3 Timer W P84/FTIOD P83/FTIOC P22/TXD Timer V IIC2 P82/FTIOB P21/RXD P81/FTIOA P20/SCK3 P80/FTCI Watchdog Timer B1 timer P57/SCL P56/SDA...

  • Page 34: Figure 1.2 Internal Block Diagram Of H8/36902 Group

    Section 1 Overview E10T_0* E10T_1* E10T_2* System On-chip clock oscillator H8/300H generator Data bus (lower) P17/IRQ3/TRGV P14/IRQ0 P76/TMOV P75/TMCIV P74/TMRIV P22/TXD P21/RXD SCI3 Timer W P20/SCK3 P84/FTIOD P83/FTIOC Watchdog Timer V P82/FTIOB timer P81/FTIOA P80/FTCI POR & LVD converter P55/WKP5/ADTRG Port C Port B Note: * Can also be used for the E7 or E8 emulator.

  • Page 35: Pin Arrangement

    Section 1 Overview Pin Arrangement P84/FTIOD P14/IRQ0 P74/TMRIV P56/SDA P75/TMCIV P57/SCL P76/TMOV E10T_2* H8/36912 Group (Top view) PB3/AN3/ExtU E10T_1* PB2/AN2/ExtD E10T_0* PB1/AN1 P17/IRQ3/TRGV PB0/AN0 Note: * Can also be used for the E7 or E8 emulator. Figure 1.3 Pin Arrangement of H8/36912 Group (FP-32A) Rev.

  • Page 36: Figure 1.4 Pin Arrangement Of H8/36902 Group (Fp-32A)

    Section 1 Overview P84/FTIOD P14/IRQ0 P74/TMRIV P75/TMCIV P76/TMOV E10T_2* H8/36902 Group (Top view) PB3/AN3/ExtU E10T_1* PB2/AN2/ExtD E10T_0* PB1/AN1 P17/IRQ3/TRGV PB0/AN0 Note: * Can also be used for the E7 or E8 emulator. Figure 1.4 Pin Arrangement of H8/36902 Group (FP-32A) Rev.

  • Page 37: Figure 1.5 Pin Arrangement Of H8/36912 Group (Fp-32D, 32P4B)

    Section 1 Overview PB3/AN3/ExtU P76/TMOV PB2/AN2/ExtD P75/TMCIV PB1/AN1 P74/TMRIV PB0/AN0 P84/FTIOD AVcc P83/FTIOC P82/FTIOB P81/FTIOA TEST P80/FTCI H8/36912 Group (Top view) P22/TXD PC1/OSC2/CLKOUT P21/RXD PC0/OSC1 P20/SCK3 P55/WKP5/ADTRG P14/IRQ0 P17/IRQ3/TRGV P56/SDA P57/SCL E10T_0* E10T_1* E10T_2* Note: * Can also be used for the E7 or E8 emulator. Figure 1.5 Pin Arrangement of H8/36912 Group (FP-32D, 32P4B) Rev.

  • Page 38: Figure 1.6 Pin Arrangement Of H8/36902 Group (Fp-32D, 32P4B)

    Section 1 Overview PB3/AN3/ExtU P76/TMOV PB2/AN2/ExtD P75/TMCIV PB1/AN1 P74/TMRIV PB0/AN0 P84/FTIOD AVcc P83/FTIOC P82/FTIOB P81/FTIOA TEST P80/FTCI H8/36902 Group (Top view) P22/TXD PC1/OSC2/CLKOUT P21/RXD PC0/OSC1 P20/SCK3 P55/WKP5/ADTRG P14/IRQ0 P17/IRQ3/TRGV E10T_0* E10T_1* E10T_2* Note: * Can also be used for the E7 or E8 emulator. Figure 1.6 Pin Arrangement of H8/36902 Group (FP-32D, 32P4B) Rev.

  • Page 39: Pin Functions

    Section 1 Overview Pin Functions Table 1.1 Pin Functions Pin No. FP-32D, Type Symbol 32P4B FP-32A Functions Power Input Power supply pin. Connect this pin source to the system power supply. Input Ground pin. Connect this pin to the system power supply (0 V). Input Analog power supply pin for the A/D converter.
  • Page 40 Section 1 Overview Pin No. FP-32D, Type Symbol 32P4B FP-32A Functions Timer V TMOV Output TMOV is an output pin for waveforms generated by the output compare function. TMCIV Input External event input pin TMRIV Input Counter reset input pin TRGV Input Counter start trigger input pin...

  • Page 41: Section 2 Cpu

    Section 2 CPU Section 2 CPU This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU, and supports only normal mode, which has a 64-kbyte address space. • Upward-compatible with H8/300 CPUs ...

  • Page 42: Address Space And Memory Map

    Section 2 CPU Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. The following two figures show the memory map, respectively. H8/36912F H8/36912 H8/36902F H8/36902 (Flash memory version) (Masked ROM version) H'0000 H'0000...

  • Page 43: Figure 2.1 Memory Map (2)

    Section 2 CPU H8/36911 H8/36901 H8/36900 (Masked ROM version) (Masked ROM version) H'0000 H'0000 Interrupt vector Interrupt vector H'0045 H'0045 H'0046 H'0046 On-chip ROM (2 kbytes) On-chip ROM H'07FF (4 kbytes) H'0FFF Not used Not used H'F600 H'F600 Internal I/O register Internal I/O register H'F77F H'F77F...

  • Page 44: Register Configuration

    Section 2 CPU Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition code register (CCR). General registers (ERn) ER7 (SP) Control registers (CR)

  • Page 45: General Registers

    Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers.

  • Page 46: Program Counter (Pc)

    Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the stack. Free area SP (ER7) Stack area Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC)
  • Page 47 Section 2 CPU Initial Bit Name Value Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. Undefined R/W User Bit Can be written and read by software using the LDC, STC,...

  • Page 48: Data Formats

    Section 2 CPU Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.

  • Page 49: Figure 2.5 General Register Data Formats (2)

    Section 2 CPU Data Type General Data Format Register Word data Word data Longword data [Legend] ERn: General register ER General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.5 General Register Data Formats (2) Rev.

  • Page 50: Memory Data Formats

    Section 2 CPU 2.3.2 Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address.

  • Page 51: Instruction Set

    Section 2 CPU Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.1 Operation Notation Symbol...

  • Page 52: Table 2.2 Data Transfer Instructions

    Section 2 CPU Symbol Description :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length Note: General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers/address registers (ER0 to ER7). Table 2.2 Data Transfer Instructions Instruction Size*...

  • Page 53: Table 2.3 Arithmetic Operations Instructions (1)

    Section 2 CPU Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register.

  • Page 54: Table 2.3 Arithmetic Operations Instructions (2)

    Section 2 CPU Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function Rd ÷ Rs → Rd DIVXS Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.

  • Page 55: Table 2.4 Logic Operations Instructions

    Section 2 CPU Table 2.4 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.

  • Page 56: Table 2.6 Bit Manipulation Instructions (1)

    Section 2 CPU Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.

  • Page 57: Table 2.6 Bit Manipulation Instructions (2)

    Section 2 CPU Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ⊕...

  • Page 58: Table 2.7 Branch Instructions

    Section 2 CPU Table 2.7 Branch Instructions Instruction Size Function Bcc* — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never C ∨...

  • Page 59: Table 2.8 System Control Instructions

    Section 2 CPU Table 2.8 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. (EAs) → CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access.

  • Page 60: Basic Instruction Formats

    Section 2 CPU Table 2.9 Block Data Transfer Instructions Instruction Size Function if R4L ≠ 0 then EEPMOV.B — Repeat @ER5+ → @ER6+, R4L–1 → R4L Until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W — Repeat @ER5+ → @ER6+, R4–1 →...

  • Page 61: Figure 2.7 Instruction Formats

    Section 2 CPU Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00). Condition Field Specifies the branching condition of Bcc instructions.

  • Page 62: Addressing Modes And Effective Address Calculation

    Section 2 CPU Addressing Modes and Effective Address Calculation The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes.
  • Page 63 Section 2 CPU Register Indirect—@ERn The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory. Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn) A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand.

  • Page 64: Table 2.11 Absolute Address Access Ranges

    Section 2 CPU Table 2.11 Absolute Address Access Ranges Absolute Address Access Range 8 bits (@aa:8) H'FF00 to H'FFFF 16 bits (@aa:16) H'0000 to H'FFFF 24 bits (@aa:24) H'0000 to H'FFFF Immediate—#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand.

  • Page 65: Effective Address Calculation

    Section 2 CPU Specified Dummy by @aa:8 Branch address Figure 2.8 Branch Address Specification in Memory Indirect Mode 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI, the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. Table 2.12 Effective Address Calculation (1) Addressing Mode and Instruction Format Effective Address Calculation...

  • Page 66: Table 2.12 Effective Address Calculation (2)

    Section 2 CPU Table 2.12 Effective Address Calculation (2) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address Sign extension Immediate Operand is immediate data. PC contents Sign extension Memory contents [Legend] r, rm,rn : Register field op : Operation field disp :...

  • Page 67: Basic Bus Cycle

    Section 2 CPU Basic Bus Cycle CPU operation is synchronized by a system clock (φ). The period from a rising edge of φ to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules.

  • Page 68: On-Chip Peripheral Modules

    Section 2 CPU 2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing states of each register, refer to section 19.1, Register Addresses (Address Order).

  • Page 69: Cpu States

    Section 2 CPU CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode. In the program halt state there are a sleep mode, and standby mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions.

  • Page 70: Usage Notes

    Section 2 CPU Reset cleared Reset state Exception-handling state Reset occurs Reset Interrupt occurs source Reset Interrupt Exception- occurs source handling complete Program halt state Program execution state SLEEP instruction executed Figure 2.12 State Transitions Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user.

  • Page 71: Figure 2.13 Example Of Timer Configuration With Two Registers Allocated To Same

    Section 2 CPU Bit Manipulation for Two Registers Assigned to the Same Address Example 1: Bit manipulation for the timer load register and timer counter (Applicable to timer B1, not available for the H8/36902 Group.) Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address.
  • Page 72 Section 2 CPU Example 2: The BSET instruction is executed for port 5. P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level signal at P50 with a BSET instruction is shown below.
  • Page 73 Section 2 CPU As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy of the PDR5 data in a work area in memory.
  • Page 74 Section 2 CPU Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56.
  • Page 75 Section 2 CPU As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However, bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins. To prevent this problem, store a copy of the PCR5 data in a work area in memory and manipulate data of the bit in the work area, then write this data to PCR5.
  • Page 76 Section 2 CPU Rev. 3.00 Sep. 14, 2006 Page 46 of 408 REJ09B0105-0300...

  • Page 77: Section 3 Exception Handling

    Section 3 Exception Handling Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. • Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin.
  • Page 78 Section 3 Exception Handling Vector Relative Module Exception Sources Number Vector Address Priority Address break Break conditions satisfied H'0018 to H'0019 High Direct transition by executing H'001A to H'001B the SLEEP instruction External interrupt IRQ0, low-voltage detection H'001C to H'001D interrupt ...

  • Page 79: Register Descriptions

    Section 3 Exception Handling Register Descriptions Interrupts are controlled by the following registers. • Interrupt edge select register 1 (IEGR1) • Interrupt edge select register 2 (IEGR2) • Interrupt enable register 1 (IENR1) • Interrupt enable register 2 (IENR2) • Interrupt flag register 1 (IRR1) •...

  • Page 80: Interrupt Edge Select Register 2 (Iegr2)

    Section 3 Exception Handling 3.2.2 Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the ADTRG and WKP5 pins. Initial Bit Name Value Description   7, 6 All 1 Reserved These bits are always read as 1.

  • Page 81: Interrupt Enable Register 2 (Ienr2)

    Section 3 Exception Handling Initial Bit Name Value Description IEN0 IRQ0 Interrupt Enable When this bit is set to 1, interrupt requests of the IRQ0 pin are enabled. 3.2.4 Interrupt Enable Register 2 (IENR2) IENR2 enables timer B1 interrupts. Initial Bit Name Value Description...

  • Page 82: Interrupt Flag Register 1 (Irr1)

    Section 3 Exception Handling 3.2.5 Interrupt Flag Register 1 (IRR1) IRR1 is a status flag register for direct transition interrupts, and IRQ3 and IRQ0 interrupt requests. Initial Bit Name Value Description IRRDT Direct Transfer Interrupt Request Flag [Setting condition] • When a direct transfer is made by executing a SLEEP instruction while DTON in SYSCR2 is set to 1.

  • Page 83: Interrupt Flag Register 2 (Irr2)

    Section 3 Exception Handling 3.2.6 Interrupt Flag Register 2 (IRR2) IRR2 is a status flag register for timer B1 interrupt requests. Initial Bit Name Value Description   Reserved This bit is always read as 0.    Reserved IRRTB1 Timer B1 Interrupt Request Flag [Setting condition]...

  • Page 84: Reset Exception Handling

    Section 3 Exception Handling Reset Exception Handling When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure that this LSI is reset at power-up, hold the RES pin low for the specified period.

  • Page 85: Interrupt Exception Handling

    Section 3 Exception Handling Interrupt Exception Handling 3.4.1 External Interrupts As external interrupts, there are NMI, IRQ3, IRQ0, and WKP5 interrupts. NMI Interrupt NMI interrupt is requested by input falling edge to the NMI pin. NMI is the highest interrupt, and can always be accepted without depending on the I bit value in CCR.

  • Page 86: Internal Interrupts

    Section 3 Exception Handling Reset cleared Initial program instruction prefetch Vector fetch Internal processing φ Internal address bus Internal read signal Internal write signal Internal data bus (16 bits) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) Initial program instruction Figure 3.1 Reset Sequence 3.4.2...

  • Page 87: Interrupt Handling Sequence

    Section 3 Exception Handling 3.4.3 Interrupt Handling Sequence Interrupts are controlled by an interrupt controller. Interrupt operation is described as follows. 1. If an interrupt occurs while the NMI or interrupt enable bit is set to 1, an interrupt request signal is sent to the interrupt controller.

  • Page 88: Figure 3.2 Stack Status After Exception Handling

    Section 3 Exception Handling Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and the stack area is in the on-chip RAM. Reset cleared Initial program instruction prefetch Vector fetch Internal processing φ Internal address bus Internal read...

  • Page 89: Interrupt Response Time

    Section 3 Exception Handling 3.4.4 Interrupt Response Time Table 3.2 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. Table 3.2 Interrupt Wait States Item States Total Waiting time for completion of executing instruction* 1 to 23...

  • Page 90: Figure 3.3 Interrupt Sequence

    Section 3 Exception Handling Figure 3.3 Interrupt Sequence Rev. 3.00 Sep. 14, 2006 Page 60 of 408 REJ09B0105-0300...

  • Page 91: Usage Notes

    Section 3 Exception Handling Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset.
  • Page 92 Section 3 Exception Handling Rev. 3.00 Sep. 14, 2006 Page 62 of 408 REJ09B0105-0300...

  • Page 93: Section 4 Address Break

    Section 4 Address Break Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address.

  • Page 94: Register Descriptions

    Section 4 Address Break Register Descriptions Address break has the following registers. • Address break control register (ABRKCR) • Address break status register (ABRKSR) • Break address register (BARH, BARL) • Break data register (BDRH, BDRL) 4.1.1 Address Break Control Register (ABRKCR) ABRKCR sets address break conditions.
  • Page 95 Section 4 Address Break Initial Bit Name Value Description DCMP1 Data Compare Condition Select 1 and 0 DCMP0 These bits set the comparison condition between the data set in BDR and the internal data bus. 00: No data comparison 01: Compares lower 8-bit data between BDRL and data 10: Compares upper 8-bit data between BDRH and data 11: Compares 16-bit data between BDR and data bus [Legend]...

  • Page 96: Address Break Status Register (Abrksr)

    Section 4 Address Break 4.1.2 Address Break Status Register (ABRKSR) ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit. Initial Bit Name Value Description ABIF Address Break Interrupt Flag [Setting condition] • When the condition set in ABRKCR is satisfied [Clearing condition] •...

  • Page 97: Operation

    Section 4 Address Break Operation When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR.

  • Page 98: Figure 4.2 Address Break Interrupt Operation Example (2)

    Section 4 Address Break When the address break is specified in the data read cycle Register setting Program • ABRKCR = H'A0 0258 • BAR = H'025A 025A 025C MOV.W @H'025A,R0 0260 Underline indicates the address 0262 to be stacked. Next instruc- instruc-...

  • Page 99: Section 5 Clock Pulse Generators

    Section 5 Clock Pulse Generators Section 5 Clock Pulse Generators Clock oscillator circuitry (CPG: clock pulse generator) consists of an external oscillator, an on- chip oscillator, a duty correction circuit, a clock select circuit, and system clock dividers. Figure 5.1 shows a block diagram of the clock pulse generator. φ...

  • Page 100: Features

    Section 5 Clock Pulse Generators Features • Choice of two clock sources On-chip oscillator clock External oscillator clock • Choice of two types of on-chip oscillation frequency by the user software 8MHz 10MHz • Frequency trimming Users can adjust the on-chip oscillation frequency by rewriting the trimming registers. •...

  • Page 101: Register Descriptions

    Section 5 Clock Pulse Generators Register Descriptions Clock oscillators are controlled by the following registers. • RC control register (RCCR) • RC trimming data protect register (RCTRMDPR) • RC trimming data register (RCTRMDR) • Clock control/status register (CKCSR) 5.2.1 RC Control Register (RCCR) RCCR controls the on-chip oscillator.

  • Page 102: Rc Trimming Data Protect Register (Rctrmdpr)

    Section 5 Clock Pulse Generators 5.2.2 RC Trimming Data Protect Register (RCTRMDPR) RCTRMDPR controls RCTRMDPR itself and writing to RCTRMDR. Use the MOV instruction to rewrite this register. Bit manipulation instruction cannot change the settings. Initial Bit Name Value Description Write Inhibit Only when writing 0 to this bit, this register can be written to.

  • Page 103: Rc Trimming Data Register (Rctrmdr)

    Section 5 Clock Pulse Generators Initial Bit Name Value Description Trimming Date Register Write Enable TRMDRWE This register can be written to when the LOCKDW bit is 0 and this bit is 1. [Setting condition] • When writing 0 to the WRI bit while writing 1 to the TRMDRWE bit while the PRWE bit is 1 [Clearing conditions] •...

  • Page 104: Clock Control/Status Register (Ckcsr)

    Section 5 Clock Pulse Generators 5.2.4 Clock Control/Status Register (CKCSR) CKCSR selects the port C function, controls switching the system clocks, and indicates the system clock state. Initial Bit Name Value Description PMRC1 Port C Function Select 1 and 0 PMRC0 PMRC1 PMRC0 PC1 CLKOUT I/O...

  • Page 105: System Clock Select Operation

    Section 5 Clock Pulse Generators System Clock Select Operation Figure 5.2 shows the state transition of the system clock. LSI operates on on-chip oscillator clock Reset release On-chip oscillator: Operated Reset state External oscillator: Halted Switching to Switching to on-chip oscillator external clock On-chip oscillator halted On-chip oscillator: Halted...

  • Page 106: Clock Control Operation

    Section 5 Clock Pulse Generators 5.3.1 Clock Control Operation The LSI system clock is generated by the on-chip oscillator clock after a reset. The on-chip oscillator clock is switched to the external clock by the user software. LSI operates on on-chip oscillator RC clock [1] External oscillation starts when pins PC1 and PC0 are selected as external oscillation pins.

  • Page 107: Figure 5.4 Flowchart Of Clock Switching External Clock To On-Chip Oscillator Clock (2)

    Section 5 Clock Pulse Generators LSI operates on external clock [1] When 0 is written to the OSCSEL bit, this LSI Start switches the external clock to the on-chip oscillator (LSI operates on external clock) clock after the φ stop duration. Seven rising edges of the φ...

  • Page 108: Clock Change Timing

    Section 5 Clock Pulse Generators 5.3.2 Clock Change Timing The timing for changing clocks are shown in figures 5.5 and 5.6. φOSC φRC φ OSCSEL PHISTOP (Internal signal) CKSTA φ halt* On-chip oscillator clock operation External clock operation Wait for external oscillation settling Nwait [Legend]...

  • Page 109: Figure 5.6 Timing Chart To Switch External Clock To On-Chip Oscillator Clock

    Section 5 Clock Pulse Generators φOSC φRC φ OSCSEL PHISTOP (Internal signal) CKSTA CKSWIF On-chip oscillator φ halt* External clock operation clock operation Wait for external oscillation settling Nwait [Legend] φOSC: External clock φRC: On-chip oscillator clock φ: System clock OSCSEL: Bit 4 in CKCSR PHISTOP: System clock stop control signal CKSTA:...

  • Page 110: Trimming Of On-Chip Oscillator Frequency

    Section 5 Clock Pulse Generators Trimming of On-chip Oscillator Frequency Users can trim the on-chip oscillator frequency, supplying the external reference pulses with the input capture function in internal timer W. An example of trimming flow and a timing chart are shown in figures 5.7 and 5.8, respectively.

  • Page 111: Figure 5.8 Timing Chart Of Trimming Of On-Chip Oscillator Frequency

    Section 5 Clock Pulse Generators φRC FTIOA input capture input (µs) Timer W M + α M + 1 M - 1 TCNT M + α Capture 1 Capture 2 Figure 5.8 Timing Chart of Trimming of On-chip Oscillator Frequency The on-chip oscillator frequency is gained by the expression below.

  • Page 112: External Oscillators

    Section 5 Clock Pulse Generators External Oscillators This LSI has two methods to supply external clock pulses into it: connecting a crystal or ceramic resonator, and an external clock. Oscillation pins OSC1 and OSC2 are common with general ports PC0 and PC1, respectively. To set pins PC0 and PC1 as crystal resonator or external clock input ports, refer to section 5.3, System Clock Select Operation.

  • Page 113: Connecting Ceramic Resonator

    Section 5 Clock Pulse Generators 5.5.2 Connecting Ceramic Resonator Figure 5.11 shows an example of connecting a ceramic resonator. PC0/OSC1 C = C = 5 to 30 pF PC1/OSC2/CLKOUT Figure 5.11 Example of Connection to Ceramic Resonator 5.5.3 External Clock Input Method To use the external clock, input the external clock on pin OSC1.

  • Page 114: Usage Notes

    Section 5 Clock Pulse Generators Usage Notes 5.7.1 Note on Resonators Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit parameters will differ depending on the resonator element, stray capacitance of the PCB, and other factors.

  • Page 115: Section 6 Power-Down Modes

    Section 6 Power-Down Modes Section 6 Power-Down Modes For operating modes after a reset, this LSI has not only a normal active mode but also three power-down modes in which power consumption is significantly reduced. In addition, there is also a module standby function which reduces power consumption by individually stopping on-chip peripheral modules.

  • Page 116: System Control Register 1 (Syscr1)

    Section 6 Power-Down Modes 6.1.1 System Control Register 1 (SYSCR1) SYSCR1 controls the power-down modes, as well as SYSCR2. Initial Bit Name Value Description SSBY Software Standby Specifies the operating mode to be entered after executing the SLEEP instruction. 0: Shifts to sleep mode. 1: Shifts to standby mode.

  • Page 117: Table 6.1 Operating Frequency And Wait Time

    Section 6 Power-Down Modes Table 6.1 Operating Frequency and Wait Time Bit Name Operating Frequency STS2 STS1 STS0 Wait Time 10 MHz 8 MHz 5 MHz 4 MHz 2.5 MHz 2 MHz 8,192 states 16,384 states 32,768 states 13.1 16.4 65,536 states 13.1 16.4...

  • Page 118: System Control Register 2 (Syscr2)

    Section 6 Power-Down Modes 6.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Initial Bit Name Value Description SMSEL Sleep Mode Selection This bit specifies the mode to be entered after executing the SLEEP instruction, as well as the SSBY bit in SYSCR1.

  • Page 119: Module Standby Control Register 1 (Mstcr1)

    Section 6 Power-Down Modes 6.1.3 Module Standby Control Register 1 (MSTCR1) MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units. Initial Bit Name Value Description   Reserved This bit is always read as 0. MSTIIC IIC2 Module Standby IIC2 enters standby mode when this bit is set to 1.

  • Page 120: Module Standby Control Register 2 (Mstcr2)

    Section 6 Power-Down Modes 6.1.4 Module Standby Control Register 2 (MSTCR2) MSTCR2 allows the on-chip peripheral modules to enter a standby state in module units. Initial Bit Name Value Description   7 to 5 All 0 Reserved These bits are always read as 0. MSTTB1 Timer B1 Module Standby Timer B1 enters standby mode when this bit is set to 1.

  • Page 121: Mode Transitions And States Of Lsi

    Section 6 Power-Down Modes Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction.

  • Page 122: Table 6.2 Transition Mode After Sleep Instruction Execution And Interrupt Handling

    Section 6 Power-Down Modes Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling Transition Mode after SLEEP Transition Mode due to DTON SSBY SMSEL Instruction Execution Interrupt Sleep mode Active mode Subsleep mode Active mode Standby mode Active mode Active mode (direct transition) —...

  • Page 123: Sleep Mode

    Section 6 Power-Down Modes 6.2.1 Sleep Mode In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2 to MA0 bits in SYSCR2. CPU register contents are retained. When an interrupt is requested, sleep mode is cleared and the CPU starts interrupt exception handling.

  • Page 124: Subsleep Mode

    Section 6 Power-Down Modes 6.2.3 Subsleep Mode In subsleep mode, the system clock oscillator is halted, and operation of the CPU and on-chip peripheral modules is halted. However, as long as the rated voltage is supplied, the contents of CPU registers, the on-chip RAM, and some on-chip peripheral module registers are retained. The I/O ports keep the same states as before the transition.

  • Page 125: Module Standby Function

    Section 6 Power-Down Modes Module Standby Function The module standby function can be set to any peripheral module. In module standby mode, the clock supply to the specified module stops and the module enters the power-down mode. Module standby mode enables each on-chip peripheral module to enter the standby state by setting a bit that corresponds to each module in MSTCR1 and MSTCR2 to 1 and cancels the mode by clearing the bit to 0.
  • Page 126 Section 6 Power-Down Modes Rev. 3.00 Sep. 14, 2006 Page 96 of 408 REJ09B0105-0300...

  • Page 127: Section 7 Rom

    Section 7 ROM Section 7 ROM The features of the 12-kbyte (including 4 kbytes as the E7 or E8 control program area) flash memory built into the HD64F36912G and HD64F36902G are summarized below. • Programming/erase methods  The flash memory is programmed in 64-byte units at a time. Erase is performed in single- block units.

  • Page 128: Figure 7.1 Flash Memory Block Configuration

    Section 7 ROM H'0000 H'0001 H'0002 H'003F Programming unit: 64 bytes Erase unit H'0040 H'0041 H'0042 H'007F 1 kbyte H'03C0 H'03C1 H'03C2 H'03FF H'0400 H'0401 H'0402 H'043F Programming unit: 64 bytes Erase unit H'0440 H'0441 H'0442 H'047F 1 kbyte H'07C0 H'07C1 H'07C2 H'07FF...

  • Page 129: Register Descriptions

    Section 7 ROM Register Descriptions The flash memory has the following registers. • Flash memory control register 1 (FLMCR1) • Flash memory control register 2 (FLMCR2) • Erase block register 1 (EBR1) • Flash memory enable register (FENR) 7.2.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode.

  • Page 130: Flash Memory Control Register 2 (Flmcr2)

    Section 7 ROM Initial Bit Name Value Description Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, program- verify mode is cancelled. Erase When this bit is set to 1 while SWE = 1 and ESU = 1, the flash memory changes to erase mode.

  • Page 131: Erase Block Register 1 (Ebr1)

    Section 7 ROM 7.2.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be automatically cleared to 0.

  • Page 132: On-Board Programming Modes

    Section 7 ROM On-Board Programming Modes There is a mode for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST pin settings, NMI pin settings, and input level of each port, as shown in table 7.1.
  • Page 133 Section 7 ROM 3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that of the host.

  • Page 134: Table 7.2 Boot Mode Operation

    Section 7 ROM Table 7.2 Boot Mode Operation Host Operation Communication Contents LSI Operation Processing Contents Processing Contents Branches to boot program at reset-start. Boot program initiation H'00, H'00 . . . H'00 Continuously transmits data H'00 • Measures low-level period of receive data at specified bit rate.

  • Page 135: Table 7.3 System Clock Frequencies For Which Automatic Adjustment Of Lsi Bit Rate Is Possible

    Section 7 ROM Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 9,600 bps 8 MHz (on-chip oscillator clock) 4,800 bps 8 MHz (on-chip oscillator clock) 2,400 bps 8 MHz (on-chip oscillator clock) Rev.

  • Page 136: Programming/Erasing In User Program Mode

    Section 7 ROM 7.3.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory.

  • Page 137: Flash Memory Programming/Erasing

    Section 7 ROM Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the on- board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode.

  • Page 138: Figure 7.3 Program/Program-Verify Flowchart

    Section 7 ROM START Write pulse application subroutine Disable WDT Apply Write Pulse Set SWE bit in FLMCR1 WDT enable Wait 1 µs Set PSU bit in FLMCR1 Store 64-byte program data in program data area and reprogram data area Wait 50 µs n = 1 Set P bit in FLMCR1...

  • Page 139: Erase/Erase-Verify

    Section 7 ROM Table 7.4 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments Programming completed Reprogram bit — Remains in erased state Table 7.5 Additional-Program Data Computation Table Additional-Program Reprogram Data Verify Data Data Comments Additional-program bit No additional programming No additional programming No additional programming...

  • Page 140: Interrupt Handling When Programming/Erasing Flash Memory

    Section 7 ROM 6. If the read data is not erased successfully, set erase mode again, and repeat the erase/erase- verify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is 100. 7.4.3 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1.

  • Page 141: Figure 7.4 Erase/Erase-Verify Flowchart

    Section 7 ROM Erase start Disable WDT SWE bit ← 1 Wait 1 µs n ← 1 Set EBR1 Enable WDT ESU bit ← 1 Wait 100 µs E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 µs ESU bit ←...

  • Page 142: Program/Erase Protection

    Section 7 ROM Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subsleep mode or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), and erase block register 1 (EBR1) are initialized.
  • Page 143 Section 7 ROM The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re- entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode.
  • Page 144 Section 7 ROM Rev. 3.00 Sep. 14, 2006 Page 114 of 408 REJ09B0105-0300...

  • Page 145: Section 8 Ram

    Section 8 RAM Section 8 RAM The H8/36912F and H8/36902F have 1536 bytes, the H8/36912 and H8/36902 have 512 bytes, and the H8/36911, H8/36901, and H8/36900 have 256 bytes of on-chip high-speed static RAM, respectively. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data.
  • Page 146 Section 8 RAM Rev. 3.00 Sep. 14, 2006 Page 116 of 408 REJ09B0105-0300...

  • Page 147: Section 9 I/O Ports

    Section 9 I/O Ports Section 9 I/O Ports The LSI of the H8/36912 Group and H8/36902 Group has 18 general I/O ports. Port 8 (P84 to P80) is a large current port, which can drive 20 mA (@V = 1.5 V) when a low level signal is output.

  • Page 148: Port Mode Register 1 (Pmr1)

    Section 9 I/O Ports 9.1.1 Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Initial Bit Name Value Description IRQ3 P17/IRQ3/TRGV Pin Function Switch Selects whether pin P17/IRQ3/TRGV is used as P17 or as IRQ3/TRGV.

  • Page 149: Port Control Register 1 (Pcr1)

    Section 9 I/O Ports 9.1.2 Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Initial Bit Name Value Description PCR17 When the corresponding pin is designated in PMR1 as a general I/O pin, setting a PCR1 bit to 1 makes the ...

  • Page 150: Port Pull-Up Control Register 1 (Pucr1)

    Section 9 I/O Ports 9.1.4 Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports. Initial Bit Name Value Description PUCR17 Only bits for which PCR1 is cleared are valid. ...

  • Page 151: Port 2

    Section 9 I/O Ports • P14/IRQ0 pin Register PMR1 PCR1 Bit Name IRQ0 PCR14 Pin Function Setting value 0 P14 input pin P14 output pin IRQ0 input pin [Legend] Don't care Port 2 Port 2 is a general I/O port also functioning as a SCI3 I/O pin. Each pin of the port 2 is shown in figure 9.2.

  • Page 152: Port Control Register 2 (Pcr2)

    Section 9 I/O Ports 9.2.1 Port Control Register 2 (PCR2) PCR2 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 2. Initial Bit Name Value Description    7 to 3 Reserved PCR22 When each of the port 2 pins, P22 to P20, functions as an general I/O port, setting a PCR2 bit to 1 makes the...

  • Page 153: Pin Functions

    Section 9 I/O Ports 9.2.3 Pin Functions The correspondence between the register specification and the port functions is shown below. • P22/TXD pin Register PMR1 PCR2 Bit Name PCR22 Pin Function Setting P22 input pin value P22 output pin TXD output pin [Legend] Don't care •...

  • Page 154: Port 5

    Section 9 I/O Ports Port 5 Port 5 is a general I/O port also functioning as an I C bus interface I/O pin*, A/D trigger input pin, and wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.3. The register setting of the I C bus interface has priority for functions of the P57/SCL and P56/SDA pins.

  • Page 155: Port Mode Register 5 (Pmr5)

    Section 9 I/O Ports 9.3.1 Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5. Initial Bit Name Value Description   7, 6 All 0 Reserved These bits are always read as 0. WKP5 P55/WKP5/ADTRG Pin Function Switch Selects whether pin P55/WKP5/ADTRG is used as P55 or as WKP5/ADTRG.

  • Page 156: Port Data Register 5 (Pdr5)

    Section 9 I/O Ports 9.3.3 Port Data Register 5 (PDR5) PDR5 is a general I/O port data register of port 5. Initial Bit Name Value Description These bits store output data for port 5 pins. If PDR5 is read while PCR5 bits are set to 1, the value stored in PDR5 are read.

  • Page 157: Pin Functions

    Section 9 I/O Ports 9.3.5 Pin Functions The correspondence between the register specification and the port functions is shown below. • P57/SCL pin Register ICCR PCR5 Bit Name PCR57 Pin Function Setting value P57 input pin P57 output pin SCL I/O pin* [Legend] Don't care Note:...

  • Page 158: Port 7

    Section 9 I/O Ports Port 7 Port 7 is a general I/O port also functioning as a timer V I/O pin. Each pin of the port 7 is shown in figure 9.4. The register setting of TCSRV in timer V has priority for functions of the P76/TMOV pin.

  • Page 159: Port Data Register 7 (Pdr7)

    Section 9 I/O Ports 9.4.2 Port Data Register 7 (PDR7) PDR7 is a general I/O port data register of port 7. Initial Bit Name Value Description   Reserved This bit is always read as 1. These bits store output data for port 7 pins. If PDR7 is read while PCR7 bits are set to 1, the value stored in PDR7 is read.

  • Page 160: Port 8

    Section 9 I/O Ports • P75/TMCIV pin Register PCR7 Bit Name PCR75 Pin Function Setting value 0 P75 input/TMCIV input pin P75 output/TMCIV input pin • P74/TMRIV pin Register PCR7 Bit Name PCR74 Pin Function Setting value 0 P74 input/TMRIV input pin P74 output/TMRIV input pin Port 8 Port 8 is a general I/O port also functioning as a timer W I/O pin.

  • Page 161: Port Control Register 8 (Pcr8)

    Section 9 I/O Ports 9.5.1 Port Control Register 8 (PCR8) PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8. Initial Bit Name Value Description    7 to 5 Reserved PCR84 When each of the port 8 pins, P84 to P80, functions as an general I/O port, setting a PCR8 bit to 1 makes the...

  • Page 162: Pin Functions

    Section 9 I/O Ports 9.5.3 Pin Functions The correspondence between the register specification and the port functions is shown below. • P84/FTIOD pin Register TMRW TIOR1 PCR8 Bit Name PWMD IOD2 IOD1 IOD0 PCR84 Pin Function Setting P84 input/FTIOD input pin value P84 output/FTIOD input pin FTIOD output pin...
  • Page 163 Section 9 I/O Ports • P82/FTIOB pin Register TMRW TIOR0 PCR8 Bit Name PWMB IOB2 IOB1 IOB0 PCR82 Pin Function Setting P82 input/FTIOB input pin value P82 output/FTIOB input pin FTIOB output pin FTIOB output pin P82 input/FTIOB input pin P82 output/FTIOB input pin PWM output pin [Legend]...

  • Page 164: Port B

    Section 9 I/O Ports Port B Port B is an input port also functioning as an A/D converter analog input pin and LVD external comparison voltage input pin. Each pin of the port B is shown in figure 9.6. PB3/AN3/ExtU PB2/AN2/ExtD Port B PB1/AN1...

  • Page 165: Pin Functions

    Section 9 I/O Ports 9.6.2 Pin Functions The correspondence between the register specification and the port functions is shown below. • PB3/AN3/ExtU pin Register ADCSR LVDCR Bit Name VDDII Pin Function Setting value AN3 input pin AN3 input/ExtU input pin Other than the above values PB3 input pin PB3 input/ExtU input pin...

  • Page 166: Port C

    Section 9 I/O Ports • PB0/AN0 pin Register ADCSR Bit Name SCAN Pin Function Setting AN0 input pin value Other than the above values PB0 input pin [Legend] Don't care Port C Port C is a general I/O port also functioning as an external oscillation pin and clock output pin. Each pin of the port C is shown in figure 9.7.

  • Page 167: Port Control Register C (Pcrc)

    Section 9 I/O Ports 9.7.1 Port Control Register C (PCRC) PCRC selects inputs/outputs in bit units for pins to be used as general I/O ports of port C. Initial Bit Name Value Description    7 to 2 Reserved PCRC1 When each of the port C pins, PC1 and PC0, functions as an general I/O port, setting a PCRC bit to 1 makes the...

  • Page 168: Pin Functions

    Section 9 I/O Ports 9.7.3 Pin Functions The correspondence between the register specification and the port functions is shown below. • PC1/OSC2/CLKOUT pin Register CKCSR PCRC Bit Name PMRC1 PMRC0 PCRC1 Pin Function Setting value PC1 input pin PC1 output pin CLKOUT output pin OSC2 oscillation pin [Legend]...

  • Page 169: Section 10 Timer B1

    Section 10 Timer B1 Section 10 Timer B1 Timer B1 is an 8-bit timer that increments each time a clock pulse is input. This timer has two operating modes, interval and auto reload. Figure 10.1 shows a block diagram of timer B1. 10.1 Features •...

  • Page 170: Register Descriptions

    Section 10 Timer B1 10.2 Register Descriptions The timer B1 has the following registers. • Timer mode register B1 (TMB1) • Timer counter B1 (TCB1) • Timer load register B1 (TLB1) 10.2.1 Timer Mode Register B1 (TMB1) TMB1 selects the auto-reload function and input clock. Initial Bit Name Value...

  • Page 171: Timer Counter B1 (Tcb1)

    Section 10 Timer B1 10.2.2 Timer Counter B1 (TCB1) TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMB12 to TMB10 in TMB1. TCB1 values can be read by the CPU at any time.

  • Page 172: Operation

    Section 10 Timer B1 10.3 Operation 10.3.1 Interval Timer Operation When bit TMB17 in TMB1 is cleared to 0, timer B1 functions as an 8-bit interval timer. Upon reset, TCB1 is cleared to H'00 and bit TMB17 is cleared to 0, so up-counting and interval timing resume immediately.

  • Page 173: Timer B1 Operating Modes

    Section 10 Timer B1 10.4 Timer B1 Operating Modes Table 10.1 shows the timer B1 operating modes. Table 10.1 Timer B1 Operating Modes Operating Mode Reset Active Sleep Subsleep Standby TCB1 Interval Reset Functions Functions Halted Halted Auto-reload Reset Functions Functions Halted Halted...
  • Page 174 Section 10 Timer B1 Rev. 3.00 Sep. 14, 2006 Page 144 of 408 REJ09B0105-0300...

  • Page 175: Section 11 Timer V

    Section 11 Timer V Section 11 Timer V Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Compare- match signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle.
  • Page 176 Section 11 Timer V TCRV1 TCORB Trigger TRGV control Comparator Clock select TMCIV TCNTV Comparator φ TCORA Clear TCRV0 TMRIV control Interrupt request control Output TMOV TCSRV control CMIA CMIB [Legend] TCORA: Time constant register A TCORB: Time constant register B TCNTV: Timer counter V TCSRV:...

  • Page 177: Input/Output Pins

    Section 11 Timer V 11.2 Input/Output Pins Table 11.1 shows the timer V pin configuration. Table 11.1 Pin Configuration Name Abbreviation I/O Function Timer V output TMOV Output Timer V waveform output Timer V clock input TMCIV Input Clock input to TCNTV Timer V reset input TMRIV Input...

  • Page 178: Time Constant Registers A And B (Tcora, Tcorb)

    Section 11 Timer V 11.3.2 Time Constant Registers A and B (TCORA, TCORB) TCORA and TCORB have the same function. TCORA and TCORB are 8-bit read/write registers. TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match, CMFA is set to 1 in TCSRV.

  • Page 179: Table 11.2 Clock Signals To Input To Tcntv And Counting Conditions

    Section 11 Timer V Initial Bit Name Value Description CCLR1 Counter Clear 1 and 0 CCLR0 These bits specify the clearing conditions of TCNTV. 00: Clearing is disabled 01: Cleared by compare match A 10: Cleared by compare match B 11: Cleared on the rising edge of the TMRIV pin.

  • Page 180: Timer Control/Status Register V (Tcsrv)

    Section 11 Timer V 11.3.4 Timer Control/Status Register V (TCSRV) TCSRV indicates the status flag and controls outputs by using a compare match. Initial Bit Name Value Description CMFB Compare Match Flag B [Setting condition] • When the TCNTV value matches the TCORB value [Clearing condition] •...

  • Page 181: Timer Control Register V1 (Tcrv1)

    Section 11 Timer V Initial Bit Name Value Description Output Select 1 and 0 These bits select an output method for the TMOV pin by the compare match of TCORA and TCNTV. 00: No change 01: 0 output 10: 1 output 11: Output toggles OS3 and OS2 select the output level for compare match B.

  • Page 182: Operation

    Section 11 Timer V Initial Bit Name Value Description   Reserved This bit is always read as 1. ICKS0 Internal Clock Select 0 This bit selects clock signals to input to TCNTV in combination with CKS2 to CKS0 in TCRV0. Refer to table 11.2.

  • Page 183: Figure 11.2 Increment Timing With Internal Clock

    Section 11 Timer V φ Internal clock TCNTV input clock N – 1 N + 1 TCNTV Figure 11.2 Increment Timing with Internal Clock φ TMCIV (External clock input pin) TCNTV input clock N – 1 N + 1 TCNTV Figure 11.3 Increment Timing with External Clock φ...

  • Page 184: Figure 11.5 Cmfa And Cmfb Set Timing

    Section 11 Timer V φ TCNTV TCORA or TCORB Compare match signal CMFA or CMFB Figure 11.5 CMFA and CMFB Set Timing φ Compare match A signal Timer V output Figure 11.6 TMOV Output Timing φ Compare match A signal H'00 TCNTV Figure 11.7 Clear Timing by Compare Match...

  • Page 185: Timer V Application Examples

    Section 11 Timer V φ TMRIV (External counter reset input pin) TCNTV reset signal N – 1 H'00 TCNTV Figure 11.8 Clear Timing by TMRIV Input 11.5 Timer V Application Examples 11.5.1 Pulse Output with Arbitrary Duty Cycle Figure 11.9 shows an example of output of pulses with an arbitrary duty cycle. 1.

  • Page 186: Pulse Output With Arbitrary Pulse Width And Delay From Trgv Input

    Section 11 Timer V 11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 11.10. To set up this output: 1.

  • Page 187: Usage Notes

    Section 11 Timer V 11.6 Usage Notes The following types of contention or operation can occur in timer V operation. 1. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 11.11, clearing takes precedence and the write to the counter is not carried out.

  • Page 188: Figure 11.12 Contention Between Tcora Write And Compare Match

    Section 11 Timer V TCORA write cycle by CPU φ TCORA address Address Internal write signal TCNTV TCORA TCORA write data Compare match signal Inhibited Figure 11.12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV Write to CKS1 and CKS0...

  • Page 189: Section 12 Timer W

    Section 12 Timer W Section 12 Timer W The timer W has a 16-bit timer having output compare and input capture functions. The timer W can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers.

  • Page 190: Table 12.1 Timer W Functions

    Section 12 Timer W Table 12.1 summarizes the timer W functions, and figure 12.1 shows a block diagram of the timer Table 12.1 Timer W Functions Input/Output Pins Item Counter FTIOA FTIOB FTIOC FTIOD Internal clocks: φ, φ/2, φ/4, φ/8 Count clock External clock: FTCI General registers...

  • Page 191: Figure 12.1 Timer W Block Diagram

    Section 12 Timer W φ Internal clock: FTIOA φ /2 Clock φ /4 FTIOB selector φ /8 FTIOC Control logic External clock: FTCI FTIOD Comparator IRRTW Internal data bus [Legend] TMRW: Timer mode register W (8 bits) TCRW: Timer control register W (8 bits) TIERW: Timer interrupt enable register W (8 bits) TSRW: Timer status register W (8 bits)

  • Page 192: Input/Output Pins

    Section 12 Timer W 12.2 Input/Output Pins Table 12.2 summarizes the timer W pins. Table 12.2 Pin Configuration Name Abbreviation Input/Output Function External clock input FTCI Input External clock input pin Input capture/output FTIOA Input/output Output pin for GRA output compare or compare A input pin for GRA input capture Input capture/output...

  • Page 193: Timer Mode Register W (Tmrw)

    Section 12 Timer W 12.3.1 Timer Mode Register W (TMRW) TMRW selects the general register functions and the timer output mode. Initial Bit Name Value Description Counter Start The counter operation is halted when this bit is 0, while it can be performed when this bit is 1.

  • Page 194: Timer Control Register W (Tcrw)

    Section 12 Timer W 12.3.2 Timer Control Register W (TCRW) TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer output levels. Initial Bit Name Value Description CCLR Counter Clear The TCNT value is cleared by compare match A when this bit is 1.

  • Page 195: Timer Interrupt Enable Register W (Tierw)

    Section 12 Timer W Initial Bit Name Value Description Timer Output Level Setting A Sets the output value of the FTIOA pin until the first compare match A is generated. 0: Output value is 0* 1: Output value is 1* [Legend] Don't care Note:...

  • Page 196: Timer Status Register W (Tsrw)

    Section 12 Timer W 12.3.4 Timer Status Register W (TSRW) TSRW shows the status of interrupt requests. Initial Bit Name Value Description Timer Overflow Flag [Setting condition] • When TCNT overflows from H'FFFF to H'0000 [Clearing condition] • Read OVF when OVF = 1, then write 0 in OVF ...
  • Page 197 Section 12 Timer W Initial Bit Name Value Description IMFB Input Capture/Compare Match Flag B [Setting conditions] • TCNT = GRB when GRB functions as an output compare register • The TCNT value is transferred to GRB by an input capture signal when GRB functions as an input capture register [Clearing condition]...

  • Page 198: Timer I/O Control Register 0 (Tior0)

    Section 12 Timer W 12.3.5 Timer I/O Control Register 0 (TIOR0) TIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and FTIOB pins. Initial Bit Name Value Description   Reserved This bit is always read as 1. IOB2 I/O Control B2 Selects the GRB function.

  • Page 199: Timer I/O Control Register 1 (Tior1)

    Section 12 Timer W Initial Bit Name Value Description IOA1 I/O Control A1 and A0 IOA0 When IOA2 = 0, 00: No output at compare match 01: 0 output to the FTIOA pin at GRA compare match 10: 1 output to the FTIOA pin at GRA compare match 11: Output toggles to the FTIOA pin at GRA compare match When IOA2 = 1,...
  • Page 200 Section 12 Timer W Initial Bit Name Value Description IOD1 I/O Control D1 and D0 IOD0 When IOD2 = 0, 00: No output at compare match 01: 0 output to the FTIOD pin at GRD compare match 10: 1 output to the FTIOD pin at GRD compare match 11: Output toggles to the FTIOD pin at GRD compare match When IOD2 = 1,...

  • Page 201: Timer Counter (Tcnt)

    Section 12 Timer W 12.3.7 Timer Counter (TCNT) TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA by setting the CCLR in TCRW to 1.

  • Page 202: Operation

    Section 12 Timer W 12.4 Operation The timer W has the following operating modes. • Normal Operation • PWM Operation 12.4.1 Normal Operation TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a free- running counter. When the CTS bit in TMRW is set to 1, TCNT starts incrementing the count. When the count overflows from H'FFFF to H'0000, the OVF flag in TSRW is set to 1.

  • Page 203: Figure 12.3 Periodic Counter Operation

    Section 12 Timer W Periodic counting operation can be performed when GRA is set as an output compare register and bit CCLR in TCRW is set to 1. When the count matches GRA, TCNT is cleared to H'0000, the IMFA flag in TSRW is set to 1. If the corresponding IMIEA bit in TIERW is set to 1, an interrupt request is generated.

  • Page 204: Figure 12.5 Toggle Output Example (Toa = 0, Tob = 1)

    Section 12 Timer W Figure 12.5 shows an example of toggle output when TCNT operates as a free-running counter, and toggle output is selected for both compare match A and B. TCNT value H'FFFF Time H'0000 Toggle output FTIOA Toggle output FTIOB Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1) Figure 12.6 shows another example of toggle output when TCNT operates as a periodic counter,...

  • Page 205: Figure 12.7 Input Capture Operating Example

    Section 12 Timer W The TCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when a signal level changes at an input-capture pin (FTIOA, FTIOB, FTIOC, or FTIOD). Capture can take place on the rising edge, falling edge, or both edges. By using the input-capture function, the pulse width and periods can be measured.

  • Page 206: Pwm Operation

    Section 12 Timer W Figure 12.8 shows an example of buffer operation when the GRA is set as an input-capture register and GRC is set as the buffer register for GRA. TCNT operates as a free-running counter, and FTIOA captures both rising and falling edge of the input signal. Due to the buffer operation, the GRA value is transferred to GRC by input-capture A and the TCNT value is stored in GRA.

  • Page 207: Figure 12.9 Pwm Mode Example (1)

    Section 12 Timer W TCNT value Counter cleared by compare match A H'0000 Time FTIOB FTIOC FTIOD Figure 12.9 PWM Mode Example (1) Figure 12.10 shows another example of operation in PWM mode. The output signals go to 0 and TCNT is cleared at compare match A, and the output signals go to 1 at compare match B, C, and D (TOB, TOC, and TOD = 0: initial output values are set to 1).

  • Page 208: Figure 12.11 Buffer Operation Example (Output Compare)

    Section 12 Timer W Figure 12.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB outputs 1 at compare match B and 0 at compare match A.

  • Page 209: Figure 12.12 Pwm Mode Example (Tob, Toc, And Tod = 0: Initial Output Values Are Set To 0)

    Section 12 Timer W Figures 12.12 and 12.13 show examples of the output of PWM waveforms with duty cycles of 0% and 100%. TCNT value Write to GRB Write to GRB H'0000 Time Duty 0% FTIOB Output does not change when cycle register and duty register compare matches occur TCNT value simultaneously.

  • Page 210: Figure 12.13 Pwm Mode Example (Tob, Toc, And Tod = 1: Initial Output Values Are Set To 1)

    Section 12 Timer W TCNT value Write to GRB Write to GRB H'0000 Time Duty 100% FTIOB Output does not change when cycle register and duty register compare matches occur TCNT value simultaneously. Write to GRB Write to GRB Write to GRB H'0000 Time Duty 0%...

  • Page 211: Operation Timing

    Section 12 Timer W 12.5 Operation Timing 12.5.1 TCNT Count Timing Figure 12.14 shows the TCNT count timing when the internal clock source is selected. Figure 12.15 shows the timing when the external clock source is selected. The pulse width of the external clock signal must be at least two system clock (φ) cycles;...

  • Page 212: Output Compare Output Timing

    Section 12 Timer W 12.5.2 Output Compare Output Timing The compare match signal is generated in the last state in which TCNT and GR match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD).

  • Page 213: Input Capture Timing

    Section 12 Timer W 12.5.3 Input Capture Timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR0 and TIOR1. Figure 12.17 shows the timing when the falling edge is selected. The pulse width of the input capture signal must be at least two system clock (φ) cycles;...

  • Page 214: Buffer Operation Timing

    Section 12 Timer W 12.5.5 Buffer Operation Timing Figures 12.19 and 12.20 show the buffer operation timing. φ Compare match signal TCNT GRC, GRD GRA, GRB Figure 12.19 Buffer Operation Timing (Compare Match) φ Input capture signal TCNT GRA, GRB GRC, GRD Figure 12.20 Buffer Operation Timing (Input Capture) Rev.

  • Page 215: Timing Of Imfa To Imfd Flag Setting At Compare Match

    Section 12 Timer W 12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general register.

  • Page 216: Timing Of Imfa To Imfd Setting At Input Capture

    Section 12 Timer W 12.5.7 Timing of IMFA to IMFD Setting at Input Capture If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure 12.22 shows the timing of the IMFA to IMFD flag setting at input capture.

  • Page 217: Usage Notes

    Section 12 Timer W 12.6 Usage Notes The following types of contention or operation can occur in timer W operation. 1. The pulse width of the input clock signal and the input capture signal must be at least two system clock (φ) cycles; shorter pulses will not be detected correctly. 2.

  • Page 218: Figure 12.24 Contention Between Tcnt Write And Clear

    Section 12 Timer W TCNT write cycle φ TCNT address Address Write signal Counter clear signal H'0000 TCNT Figure 12.24 Contention between TCNT Write and Clear Clock before switching Clock after switching Count clock TCNT The change in signal level at clock switching is assumed to be a rising edge, and TCNT increments the count.

  • Page 219: Figure 12.26 When Compare Match And Bit Manipulation Instruction To Tcrw Occur At The Same Timing

    Section 12 Timer W TCRW has been set to H'06. Compare match B and compare match C are used. The FTIOB pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match B. When BCLR#2, @TCRW is executed to clear the TOC bit (the FTIOC signal is low) and compare match B occurs at the same timing as shown below, the H'02 writing to TCRW has priority and compare match B does not drive the FTIOB signal low;...
  • Page 220 Section 12 Timer W Rev. 3.00 Sep. 14, 2006 Page 190 of 408 REJ09B0105-0300...

  • Page 221: Section 13 Watchdog Timer

    Section 13 Watchdog Timer Section 13 Watchdog Timer The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. The block diagram of the watchdog timer is shown in figure 13.1.

  • Page 222: Register Descriptions

    Section 13 Watchdog Timer 13.2 Register Descriptions The watchdog timer has the following registers. • Timer control/status register WD (TCSRWD) • Timer counter WD (TCWD) • Timer mode register WD (TMWD) 13.2.1 Timer Control/Status Register WD (TCSRWD) TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the watchdog timer operation and indicates the operating state.
  • Page 223 Section 13 Watchdog Timer Initial Bit Name Value Description WDON Watchdog Timer On TCWD starts counting up when the WDON bit is set to 1 and halts when the WDON bit is cleared to 0. The watchdog timer is enabled in the initial state. When the watchdog timer is not used, clear the WDON bit to 0.

  • Page 224: Timer Counter Wd (Tcwd)

    Section 13 Watchdog Timer 13.2.2 Timer Counter WD (TCWD) TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the internal reset signal is generated and the WRST bit in TCSRWD is set to 1. TCWD is initialized to H'00.

  • Page 225: Operation

    Section 13 Watchdog Timer 13.3 Operation The watchdog timer is provided with an 8-bit counter. After the reset state is released, TCWD starts counting up. When the TCWD count value overflows H'FF, an internal reset signal is generated. The internal reset signal is output for a period of 256 φ clock cycles.
  • Page 226 Section 13 Watchdog Timer Rev. 3.00 Sep. 14, 2006 Page 196 of 408 REJ09B0105-0300...

  • Page 227: Section 14 Serial Communication Interface 3 (Sci3)

    Section 14 Serial Communication Interface 3 (SCI3) Section 14 Serial Communication Interface 3 (SCI3) This LSI includes serial communication interface 3 (SCI3). SCI3 can handle both asynchronous and clocked synchronous serial communication. In asynchronous mode, serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA).

  • Page 228: Figure 14.1 Block Diagram Of Sci3

    Section 14 Serial Communication Interface 3 (SCI3) Clocked synchronous mode • Data length: 8 bits • Receive error detection: Overrun errors External Internal clock (φ/64,φ/16, φ/4, φ) SCK3 clock Baud rate generator Clock SCR3 Transmit/receive control circuit SPMR Noise filter circuit Interrupt request (TEI, TXI, RXI, ERI) [Legend]...

  • Page 229: Input/Output Pins

    Section 14 Serial Communication Interface 3 (SCI3) 14.2 Input/Output Pins Table 14.1 shows the SCI3 pin configuration. Table 14.1 Pin Configuration Pin Name Abbreviation Function SCI3 clock SCK3 Input/output SCI3 clock input/output SCI3 receive data input Input SCI3 receive data input SCI3 transmit data output Output SCI3 transmit data output...

  • Page 230: Receive Shift Register (Rsr)

    Section 14 Serial Communication Interface 3 (SCI3) 14.3.1 Receive Shift Register (RSR) RSR is a shift register that is used to receive serial data input from the RXD pin and convert it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU.

  • Page 231: Serial Mode Register (Smr)

    Section 14 Serial Communication Interface 3 (SCI3) 14.3.5 Serial Mode Register (SMR) SMR is used to set the SCI3’s serial transfer format and select the baud rate generator clock source. Initial Bit Name Value Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length.

  • Page 232: Serial Control Register 3 (Scr3)

    Section 14 Serial Communication Interface 3 (SCI3) Initial Bit Name Value Description CKS1 Clock Select 0 and 1 CKS0 These bits select the clock source for the baud rate generator. 00: φ clock (n = 0) 01: φ/4 clock (n = 1) 10: φ/16 clock (n = 2) 11: φ/64 clock (n = 3) For the relationship between the bit rate register setting...
  • Page 233 Section 14 Serial Communication Interface 3 (SCI3) Initial Bit Name Value Description MPIE Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and OER status flags in SSR is disabled.

  • Page 234: Serial Status Register (Ssr)

    Section 14 Serial Communication Interface 3 (SCI3) 14.3.7 Serial Status Register (SSR) SSR is a register containing status flags of SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. Initial Bit Name Value...
  • Page 235 Section 14 Serial Communication Interface 3 (SCI3) Initial Bit Name Value Description Parity Error [Setting condition] • When a parity error is detected during reception [Clearing condition] • When 0 is written to PER after reading PER = 1 TEND Transmit End [Setting conditions] •...

  • Page 236: Bit Rate Register (Brr)

    Section 14 Serial Communication Interface 3 (SCI3) 14.3.8 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 14.2 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in asynchronous mode.

  • Page 237: Table 14.2 Examples Of Brr Settings For Various Bit Rates (Asynchronous Mode)

    Section 14 Serial Communication Interface 3 (SCI3) Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency φ (MHz) 2.097152 2.4576 Bit Rate Error Error Error Error (bits/s) 0.03 –0.04 –0.26 0.03 0.16 0.21 0.00 0.16 0.16 0.21 0.00...
  • Page 238 Section 14 Serial Communication Interface 3 (SCI3) Operating Frequency φ (MHz) 3.6864 4.9152 Bit Rate Error Error Error Error (bits/s) 0.70 0.03 0.31 –0.25 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 1200 0.00 0.16 0.00 0.16 2400 0.00...

  • Page 239: Table 14.3 Maximum Bit Rate For Each Frequency (Asynchronous Mode)

    Section 14 Serial Communication Interface 3 (SCI3) Operating Frequency φ (MHz) 9.8304 Bit Rate (bit/s) Error (%) Error (%) Error (%) 0.03 –0.26 –0.25 0.16 0.00 0.16 0.16 0.00 0.16 0.16 0.00 0.16 1200 0.16 0.00 0.16 2400 0.16 0.00 0.16 4800 0.16...

  • Page 240: Table 14.4 Examples Of Brr Settings For Various Bit Rates (Clocked Synchronous Mode)

    Section 14 Serial Communication Interface 3 (SCI3) Table 14.4 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) Bit Rate (bit/s) — — — — — — — — — — — — 2.5k 100k 250k 500k...

  • Page 241: Sampling Mode Register (Spmr)

    Section 14 Serial Communication Interface 3 (SCI3) 14.3.9 Sampling Mode Register (SPMR) SPMR controls the serial communication function. Initial Bit Name Value Description   7 to 3 All 1 Reserved These bits are always read as 1. STDSPM Noise Filter Function Select Selects the noise filter function for the RXD pin in asynchronous mode.

  • Page 242: Operation In Asynchronous Mode

    Section 14 Serial Communication Interface 3 (SCI3) 14.4 Operation in Asynchronous Mode Figure 14.3 shows the general format for asynchronous serial communication. One character (or frame) consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level).

  • Page 243: Sci3 Initialization

    Section 14 Serial Communication Interface 3 (SCI3) 14.4.2 SCI3 Initialization Before transmitting and receiving data, you should first clear the TE and RE bits in SCR3 to 0, then initialize SCI3 as described below. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure.

  • Page 244: Data Transmission

    Section 14 Serial Communication Interface 3 (SCI3) 14.4.3 Data Transmission Figure 14.6 shows an example of operation for transmission in asynchronous mode. In transmission, SCI3 operates as described below. 1. SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR.

  • Page 245: Figure 14.7 Sample Serial Transmission Data Flowchart (Asynchronous Mode)

    Section 14 Serial Communication Interface 3 (SCI3) Start transmission [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is Read TDRE flag in SSR written to TDR, the TDRE flag is automaticaly cleared to 0.

  • Page 246: Serial Data Reception

    Section 14 Serial Communication Interface 3 (SCI3) 14.4.4 Serial Data Reception Figure 14.8 shows an example of operation for reception in asynchronous mode. In serial reception, SCI3 operates as described below. 1. SCI3 monitors the communication line. If a start bit is detected, SCI3 performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit.

  • Page 247: Table 14.5 Ssr Status Flags And Receive Data Handling

    Section 14 Serial Communication Interface 3 (SCI3) Table 14.5 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1.

  • Page 248: Figure 14.9 Sample Serial Reception Data Flowchart (Asynchronous Mode)

    Section 14 Serial Communication Interface 3 (SCI3) [1] Read the OER, PER, and FER flags in Start reception SSR to identify the error. If a receive error occurs, performs the appropriate error processing. Read OER, PER, and [2] Read SSR and check that RDRF = 1, FER flags in SSR then read the receive data in RDR.

  • Page 249: Operation In Clocked Synchronous Mode

    Section 14 Serial Communication Interface 3 (SCI3) 14.5 Operation in Clocked Synchronous Mode Figure 14.10 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the synchronization clock to the next.

  • Page 250: Sci3 Initialization

    Section 14 Serial Communication Interface 3 (SCI3) 14.5.2 SCI3 Initialization Before transmitting and receiving data, SCI3 should be initialized as described in a sample flowchart in figure 14.5. 14.5.3 Serial Data Transmission Figure 14.11 shows an example of SCI3 operation for transmission in clocked synchronous mode. In serial transmission, SCI3 operates as described below.

  • Page 251: Figure 14.11 Example Of Sci3 Transmission In Clocked Synchronous Mode

    Section 14 Serial Communication Interface 3 (SCI3) Figure 14.12 shows a sample flow chart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1. Make sure that the receive error flags are cleared to 0 before starting transmission.

  • Page 252: Figure 14.12 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)

    Section 14 Serial Communication Interface 3 (SCI3) Start transmission Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag Read TDRE flag in SSR is automatically cleared to 0 and clocks are output to start the data transmission.

  • Page 253: Serial Data Reception (Clocked Synchronous Mode)

    Section 14 Serial Communication Interface 3 (SCI3) 14.5.4 Serial Data Reception (Clocked Synchronous Mode) Figure 14.13 shows an example of SCI3 operation for reception in clocked synchronous mode. In serial reception, SCI3 operates as described below. 1. SCI3 performs internal initialization synchronous with a synchronization clock input or output, starts receiving data.

  • Page 254: Figure 14.14 Sample Serial Reception Flowchart (Clocked Synchronous Mode)

    Section 14 Serial Communication Interface 3 (SCI3) Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.14 shows a sample flow chart for serial data reception.

  • Page 255: Simultaneous Serial Data Transmission And Reception

    Section 14 Serial Communication Interface 3 (SCI3) 14.5.5 Simultaneous Serial Data Transmission and Reception Figure 14.15 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations.

  • Page 256: Figure 14.15 Sample Flowchart Of Simultaneous Serial Transmit And Receive Operations (Clocked Synchronous Mode)

    Section 14 Serial Communication Interface 3 (SCI3) Read SSR and check that the TDRE flag is set to 1, then write transmit Start transmission/reception data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to Read TDRE flag in SSR Read SSR and check that the RDRF flag is set to 1, then read the receive...

  • Page 257: Multiprocessor Communication Function

    Section 14 Serial Communication Interface 3 (SCI3) 14.6 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code.

  • Page 258: Figure 14.16 Example Of Inter-Processor Communication Using Multiprocessor Format (Transmission Of Data H'aa To Receiving Station A)

    Section 14 Serial Communication Interface 3 (SCI3) Transmitting station Serial transmission line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle =...

  • Page 259: Multiprocessor Serial Data Transmission

    Section 14 Serial Communication Interface 3 (SCI3) 14.6.1 Multiprocessor Serial Data Transmission Figure 14.17 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission.

  • Page 260: Figure 14.17 Sample Multiprocessor Serial Transmission Flowchart

    Section 14 Serial Communication Interface 3 (SCI3) Start transmission Read SSR and check that the TDRE flag is set to 1, set the MPBT bit in Read TDRE flag in SSR SSR to 0 or 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0.

  • Page 261: Multiprocessor Serial Data Reception

    Section 14 Serial Communication Interface 3 (SCI3) 14.6.2 Multiprocessor Serial Data Reception Figure 14.18 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR.

  • Page 262: Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (1)

    Section 14 Serial Communication Interface 3 (SCI3) Set the MPIE bit in SCR3 to 1. Start reception Read OER and FER in SSR to check for errors. Receive error processing is performed Set MPIE bit in SCR3 to 1 in cases where a receive error occurs. Read SSR and check that the RDRF flag is Read OER and FER flags in SSR set to 1, then read the receive data in RDR...

  • Page 263: Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (2)

    Section 14 Serial Communication Interface 3 (SCI3) Error processing OER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear OER, and FER flags in SSR to 0 <End> Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (2) Rev.

  • Page 264: Figure 14.19 Example Of Sci3 Reception Using Multiprocessor Format (Example With 8-Bit Data, Multiprocessor Bit, One Stop Bit)

    Section 14 Serial Communication Interface 3 (SCI3) Start Receive Stop Start Receive data Stop Mark state data (ID1) (Data1) (idle state) Serial data 1 frame 1 frame MPIE RDRF value RXI interrupt RDRF flag RXI interrupt request operation request cleared is not generated, and MPIE cleared to 0...

  • Page 265: Interrupts

    Section 14 Serial Communication Interface 3 (SCI3) 14.7 Interrupts SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 14.6 shows the interrupt sources. Table 14.6 SCI3 Interrupt Requests Interrupt Requests Abbreviation...

  • Page 266: Usage Notes

    Section 14 Serial Communication Interface 3 (SCI3) 14.8 Usage Notes 14.8.1 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RXD pin value directly. In a break, the input from the RXD pin becomes all 0s, setting the FER flag, and possibly the PER flag.

  • Page 267: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode

    Section 14 Serial Communication Interface 3 (SCI3) 14.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
  • Page 268 Section 14 Serial Communication Interface 3 (SCI3) Rev. 3.00 Sep. 14, 2006 Page 238 of 408 REJ09B0105-0300...

  • Page 269: Section 15 I C Bus Interface 2 (Iic2)

    Section 15 I C Bus Interface 2 (IIC2) Section 15 I C Bus Interface 2 (IIC2) The I C bus interface 2 conforms to and provides a subset of the Philips I C bus (inter-IC bus) interface functions. The register configuration that controls the I C bus differs partly from the Philips configuration, however.

  • Page 270: Figure 15.1 Block Diagram Of I

    Section 15 I C Bus Interface 2 (IIC2) Transfer clock generation circuit Transmit/ ICCR1 receive control circuit Output ICCR2 control ICMR Noise canceler ICDRT Output ICDRS control Address Noise canceler comparator ICDRR Bus state decision circuit Arbitration ICSR decision circuit ICIER [Legend] ICCR1:...

  • Page 271: Input/Output Pins

    Section 15 I C Bus Interface 2 (IIC2) SCL in SCL out SDA in SDA out SCL in SCL in (Master) SCL out SCL out SDA in SDA in SDA out SDA out (Slave 1) (Slave 2) Figure 15.2 External Circuit Connections of I/O Pins 15.2 Input/Output Pins Table 15.1 summarizes the input/output pins used by the I...

  • Page 272: Register Descriptions

    Section 15 I C Bus Interface 2 (IIC2) 15.3 Register Descriptions The I C bus interface 2 has the following registers. • I C bus control register 1 (ICCR1) • I C bus control register 2 (ICCR2) • I C bus mode register (ICMR) •...
  • Page 273 Section 15 I C Bus Interface 2 (IIC2) Bit Name Initial Value R/W Description Master/Slave Select Transmit/Receive Select In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode.

  • Page 274: Table 15.2 Transfer Rate

    Section 15 I C Bus Interface 2 (IIC2) Table 15.2 Transfer Rate Bit 3 Bit 2 Bit 1 Bit 0 Transfer Rate φ = 5 MHz φ = 8 MHz φ = 10 MHz Clock CKS3 CKS2 CKS1 CKS0 φ/28 179 kHz 286 kHz 357 kHz...

  • Page 275: C Bus Control Register 2 (Iccr2)

    Section 15 I C Bus Interface 2 (IIC2) 15.3.2 C Bus Control Register 2 (ICCR2) ICCR2 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in the control part of the I C bus interface 2. Bit Bit Name Initial Value R/W Description BBSY...

  • Page 276: C Bus Mode Register (Icmr)

    Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description SCLO This bit monitors SCL output level. When SCLO is 1, SCL pin outputs high. When SCLO is 0, SCL pin outputs low.   Reserved This bit is always read as 1.
  • Page 277 Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description BCWP R/W BC Write Protect This bit controls the BC2 to BC0 modifications. When modifying BC2 to BC0, this bit should be cleared to 0 and use the MOV instruction.

  • Page 278: C Bus Interrupt Enable Register (Icier)

    Section 15 I C Bus Interface 2 (IIC2) 15.3.4 C Bus Interrupt Enable Register (ICIER) ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received. Bit Bit Name Initial Value R/W Description R/W Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1, this bit enables or...
  • Page 279 Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description NAKIE R/W NACK Receive Interrupt Enable This bit enables or disables the NACK receive interrupt request (NAKI) and the overrun error (setting of the OVE bit in ICSR) interrupt request (ERI) with the clocked synchronous format, when the NACKF and AL bits in ICSR are set to 1.

  • Page 280: C Bus Status Register (Icsr)

    Section 15 I C Bus Interface 2 (IIC2) 15.3.5 C Bus Status Register (ICSR) ICSR performs confirmation of interrupt request flags and status. Bit Bit Name Initial Value R/W Description TDRE R/W Transmit Data Register Empty [Setting conditions] • When data is transferred from ICDRT to ICDRS and ICDRT becomes empty •...
  • Page 281 Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description NACKF R/W No Acknowledge Detection Flag [Setting condition] • When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 [Clearing condition] •...

  • Page 282: Slave Address Register (Sar)

    Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description R/W Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR.

  • Page 283: C Bus Transmit Data Register (Icdrt)

    Section 15 I C Bus Interface 2 (IIC2) 15.3.7 C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data.

  • Page 284: Operation

    Section 15 I C Bus Interface 2 (IIC2) 15.4 Operation The I C bus interface can communicate either in I C bus mode or clocked synchronous serial mode by setting FS in SAR. 15.4.1 C Bus Format Figure 15.3 shows the I C bus formats.

  • Page 285: Master Transmit Operation

    Section 15 I C Bus Interface 2 (IIC2) [Legend] Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0.

  • Page 286: Figure 15.5 Master Transmit Mode Operation Timing (1)

    Section 15 I C Bus Interface 2 (IIC2) (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (Master output) Slave address (Slave output) TDRE TEND ICDRT Address + R/W Data 1 Data 2 ICDRS...

  • Page 287: Master Receive Operation

    Section 15 I C Bus Interface 2 (IIC2) 15.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 15.7 and 15.8.

  • Page 288: Figure 15.7 Master Receive Mode Operation Timing (1)

    Section 15 I C Bus Interface 2 (IIC2) Master transmit mode Master receive mode (Master output) (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 (Slave output) TDRE TEND RDRF ICDRS Data 1...

  • Page 289: Slave Transmit Operation

    Section 15 I C Bus Interface 2 (IIC2) (Master output) (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Slave output) RDRF RCVD ICDRS Data n-1 Data n ICDRR Data n Data n-1 User [7] Read ICDRR,...

  • Page 290: Figure 15.9 Slave Transmit Mode Operation Timing (1)

    Section 15 I C Bus Interface 2 (IIC2) Slave transmit mode Slave receive mode (Master output) (Master output) (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 (Slave output) TDRE TEND ICDRT...

  • Page 291: Slave Receive Operation

    Section 15 I C Bus Interface 2 (IIC2) Slave receive mode Slave transmit mode (Master output) (Master output) (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Slave output) TDRE TEND ICDRT ICDRS Data n...

  • Page 292: Figure 15.11 Slave Receive Mode Operation Timing (1)

    Section 15 I C Bus Interface 2 (IIC2) 4. The last byte data is read by reading ICDRR. (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 (Master output) (Slave output) (Slave output) RDRF...

  • Page 293: Clocked Synchronous Serial Format

    Section 15 I C Bus Interface 2 (IIC2) 15.4.6 Clocked Synchronous Serial Format This module can be operated with the clocked synchronous serial format, by setting the FS bit in SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When MST is 0, the external clock input is selected.

  • Page 294: Figure 15.14 Transmit Mode Operation Timing

    Section 15 I C Bus Interface 2 (IIC2) Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 0 Bit 1 (Output) TDRE Data 1 ICDRT Data 2 Data 3 Data 1 Data 2 Data 3 ICDRS User [3] Write data [3] Write data...

  • Page 295: Noise Canceler

    Section 15 I C Bus Interface 2 (IIC2) Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 1 Bit 0 Bit 1 (Input) RDRF Data 1 Data 2 Data 3 ICDRS ICDRR Data 1 Data 2 User [2] Set MST [3] Read ICDRR...

  • Page 296: Example Of Use

    Section 15 I C Bus Interface 2 (IIC2) 15.4.8 Example of Use Flowcharts in respective modes that use the I C bus interface are shown in figures 15.17 to 15.20. Start Initialize [1] Test the status of the SCL and SDA lines. Read BBSY in ICCR2 [2] Set master transmit mode.

  • Page 297: Figure 15.18 Sample Flowchart For Master Receive Mode

    Section 15 I C Bus Interface 2 (IIC2) Mater receive mode [1] Clear TEND, select master receive mode, and then clear TDRE.* Clear TEND in ICSR [2] Set acknowledge to the transmit device.* Clear TRS in ICCR1 to 0 Clear TDRE in ICSR [3] Dummy-read ICDDR.* [4] Wait for 1 byte to be received Clear ACKBT in ICIER to 0...

  • Page 298: Figure 15.19 Sample Flowchart For Slave Transmit Mode

    Section 15 I C Bus Interface 2 (IIC2) [1] Clear the AAS flag. Slave transmit mode Clear AAS in ICSR [2] Set transmit data for ICDRT (except for the last data). [3] Wait for ICDRT empty. Write transmit data in ICDRT [4] Set the last byte of transmit data.

  • Page 299: Figure 15.20 Sample Flowchart For Slave Receive Mode

    Section 15 I C Bus Interface 2 (IIC2) Slave receive mode [1] Clear the AAS flag. Clear AAS in ICSR [2] Set acknowledge to the transmit device. Clear ACKBT in ICIER to 0 [3] Dummy-read ICDRR. Dummy-read ICDRR [4] Wait for 1 byte to be received. [5] Check whether it is the (last receive - 1).

  • Page 300: Interrupts

    Section 15 I C Bus Interface 2 (IIC2) 15.5 Interrupts There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost/overrun error. Table 15.3 shows the contents of each interrupt request. Table 15.3 Interrupt Requests Clocked Synchronous...

  • Page 301: Bit Synchronous Circuit

    Section 15 I C Bus Interface 2 (IIC2) 15.6 Bit Synchronous Circuit In master mode, this module has a possibility that high level period may be short in the two states described below. • When SCL is driven to low by the slave device •...

  • Page 302: Usage Notes

    Section 15 I C Bus Interface 2 (IIC2) 15.7 Usage Notes 15.7.1 Issue (Retransmission) of Start/Stop Conditions In master mode, when the start/stop conditions are issued (retransmitted) at the specific timing under the following condition 1 or 2, such conditions may not be output successfully. To avoid this, issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed.

  • Page 303: Section 16 A/D Converter

    Section 16 A/D Converter Section 16 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to four analog input channels to be selected. The block diagram of the A/D converter is shown in figure 16.1.

  • Page 304: Figure 16.1 Block Diagram Of A/D Converter

    Section 16 A/D Converter Internal data bus Module data bus 10-bit D/A φ /4 Control circuit φ /8 Comparator Sample-and- hold circuit interrupt request ADTRG [Legend] ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C ADDRD: A/D data register D Figure 16.1 Block Diagram of A/D Converter...

  • Page 305: Input/Output Pins

    Section 16 A/D Converter 16.2 Input/Output Pins Table 16.1 summarizes the input pins used by the A/D converter. Table 16.1 Pin Configuration Pin Name Symbol Function Analog power supply pin Input Analog block power supply pin Analog input pin 0 Input Analog input pins Analog input pin 1...

  • Page 306: A/D Control/Status Register (Adcsr)

    Section 16 A/D Converter Therefore, byte access to ADDR should be done by reading the upper byte first then the lower one. ADDR is initialized to H'0000. Table 16.2 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel A/D Data Register to Be Stored Results of A/D Conversion ADDRA ADDRB ADDRC...
  • Page 307 Section 16 A/D Converter Initial Bit Name Value Description SCAN Scan Mode Selects single mode or scan mode as the A/D conversion operating mode. 0: Single mode 1: Scan mode Clock Select Selects the A/D conversions time 0: Conversion time = 134 states (max.) 1: Conversion time = 70 states (max.) Clear the ADST bit to 0 before switching the conversion time.

  • Page 308: A/D Control Register (Adcr)

    Section 16 A/D Converter 16.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion started by an external trigger signal. Initial Bit Name Value Description TRGE Trigger Enable A/D conversion is started at the falling edge and the rising edge of the external trigger signal (ADTRG) when this bit is set to 1.

  • Page 309: Operation

    Section 16 A/D Converter 16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The ADST bit can be set at the same time as the operating mode or analog input channel is changed.

  • Page 310: Input Sampling And A/D Conversion Time

    Section 16 A/D Converter 16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (t ) has passed after the ADST bit is set to 1, then starts conversion.

  • Page 311: External Trigger Input Timing

    Section 16 A/D Converter Table 16.3 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Item Symbol Min. Typ. Max. Min. Typ. Max. A/D conversion start delay t — — Input sampling time — — — — A/D conversion time —...

  • Page 312: A/D Conversion Accuracy Definitions

    Section 16 A/D Converter 16.5 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.4). •...

  • Page 313: Figure 16.4 A/D Conversion Accuracy Definitions (1)

    Section 16 A/D Converter Digital output Ideal A/D conversion characteristic Quantization error Analog input voltage Figure 16.4 A/D Conversion Accuracy Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog Offset error input voltage Figure 16.5 A/D Conversion Accuracy Definitions (2) Rev.

  • Page 314: Usage Notes

    Section 16 A/D Converter 16.6 Usage Notes 16.6.1 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time;...

  • Page 315: Section 17 Band-Gap Circuit, Power-On Reset, And Low-Voltage Detection Circuits

    Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits This LSI can include a band-gap circuit (BGR, band-gap regulator), a power-on reset circuit and low-voltage detection circuit. BGR supplies a reference voltage to the on-chip oscillator and low-voltage detection circuit. Figure 17.1 shows the block diagram of how BGR is allocated.

  • Page 316: Features

    Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 17.1 Features • BGR circuit Supplies stable reference voltage covering the entire operating voltage range and the operating temperature range. Reduces power consumption when BGR is disabled by setting registers. •...

  • Page 317: Figure 17.2 Block Diagram Of Power-On Reset Circuit And Low-Voltage Detection Circuit

    Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits φ Internal Noise filter reset signal circuit Power-on reset circuit Noise filter circuit External power supply LVDCR Vreset LVDRES Ladder VintU network VintD ExtD LVDINT Interrupt LVDSR control circuit ExtU Interrupt request VDDII VBGR...

  • Page 318: Register Descriptions

    Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 17.2 Register Descriptions The low-voltage detection circuit has the following registers. • Low-voltage-detection control register (LVDCR) • Low-voltage-detection status register (LVDSR) 17.2.1 Low-Voltage-Detection Control Register (LVDCR) LVDCR enables or disables the low-voltage detection circuit and BGR circuit, selects the compared voltage of the LVDI circuit, sets the detection levels for the LVDR circuit, enables or disables the LVDR circuit, and enables or disables generation of an interrupt when the power- supply voltage rises above or falls below the respective levels.

  • Page 319: Table 17.1 Lvdcr Settings And Select Functions

    Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Initial Bit Name Value Description LVDSEL LVDR Detection Level Select 0: Reset detection voltage is 2.3 V (Typ.) 1: Reset detection voltage is 3.6 V (Typ.) When the falling or rising voltage detection interrupt is used, the reset detection voltage of 2.3 V (Typ.) should be used.

  • Page 320: Low-Voltage-Detection Status Register (Lvdsr)

    Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 17.2.2 Low-Voltage-Detection Status Register (LVDSR) LVDSR indicates whether the power-supply voltage falls below or rises above the respective given values. Initial Bit Name Value Description   7 to 2 All 1 Reserved These bits are always read as 1 and cannot be modified.

  • Page 321: Operations

    Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 17.3 Operations 17.3.1 Power-On Reset Circuit Figure 17.3 shows the timing of the operation of the power-on reset circuit. As the power-supply voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via the internal pull-up resistor (Typ.

  • Page 322: Low-Voltage Detection Circuit

    Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits PWON Vpor PSS-reset signal Internal reset signal 131,072 cycles PSS counter starts Reset released Figure 17.3 Operational Timing of Power-On Reset Circuit 17.3.2 Low-Voltage Detection Circuit LVDR (Reset by Low Voltage Detection) Circuit Figure 17.4 shows the timing of the operation of the LVDR circuit.

  • Page 323: Figure 17.4 Operating Timing Of Lvdr Circuit

    Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Vreset LVDRmin LVDRES PSS-reset signal Internal reset signal 131,072 cycles PSS counter starts Reset released Figure 17.4 Operating Timing of LVDR Circuit Low Voltage Detection Interrupt (LVDI) Circuit (When Internally Generated Voltage is used for Detection) Figure 17.5 shows the timing of the operation of the LVDI circuit.

  • Page 324: Figure 17.5 Operational Timing Of Lvdi Circuit

    Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits EEPROM and a transition to standby mode or subsleep mode must be made. Until this processing is completed, the power supply voltage must be higher than the lower limit of the guaranteed operating voltage.
  • Page 325 Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Low Voltage Detection Interrupt (LVDI) Circuit (When Voltages Input via ExtU and ExtD Pins are used for Detection) Figure 17.6 shows the timing of the LVDI circuit. The LVDI circuit is enabled after a power-on reset, however, the interrupt request is disabled.

  • Page 326: Figure 17.6 Operational Timing Of Lvdi Circuit (When Compared Voltage Is Input Through Extu And Extd Pins)

    Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits External power supply voltage ExtD input voltage ExtU input voltage Vexd reset1 LVDINT LVDDE LVDDF LVDUE LVDUF IRQ0 interrupt IRQ0 interrupt generated generated Figure 17.6 Operational Timing of LVDI Circuit (When Compared Voltage is Input through ExtU and ExtD Pins) Rev.

  • Page 327: Figure 17.7 Timing For Enabling/Disabling Of Low-Voltage Detection Circuit

    Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Operating Procedures for Enabling/Disabling LVDR and LVDI Circuits The low-voltage detection circuit is enabled after reset. To enable or disable the low-voltage detection circuit correctly, follow the procedure described below. Figure 17.7 shows the timing for the operation and release of the low-voltage detection circuit.
  • Page 328 Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Rev. 3.00 Sep. 14, 2006 Page 298 of 408 REJ09B0105-0300...

  • Page 329: Section 18 Power Supply Circuit

    Section 18 Power Supply Circuit Section 18 Power Supply Circuit This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external V pin.

  • Page 330: When Not Using Internal Power Supply Step-Down Circuit

    Section 18 Power Supply Circuit 18.2 When Not Using Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supply to the V pin and V pin, as shown in figure 18.2. The external power supply is then input directly to the internal power supply.

  • Page 331: Section 19 List Of Registers

    Section 19 List of Registers Section 19 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below.

  • Page 332: Register Addresses (Address Order)

    Section 19 List of Registers 19.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock. Abbre- Module Data Bus...
  • Page 333 Section 19 List of Registers Abbre- Module Data Bus Access Register Name viation Address Name Width State Timer I/O control register 0 TIOR0 H'FF84 Timer W Timer I/O control register 1 TIOR1 H'FF85 Timer W Timer counter TCNT H'FF86 Timer W General register A H'FF88 Timer W...
  • Page 334 Section 19 List of Registers Abbre- Module Data Bus Access Register Name viation Address Name Width State Timer counter WD TCWD H'FFC1 WDT* Timer mode register WD TMWD H'FFC2 WDT* Address break control register ABRKCR 8 H'FFC8 Address break Address break status register ABRKSR H'FFC9 Address break...
  • Page 335 Section 19 List of Registers Abbre- Module Data Bus Access Register Name viation Address Name Width State Interrupt flag register 1 IRR1 H'FFF6 Interrupts Interrupt flag register 2 IRR2 H'FFF7 Interrupts Wake-up interrupt flag register IWPR H'FFF8 Interrupts Module standby control register MSTCR1 H'FFF9 Power-down...

  • Page 336: Register Bits

    Section 19 List of Registers 19.2 Register Bits Register bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit registers are shown as 2 lines. Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
  • Page 337 Section 19 List of Registers Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name GRC15 GRC14 GRC13 GRC12 GRC11 GRC10 GRC9 GRC8 Timer W GRC7 GRC6 GRC5 GRC4 GRC3 GRC2 GRC1 GRC0...
  • Page 338 Section 19 List of Registers Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name ABRKCR RTINTE CSEL1 CSEL0 ACMP2 ACMP1 ACMP0 DCMP1 DCMP0 Address break ABRKSR ABIF ABIE — —...

  • Page 339: Register States In Each Operating Mode

    Section 19 List of Registers 19.3 Register States in Each Operating Mode Register Name Reset Active Sleep Subsleep Standby Module LVDCR Initialized — — — — LVDC LVDSR Initialized — — — — CKCSR Initialized — — — — Clock oscillator RCCR Initialized —...
  • Page 340 Section 19 List of Registers Register Name Reset Active Sleep Subsleep Standby Module TCSRV Initialized — — Initialized Initialized Timer V TCORA Initialized — — Initialized Initialized TCORB Initialized — — Initialized Initialized TCNTV Initialized — — Initialized Initialized TCRV1 Initialized —...
  • Page 341 Section 19 List of Registers Register Name Reset Active Sleep Subsleep Standby Module PDRC Initialized — — — — I/O port PMR1 Initialized — — — — PMR5 Initialized — — — — PCR1 Initialized — — — — PCR2 Initialized —...
  • Page 342 Section 19 List of Registers Rev. 3.00 Sep. 14, 2006 Page 312 of 408 REJ09B0105-0300...

  • Page 343: Section 20 Electrical Characteristics

    Section 20 Electrical Characteristics Section 20 Electrical Characteristics 20.1 Absolute Maximum Ratings Table 20.1 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage –0.3 to +7.0 Analog power supply voltage –0.3 to +7.0 Input voltage Ports other than port B –0.3 to V +0.3 Port B...

  • Page 344: Electrical Characteristics (F-Ztat Tm Version)

    Section 20 Electrical Characteristics 20.2 Electrical Characteristics (F-ZTAT Version) 20.2.1 Power Supply Voltage and Operating Ranges 1. Supply voltage and external oscillation frequency range φosc(MHz) 12.0 Vcc(V) AVcc = 3.0 to 5.5 V • Active mode • Sleep mode 2. Power supply voltage and operating frequency range φosc(MHz) φ(kHz) 12.0...
  • Page 345 Section 20 Electrical Characteristics 3. Analog power supply voltage and A/D converter accuracy guarantee range φosc(MHz) 12.0 AVcc(V) Vcc = 3.0 to 5.5 V • Active mode • Sleep mode Rev. 3.00 Sep. 14, 2006 Page 315 of 408 REJ09B0105-0300...

  • Page 346: Dc Characteristics

    Section 20 Electrical Characteristics 20.2.2 DC Characteristics Table 20.2 DC Characteristics (1) = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C unless otherwise indicated. Values Applicable Test Item Symbol Pins Condition Min. Typ. Max. Unit Notes RES, NMI, WKP5,...
  • Page 347 Section 20 Electrical Characteristics Values Applicable Test Item Symbol Pins Condition Min. Typ. Max. Unit Notes Output P17, P14, = 4.0 V to 5.5 V – 1.0 — — high P22 to P20, –I = 4 mA voltage P55, –I = 0.1 mA –...
  • Page 348 Section 20 Electrical Characteristics Values Applicable Test Item Symbol Pins Condition Min. Typ. Max. Unit Notes –I P17, P14, P55 = 5.0 V, 50.0 — 300.0 µA Pull-up = 0.0 V current = 3.0 V, — 60.0 — µA Reference = 0.0 V value Input...
  • Page 349 Section 20 Electrical Characteristics Values Applicable Test Item Symbol Pins Condition Min. Typ. Max. Unit Notes RAM data — — retaining voltage Note: Pin states during current consumption measurement are given below (excluding current in the pull-up MOS transistors and output buffers). RES Pin Mode Internal State...

  • Page 350: Table 20.2 Dc Characteristics (2)

    Section 20 Electrical Characteristics Table 20.2 DC Characteristics (2) = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise indicated. Values Application Test Item Symbol Pins Condition Min. Typ. Max. Unit Allowable output low Output pins except = 4.0 V to 5.5 V —...

  • Page 351: Ac Characteristics

    Section 20 Electrical Characteristics 20.2.3 AC Characteristics Table 20.3 AC Characteristics = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Test Reference Pins Condition Figure Item Symbol Min. Typ. Max. Unit System clock OSC1, OSC2 —...
  • Page 352 Section 20 Electrical Characteristics Values Applicable Test Reference Item Symbol Pins Condition Min. Typ. Max. Unit Figure On-chip oscillator = 5.0 V 7.92 8.08 oscillation frequency * Ta = 25°C FSEL = 0, VCLSEL = 0 = 4.0 V to 5.5 V 7.76 8.24 FSEL = 0,...

  • Page 353: Table 20.4 I 2 C Bus Interface Timing

    Section 20 Electrical Characteristics Table 20.4 I C Bus Interface Timing = 3.0 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Applicable Test Reference Item Symbol Pins Condition Min. Typ. Max. Unit Figure + 600 ...

  • Page 354: Table 20.5 Serial Interface (Sci3) Timing

    Section 20 Electrical Characteristics Table 20.5 Serial Interface (SCI3) Timing = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Test Reference Item Symbol Pins Condition Min. Typ. Max. Unit Figure Input Asynchro-...

  • Page 355: A/D Converter Characteristics

    Section 20 Electrical Characteristics 20.2.4 A/D Converter Characteristics Table 20.6 A/D Converter Characteristics = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Test Item Symbol Pins Condition Min. Typ. Max.

  • Page 356: Watchdog Timer Characteristics

    Section 20 Electrical Characteristics Values Applicable Test Item Symbol Pins Condition Min. Typ. Max. Unit Notes Conversion time (single = 4.0 V — — mode) to 5.5 V Nonlinearity error — — ±3.5 Offset error — — ±3.5 Full-scale error —...

  • Page 357: Power-Supply-Voltage Detection Circuit Characteristics

    Section 20 Electrical Characteristics 20.2.6 Power-Supply-Voltage Detection Circuit Characteristics Table 20.8 Power-Supply-Voltage Detection Circuit Characteristics = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Test Item Symbol Condition Min. Typ. Max. Unit Power-supply falling detection Vint(D) LVDSEL = 0 voltage Power-supply rising detection Vint(U)

  • Page 358: Power-On Reset Characteristics

    Section 20 Electrical Characteristics 20.2.8 Power-On Reset Characteristics Table 20.10 Power-On Reset Circuit Characteristics = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Test Item Symbol Condition Min. Typ. Max. Unit Pull-up resistance of RES pin — kΩ...

  • Page 359: Flash Memory Characteristics

    Section 20 Electrical Characteristics 20.2.9 Flash Memory Characteristics Table 20.11 Flash Memory Characteristics = 3.0 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Test Item Symbol Condition Min. Typ. Max. Unit Programming time (per 128 bytes)* —...
  • Page 360 Section 20 Electrical Characteristics Values Test Item Symbol Condition Min. Typ. Max. Unit Erase Wait time after SWE — — µs bit setting* Wait time after ESU — — µs bit setting* Wait time after E bit — setting* α Wait time after E bit —...

  • Page 361: Electrical Characteristics (Masked Rom Version)

    Section 20 Electrical Characteristics 20.3 Electrical Characteristics (Masked ROM Version) 20.3.1 Power Supply Voltage and Operating Ranges 1. Supply voltage and external oscillation frequency range φosc(MHz) 12.0 Vcc(V) AVcc = 2.7 to 5.5 V • Active mode • Sleep mode 2.
  • Page 362 Section 20 Electrical Characteristics 3. Analog power supply voltage and A/D converter accuracy guarantee range φosc(MHz) 12.0 AVcc(V) Vcc = 2.7 to 5.5 V • Active mode • Sleep mode Rev. 3.00 Sep. 14, 2006 Page 332 of 408 REJ09B0105-0300...

  • Page 363: Dc Characteristics

    Section 20 Electrical Characteristics 20.3.2 DC Characteristics Table 20.12 DC Characteristics (1) = 2.7 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C unless otherwise indicated. Values Applicable Test Item Symbol Pins Condition Min. Typ. Max. Unit Notes RES, NMI, WKP5,...
  • Page 364 Section 20 Electrical Characteristics Values Applicable Test Item Symbol Pins Condition Min. Typ. Max. Unit Notes Output P17, P14, = 4.0 V to 5.5 V – — — high P22 to P20, –I = 4 mA voltage P55, –I = 0.1 mA –...
  • Page 365 Section 20 Electrical Characteristics Values Applicable Test Item Symbol Pins Condition Min. Typ. Max. Unit Notes –I P17, P14, P55 = 5.0 V, 50.0 — 300.0 µA Pull-up = 0.0 V current = 2.7 V, — 60.0 — µA Reference = 0.0 V value Input...
  • Page 366 Section 20 Electrical Characteristics Values Applicable Test Item Symbol Pins Condition Min. Typ. Max. Unit Notes RAM data — — retaining voltage Note: Pin states during current consumption measurement are given below (excluding current in the pull-up MOS transistors and output buffers). RES Pin Mode Internal State...

  • Page 367: Table 20.12 Dc Characteristics (2)

    Section 20 Electrical Characteristics Table 20.12 DC Characteristics (2) = 2.7 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise indicated. Values Application Test Item Symbol Pins Condition Min. Typ. Max. Unit Allowable output low Output pins except = 4.0 V to 5.5 V —...

  • Page 368: Ac Characteristics

    Section 20 Electrical Characteristics 20.3.3 AC Characteristics Table 20.13 AC Characteristics = 2.7 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Test Reference Item Symbol Pins Condition Min. Typ. Max. Unit Figure System clock...
  • Page 369 Section 20 Electrical Characteristics Values Applicable Test Reference Item Symbol Pins Condition Min. Typ. Max. Unit Figure IRQ0, IRQ3, Input pin low width t — — Figure 20.3 WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTCI, FTIOA to FTIOD On-chip oscillator = 4.0 V to oscillation 5.5 V frequency...

  • Page 370: Table 20.14 I 2 C Bus Interface Timing

    Section 20 Electrical Characteristics Table 20.14 I C Bus Interface Timing = 2.7 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Applicable Test Reference Item Symbol Pins Condition Min. Typ. Max. Unit Figure + 600 ...

  • Page 371: Table 20.15 Serial Interface (Sci3) Timing

    Section 20 Electrical Characteristics Table 20.15 Serial Interface (SCI3) Timing = 2.7 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Test Reference Item Symbol Pins Condition Min. Typ. Max. Unit Figure Input Asynchro-...

  • Page 372: A/D Converter Characteristics

    Section 20 Electrical Characteristics 20.3.4 A/D Converter Characteristics Table 20.16 A/D Converter Characteristics = 2.7 V to 5.5 V, V = 0.0 V, T = –20°C to +75°C, unless otherwise specified. Values Applicable Test Item Symbol Pins Condition Min. Typ. Max. Unit Notes Analog power supply...

  • Page 373: Watchdog Timer Characteristics

    Section 20 Electrical Characteristics Values Applicable Test Item Symbol Pins Condition Min. Typ. Max. Unit Notes Conversion time (single = 4.0 V — — mode) to 5.5 V Nonlinearity error — — ±3.5 Offset error — — ±3.5 Full-scale error —...

  • Page 374: Power-Supply-Voltage Detection Circuit Characteristics

    Section 20 Electrical Characteristics 20.3.6 Power-Supply-Voltage Detection Circuit Characteristics Table 20.18 Power-Supply-Voltage Detection Circuit Characteristics = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Test Item Symbol Condition Min. Typ. Max. Unit Power-supply falling detection Vint(D) LVDSEL = 0 3.3 voltage Power-supply rising detection Vint(U)

  • Page 375: Power-On Reset Characteristics

    Section 20 Electrical Characteristics 20.3.8 Power-On Reset Characteristics Table 20.20 Power-On Reset Circuit Characteristics = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Test Item Symbol Condition Min. Typ. Max. Unit Pull-up resistance of RES pin — kΩ...

  • Page 376: Operation Timing

    Section 20 Electrical Characteristics 20.4 Operation Timing OSC1 Figure 20.1 System Clock Input Timing Vcc × 0.7 OSC1 Figure 20.2 RES Low Width Timing IRQ0, IRQ3 WKP5, NMI ADTRG FTCI, FTIOA FTIOB, FTIOC FTIOD TMCIV, TMRIV TRGV Figure 20.3 Input Timing Rev.

  • Page 377: Figure 20.4 I C Bus Interface Input/Output Timing

    Section 20 Electrical Characteristics STAH STOS SCLH STAS SCLL SDAS SDAH Note: * S, P, and Sr represent the following: S: Start condition P: Stop comdition Sr: Retransmission start condition Figure 20.4 I C Bus Interface Input/Output Timing SCKW SCK3 scyc Figure 20.5 SCK3 Input Clock Timing Rev.

  • Page 378: Output Load Condition

    Section 20 Electrical Characteristics scyc or V SCK3 or V (transmit data) (receive data) Note: * Output timing reference levels Output high: = 2.0 V Output low: = 0.8 V Load conditions are shown in figure 20.7. Figure 20.6 SCI3 Input/Output Timing in Clocked Synchronous Mode 20.5 Output Load Condition 2.4 kΩ...

  • Page 379: Appendix A Instruction Set

    Appendix Appendix A Instruction Set Instruction List • Operand Notation Symbol Description General (destination*) register General (source*) register General register* General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) (EAd) Destination operand (EAs)
  • Page 380 Appendix Symbol Description ( ), < > Contents of operand Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (R0 to R7 and E0 to E7). • Condition Code Notation Symbol Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1...

  • Page 381: Table A.1 Instruction Set

    Appendix Table A.1 Instruction Set • Data transfer instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation #xx:8 → Rd8 MOV.B #xx:8, Rd — — — Rs8 → Rd8 MOV.B Rs, Rd — — — @ERs →...
  • Page 382 Appendix Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation ERd32–2 → ERd32 MOV.W Rs, @–ERd — — — Rs16 → @ERd Rs16 → @aa:16 MOV.W Rs, @aa:16 — — — Rs16 → @aa:24 MOV.W Rs, @aa:24 —...
  • Page 383 Appendix • Arithmetic instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Rd8+#xx:8 → Rd8 ADD.B #xx:8, Rd — Rd8+Rs8 → Rd8 ADD.B Rs, Rd — Rd16+#xx:16 → Rd16 ADD.W #xx:16, Rd — Rd16+Rs16 → Rd16 ADD.W Rs, Rd —...
  • Page 384 Appendix Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation ERd32–1 → ERd32 DEC.L #1, ERd — — — ERd32–2 → ERd32 DEC.L #2, ERd — — — DAS.Rd Rd8 decimal adjust — — → Rd8 Rd8 ×...
  • Page 385 Appendix Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation 0–Rd8 → Rd8 NEG.B Rd — 0–Rd16 → Rd16 NEG.W Rd — 0–ERd32 → ERd32 NEG.L ERd — 0 → (<bits 15 to 8> EXTU EXTU.W Rd —...
  • Page 386 Appendix • Logic instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Rd8∧#xx:8 → Rd8 AND.B #xx:8, Rd — — — Rd8∧Rs8 → Rd8 AND.B Rs, Rd — — — Rd16∧#xx:16 → Rd16 AND.W #xx:16, Rd —...
  • Page 387 Appendix • Shift instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation SHAL.B Rd — — SHAL SHAL.W Rd — — SHAL.L ERd — — SHAR.B Rd — — SHAR SHAR.W Rd — — SHAR.L ERd —...

  • Page 388: Bit Manipulation Instructions

    Appendix • Bit manipulation instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation (#xx:3 of Rd8) ← 1 BSET #xx:3, Rd — — — — — — BSET (#xx:3 of @ERd) ← 1 BSET #xx:3, @ERd —...
  • Page 389 Appendix Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation (#xx:3 of @ERd) → C BLD #xx:3, @ERd — — — — — (#xx:3 of @aa:8) → C BLD #xx:3, @aa:8 — — — — — ¬...
  • Page 390 Appendix • Branching instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Branch Condition BRA d:8 (BT d:8) — Always — — — — — — If condition is true then BRA d:16 (BT d:16) —...
  • Page 391 Appendix Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation PC ← ERn JMP @ERn — — — — — — — PC ← aa:24 JMP @aa:24 — — — — — — — PC ← @aa:8 JMP @@aa:8 —...
  • Page 392 Appendix • System control instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation PC → @–SP TRAPA #x:2 — — — — — — TRAPA CCR → @–SP <vector> → PC CCR ← @SP+ — PC ←...
  • Page 393 Appendix • Block transfer instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation if R4L ≠ 0 then EEPMOV. B — — — — — — — EEPMOV repeat @R5 → @R6 R5+1 → R5 R6+1 →...

  • Page 394: Operation Code Map

    Appendix Operation Code Map Table A.2 Operation Code Map (1) Rev. 3.00 Sep. 14, 2006 Page 364 of 408 REJ09B0105-0300...

  • Page 395: Table A.2 Operation Code Map (2)

    Appendix Table A.2 Operation Code Map (2) Rev. 3.00 Sep. 14, 2006 Page 365 of 408 REJ09B0105-0300...

  • Page 396: Table A.2 Operation Code Map (3)

    Appendix Table A.2 Operation Code Map (3) Rev. 3.00 Sep. 14, 2006 Page 366 of 408 REJ09B0105-0300...

  • Page 397: Number Of Execution States

    Appendix Number of Execution States The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write.

  • Page 398: Table A.3 Number Of Cycles In Each Instruction

    Appendix Table A.3 Number of Cycles in Each Instruction Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module Instruction fetch — Branch address read Stack operation Byte data access 2 or 3* Word data access 2 or 3* Internal operation Note: Depends on which on-chip peripheral module is accessed.

  • Page 399: Table A.4 Number Of Cycles In Each Instruction

    Appendix Table A.4 Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS ADDS #1/2/4, ERd...
  • Page 400 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BLT d:8 BGT d:8 BLE d:8 BRA d:16(BT d:16) BRN d:16(BF d:16) BHI d:16 BLS d:16 BCC d:16(BHS d:16) BCS d:16(BLO d:16) BNE d:16 BEQ d:16 BVC d:16...
  • Page 401 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BIOR BIOR #xx:8, Rd BIOR #xx:8, @ERd BIOR #xx:8, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8 BLD #xx:3, Rd...
  • Page 402 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BTST BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 CMP.B #xx:8, Rd...
  • Page 403 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic INC.B Rd INC.W #1/2, Rd INC.L #1/2, ERd JMP @ERn JMP @aa:24 JMP @@aa:8 JSR @ERn JSR @aa:24 JSR @@aa:8 LDC #xx:8, CCR LDC Rs, CCR LDC@ERs, CCR LDC@(d:16, ERs), CCR...
  • Page 404 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd MOV.W @(d:16,ERs), Rd MOV.W @(d:24,ERs), Rd MOV.W @ERs+, Rd MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd...
  • Page 405 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd MULXU MULXU.B Rs, Rd MULXU.W Rs, ERd NEG.B Rd NEG.W Rd NEG.L ERd NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8, Rd...
  • Page 406 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd SHAL SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd...
  • Page 407 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic SUBX SUBX #xx:8, Rd SUBX. Rs, Rd TRAPA TRAPA #xx:2 XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd XORC...

  • Page 408: Combinations Of Instructions And Addressing Modes

    Appendix Combinations of Instructions and Addressing Modes Table A.5 Combinations of Instructions and Addressing Modes Addressing Mode Functions Instructions Data — — — — transfer POP, PUSH — — — — — — — — — — — — instructions MOVFPE, —...

  • Page 409: Appendix B I/O Port Block Diagrams

    Appendix Appendix B I/O Port Block Diagrams I/O Port Block Diagrams RES goes low in a reset, and SBY goes low in a reset and in standby mode. Internal data bus PUCR Pull-up MOS TRGV [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR:...

  • Page 410: Figure B.2 Port 1 Block Diagram (P14)

    Appendix Internal data bus PUCR Pull-up MOS [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.2 Port 1 Block Diagram (P14) Rev. 3.00 Sep. 14, 2006 Page 380 of 408 REJ09B0105-0300...

  • Page 411: Figure B.3 Port 2 Block Diagram (P22)

    Appendix Internal data bus SCI3 [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.3 Port 2 Block Diagram (P22) Rev. 3.00 Sep. 14, 2006 Page 381 of 408 REJ09B0105-0300...

  • Page 412: Figure B.4 Port 2 Block Diagram (P21)

    Appendix Internal data bus SCI3 [Legend] PDR: Port data register PCR: Port control register Figure B.4 Port 2 Block Diagram (P21) Rev. 3.00 Sep. 14, 2006 Page 382 of 408 REJ09B0105-0300...

  • Page 413: Figure B.5 Port 2 Block Diagram (P20)

    Appendix SCI3 SCKIE SCKOE Internal data bus SCKO SCKI [Legend] PDR: Port data register PCR: Port control register Figure B.5 Port 2 Block Diagram (P20) Rev. 3.00 Sep. 14, 2006 Page 383 of 408 REJ09B0105-0300...

  • Page 414: Figure B.6 (1) Port 5 Block Diagram (P57, P56) (For H8/36912 Group)

    Appendix Internal data bus IIC2 SDAO/SCLO SDAI/SCLI [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.6 (1) Port 5 Block Diagram (P57, P56) (for H8/36912 Group) Rev. 3.00 Sep. 14, 2006 Page 384 of 408 REJ09B0105-0300...

  • Page 415: Figure B.6 (2) Port 5 Block Diagram (P57, P56) (For H8/36902 Group)

    Appendix Internal data bus [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.6 (2) Port 5 Block Diagram (P57, P56) (for H8/36902 Group) Rev. 3.00 Sep. 14, 2006 Page 385 of 408 REJ09B0105-0300...

  • Page 416: Figure B.7 Port 5 Block Diagram (P55)

    Appendix Internal data bus PUCR Pull-up MOS ADTRG [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.7 Port 5 Block Diagram (P55) Rev. 3.00 Sep. 14, 2006 Page 386 of 408 REJ09B0105-0300...

  • Page 417: Figure B.8 Port 5 Block Diagram (P76)

    Appendix Internal data bus Timer V TMOV [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.8 Port 5 Block Diagram (P76) Rev. 3.00 Sep. 14, 2006 Page 387 of 408 REJ09B0105-0300...

  • Page 418: Figure B.9 Port 7 Block Diagram (P75)

    Appendix Internal data bus Timer V TMCIV [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.9 Port 7 Block Diagram (P75) Rev. 3.00 Sep. 14, 2006 Page 388 of 408 REJ09B0105-0300...

  • Page 419: Figure B.10 Port 7 Block Diagram (P74)

    Appendix Internal data bus Timer V TMRIV [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.10 Port 7 Block Diagram (P74) Rev. 3.00 Sep. 14, 2006 Page 389 of 408 REJ09B0105-0300...

  • Page 420: Figure B.11 Port 8 Block Diagram (P84 To P81)

    Appendix Internal data bus Timer W Output control signal A to D FTIOA to D [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.11 Port 8 Block Diagram (P84 to P81) Rev. 3.00 Sep. 14, 2006 Page 390 of 408 REJ09B0105-0300...

  • Page 421: Figure B.12 Port 8 Block Diagram (P80)

    Appendix Internal data bus Timer W FTCI [Legend] Portdata register PDR: PCR: Portcontrol register Figure B.12 Port 8 Block Diagram (P80) Rev. 3.00 Sep. 14, 2006 Page 391 of 408 REJ09B0105-0300...

  • Page 422: Figure B.13 Port B Block Diagram (Pb3, Pb2)

    Appendix Internal data bus A/D converter CH3 to CH0 SCAN Low voltage detection circuit VDDII ExtD, ExtU [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.13 Port B Block Diagram (PB3, PB2) Internal data bus A/D converter SCAN CH3 to CH0 Figure B.14 Port B Block Diagram (PB1, PB0) Rev.

  • Page 423: Figure B.15 Port C Block Diagram (Pc1)

    Appendix Internal data bus φ PMRC1 PMRC0 XTALI [Legend] Portdata register PDR: PCR: Portcontrol register Figure B.15 Port C Block Diagram (PC1) Rev. 3.00 Sep. 14, 2006 Page 393 of 408 REJ09B0105-0300...

  • Page 424: Port States In Each Operating State

    Appendix Internal data bus PMRC0 EXTALI [Legend] PDR: Portdata register PCR: Portcontrol register Figure B.16 Port C Block Diagram (PC0) Port States in Each Operating State Port Reset Active Sleep Subsleep Standby P17, P14 High impedance Functioning Retained Retained High impedance* P22 to P20 High impedance Functioning...

  • Page 425: Appendix C Product Code Lineup

    Appendix Appendix C Product Code Lineup Product Type Product Code Model Marking Package Code H8/36912 Flash memory HD64F36912G HD64F36912GFH LQFP-32 (FP-32A) version HD64F36912GTP SOP-32 (FP-32D) HD64F36912GP SDIP-32 (32P4B) Masked ROM HD64336912G HD64336912G (***) FH LQFP-32 (FP-32A) version HD64336912G (***) TP SOP-32 (FP-32D) H8/36911 Masked ROM HD64336911G...

  • Page 426: Appendix D Package Dimensions

    Appendix Appendix D Package Dimensions The package dimensions that are shows in the Renesas Semiconductor Packages Data Book have priority. Unit: mm 20.45 20.95 Max 14.14 ± 0.30 1.00 Max 1.42 0 ˚ – 8 ˚ 0.10 0.80 ± 0.20 1.27...

  • Page 427: Figure D.2 Fp-32A Package Dimension

    Appendix Unit: mm 9.0 ± 0.2 0.70 * 0.35 ± 0.05 0 .20 M 0.37 ± 0.05 1. 0 0 ~ 10˚ 0.5 ± 0.1 0.10 Package Code FP-32A FP-32AV — JEDEC *Dimension including the plating thickness Base material dimension JEITA —...

  • Page 428: Figure D.3 32P4B Package Dimension

    Appendix Unit: mm SEATING PLANE Dimension in Millmeters Symbol − − 5.08 − − 0.51 − − 0.35 0.45 0.55 0.63 0.73 1.03 0.22 0.27 0.34 27.8 28.0 28.2 8.75 9.05 − − 1.778 Package Code 32P4B − − 10.16 JEDEC —...

  • Page 429: Main Revisions And Additions In This Edition

    Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details)  When using an on-chip emulator (E7, E8) for H8/36912, Preface H8/36902 program development and debugging, the following restrictions must be noted. 1. The NMI pin is reserved for the E7 or E8, and cannot be used.
  • Page 430 Item Page Revision (See Manual for Details) Figure 1.1 Internal Block 3, 4 Diagram of H8/36912 Group E10T_0 * E10T_1 * E10T_2 * System Figure 1.2 Internal Block On-chip clock H8/300H oscillator generator Diagram of H8/36902 Group Data bus (lower) Port C Port B Note: * Can also be used for the E7 or E8 emulator.
  • Page 431 Item Page Revision (See Manual for Details) Figure 2.1 Memory Map (2) H8/36911 H8/36901 H8/36900 (Masked ROM version (Masked ROM version (under planning)) (under planning)) H'0000 H'0000 Interrupt vector Interrupt vector H'0045 H'0045 H'0046 H'0046 Table 3.1 Exception Sources Relative Module Exception Sources and Vector Address IIC2*...
  • Page 432 Item Page Revision (See Manual for Details) 5.2.3 RC Trimming Data Bit Name Description Register (RCTRMDR) TRMD7 Trimming Data TRMD6 In the flash memory version, the trimming data is loaded from the flash memory to this TRMD5 register right after a reset. These bits are TRMD4 always read as undefined value.
  • Page 433 Item Page Revision (See Manual for Details) 13.2.1 Timer Control/Status Bit Name Description Register WD (TCSRWD) TCSRWE Timer Control/Status Register WD Write Enable The WDON and WRST bits can be written when the TCSRWE bit is set to 1. When writing data to this bit, the value for bit 5 must be 0.
  • Page 434 Item Page Revision (See Manual for Details) Table 20.13 AC Values Characteristics Item Symbol Min. Typ. Max. On-chip oscillator oscillation frequency 10.0 10.6 Table A.1 Instruction Set Addressing Mode and No. of Instruction Length (bytes) States • Arithmetic instructions Mnemonic Operation Condition Code Rd8+#xx:8 →...

  • Page 435: Index

    Index Exception handling ........47 Reset exception handling ...... 54 A/D converter ......... 273 Stack status ........... 58 A/D conversion time......280 Trap instruction........47 External trigger input......281 Sample-and-hold circuit...... 280 Scan mode........... 279 Single mode ........279 Acknowledge .......... 255 Flash memory ...........
  • Page 436 Shift Instructions ........25 Power-down modes........85 System control instructions....29 Sleep mode..........93 Internal power supply step-down Standby mode ........93 circuit............299 Subsleep mode ........94 Interrupt Power-on reset ........285 Internal interrupts ......... 56 Power-on reset circuit ......291 Interrupt response time ......
  • Page 437 ICMR......246, 302, 306, 309 TCORB ....... 148, 303, 307, 310 ICSR ......250, 302, 306, 309 TCRV0......148, 303, 307, 309 IEGR1......49, 304, 308, 311 TCRV1......151, 303, 307, 310 IEGR2......50, 304, 308, 311 TCRW......164, 302, 306, 309 IENR1......
  • Page 438 Timer B1..........139 Auto-reload timer operation ....142 Vector address........... 47 Interval timer operation ...... 142 Timer V ..........145 Timer W ..........159 Transfer Rate .......... 244 Watchdog timer........191 Rev. 3.00 Sep. 14, 2006 Page 408 of 408 REJ09B0105-0300...
  • Page 439 Publication Date: Rev.1.00, Nov. 07, 2003 Rev.3.00, Sep. 14, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.  2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
  • Page 440 Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
  • Page 442 H8/36912 Group, H8/36902 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0105-0300...

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