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Contention between General Register Write and Compare Match: If a compare match occurs
in the T
state of a general register write cycle, writing takes priority and the compare match signal
3
is inhibited. See figure 9.40.
φ
Address bus
Internal write signal
TCNT
GR
Compare match signal
Figure 9.40 Contention between General Register Write and Compare Match
General register write cycle
T
T
1
2
GR address
N
N
General register write data
Rev. 4.00 Jan 26, 2006 page 387 of 938
Section 9 16-Bit Timer
T
3
N + 1
M
Inhibited
REJ09B0276-0400
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