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Section 19 Clock Pulse Generator
19.3
Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate φ.
19.4
Prescalers
The prescalers divide the system clock (φ) to generate internal clocks (φ/2 to φ/4096).
19.5
Frequency Divider
The frequency divider divides the duty-adjusted clock signal to generate the system clock (φ). The
frequency division ratio can be changed dynamically by modifying the value in DIVCR, as
described below. Power consumption in the chip is reduced in almost direct proportion to the
frequency division ratio. The system clock generated by the frequency divider can be output at the
φ pin.
19.5.1
Register Configuration
Table 19.4 summarizes the frequency division register.
Table 19.4 Frequency Division Register
Address*
Name
H'EE01B
Division control register
Note: * Lower 20 bits of the address in advanced mode.
Rev. 4.00 Jan 26, 2006 page 672 of 938
REJ09B0276-0400
Abbreviation
R/W
DIVCR
R/W
Initial Value
H'FC
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