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Section 4 Exception Handling
φ
RES
Address bus
RD
HWR
,
LWR
D
to D
15
0
(1), (3)
Address of reset vector: (1) = H'000000, (3) = H'000002
(2), (4)
Start address (contents of reset exception handling vector address)
(5)
Start address
(6)
First instruction of program
Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Rev. 4.00 Jan 26, 2006 page 84 of 938
REJ09B0276-0400
Vector fetch
(1)
High
(2)
Figure 4.3 Reset Sequence (Modes 2 and 4)
Internal
processing
(3)
(4)
Prefetch of first
program instruction
(5)
(6)
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