Dmac Timing - Renesas H8/3067 Series User Manual

Renesas 16-bit single-chip microcomputer
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21.3.8

DMAC Timing

DMAC timing is shown as follows.
• DMAC TEND output timing for 2 state access
Figure 21.25 shows the DMAC TEND output timing for 2 state access.
• DMAC TEND output timing for 3 state access
Figure 21.26 shows the DMAC TEND output timing for 3 state access.
• DMAC DREQ input timing
Figure 21.27 shows DMAC DREQ input timing.
φ
TEND
Figure 21.25 DMAC TEND
φ
t
TED1
TEND
Figure 21.26 DMAC TEND
T
1
t
TED1
TEND Output Timing for 2 State Access
TEND
TEND
T
1
TEND Output Timing for 3 State Access
TEND
TEND
φ
t
DRQS
DREQ
Figure 21.27 DMAC DREQ
Section 21 Electrical Characteristics
T
2
T
T
2
3
t
DRQH
DREQ Input Timing
DREQ
DREQ
Rev. 4.00 Jan 26, 2006 page 751 of 938
t
TED2
t
TED2
REJ09B0276-0400

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