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SYSCR—System Control Register
7
Bit
SSBY
STS2
Initial value
0
Read/Write
R/W
Standby timer select 2 to 0
Bit 6
STS2
0
1
Software standby
0
SLEEP instruction causes transition to sleep mode
1
SLEEP instruction causes transition to software standby mode
6
5
4
STS1
STS0
0
0
0
R/W
R/W
R/W
User bit enable
0
CCR bit 6 (UI) is used as an interrupt mask bit
1
CCR bit 6 (UI) is used as a user bit
Bit 5
Bit 4
STS1
STS0
Waiting Time = 8,192 states
0
0
Waiting Time = 16,384 states
1
0
Waiting Time = 32,768 states
1
1
Waiting Time = 65,536 states
Waiting Time = 131,072 states
0
0
Waiting Time = 26,2144 states
1
0
Waiting Time = 1,024 states
1
Illegal setting
1
Appendix B Internal I/O Registers
H'EE012
3
2
1
UE
NMIEG
SSOE
1
0
0
R/W
R/W
R/W
RAM enable
Software standby output port enable
0
1
NMI edge select
0
An interrupt is requested at the falling edge of NMI
1
An interrupt is requested at the rising edge of NMI
Standby Timer
Rev. 4.00 Jan 26, 2006 page 797 of 938
System control
0
RAME
1
R/W
0
On-chip RAM is disabled
1
On-chip RAM is enabled
In software standby mode,
all address bus and bus
control signals are high-
impedance
In software standby mode,
address bus retains output
state and bus control
signals are fixed high
REJ09B0276-0400
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