System Control Register (Syscr) - Renesas H8SX/1650 Hardware Manual

Section 3 MCU Operating Modes
3.2.2

System Control Register (SYSCR)

SYSCR controls MAC saturation operation, selects bus width mode for instruction fetch, sets
external bus mode, enables/disables the on-chip RAM, and selects the DTC address mode.
Bit 15

Bit Name
Initial Value 1
R/W R/W
Bit 7

Bit Name
Initial Value 0
R/W R/W
Note: * The initial value depends on the startup mode.
Bit Bit Name

15, 14
13 MACS

12
11 FETCHMD 0
Rev.2.00 Jun. 28, 2007 Page 64 of 666
REJ09B0311-0200
14 13

MACS
1 0
R/W R/W
6 5
 
0 0
R/W R/W
Initial
Value R/W Descriptions
All 1 R/W Reserved
These bits are always read as 1. The write value should
always be 1.
0 R/W MAC Saturation Operation Control
Selects either saturation operation or non-saturation
operation for the MAC instruction.
0: MAC instruction is non-saturation operation
1: MAC instruction is saturation operation
1 R/W Reserved
This bit is always read as 1. The write value should
always be 1.
R/W Instruction Fetch Mode Select
The H8SX CPU has two modes for instruction fetch: 16-
bit and 32-bit modes. It is recommended that the mode
should be set according to the bus width of the memory in
which the program is stored*
0: 32-bit width
1: 16-bit width
12 11

FETCHMD
1 0
R/W R/W
4 3
 
0 0
R/W R/W
10 9

EXPE RAME
0 Undefined*
R/W R/W
2 1

DTCMD
0 1
R/W R/W
1
.
8
1
R/W
0

1
R/W