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Appendix B Internal I/O Registers
FLMSR-Flash Memory Status Register
Bit
7
FLER
Initial value
0
R/W
R
RAM select, RAM2, RAM1
Bit 7
FLER
0
Flash memory program/erase protection (error protection) is disabled (Initial value)
[Clearing condition]
WDT reset, reset via the RES pin or hardware standby mode
1
An error has occurred during flash memory programming/erasing, and error pro-
tection*
[Setting conditions]
1. Flash memory was read*
2. A hardware exception-handling sequence (other than a reset, invalid instruction,
3. The SLEEP instruction (including software standby mode) was executed during
Notes 1.
See 18.6.3, Error Protection, for details.
2.
The read value in this case is undefined.
3.
Before stack and vector read by exception handling.
Note: This register is used only in the flash memory and flash memory R versions. Reading the
corresponding address in a mask ROM version will always return 1s, and writes to this address
are disabled.
Rev. 4.00 Jan 26, 2006 page 816 of 938
REJ09B0276-0400
6
5
1
1
1
is enabled
or instruction fetch, but not including reading of a RAM area overlapped onto
flash memory).
trap instruction, or zero-divide exception) was executed just before programming
3
or erasing.*
programming or erasing.
H'EE07D
4
3
2
1
1
1
Reserved bits
Description
2
while being programmed or erased (including vector
Flash Memory
1
0
1
1
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