Table of Contents
Advertisement
Section 10 8-Bit Timers
Bit 4—A/D Trigger Enable (ADTE) (TCSR0): In combination with TRGE in the A/D control
register (ADCR), enables or disables A/D converter start requests by compare match A or an
external trigger. TCSR2 is a reserved bit, but can be read and written.
Bit 4
TRGE*
ADTE
Description
0
0
A/D converter start requests by compare match A or an external trigger are
disabled
1
A/D converter start requests by compare match A or an external trigger are
disabled
1
0
A/D converter start requests by an external trigger are enabled, and A/D
converter start requests by compare match A are disabled
1
A/D converter start requests by compare match A are enabled, and A/D
converter start requests by an external trigger are disabled
Note: * TRGE is bit 7 of the A/D control register (ADCR).
Bit 4—Input Capture Enable (ICE) (TCSR1, TCSR3): Selects the function of TCORB.
Bit 4
ICE
Description
0
TCORB is a compare match register
1
TCORB is an input capture register
Rev. 4.00 Jan 26, 2006 page 410 of 938
REJ09B0276-0400
(Initial value)
(Initial value)
Advertisement
Table of Contents
