Table of Contents
Advertisement
8.3
Port 2
8.3.1
Overview
Port 2 is an 8-bit input/output port with the pin configuration shown in figure 8.2. The pin
functions differ according to the operating mode.
In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 2 consists of address bus
output pins (A
to A
). In modes 5 (expanded modes with on-chip ROM enabled), settings in the
15
8
port 2 data direction register (P2DDR) can designate pins for address bus output (A
generic input. In mode 6 and 7 (single-chip mode), port 2 is a generic input/output port.
When DRAM is connected to areas 2 to 5, A
write cycles. For details see section 6.5, DRAM Interface.
Port 2 has software-programmable built-in pull-up transistors.
Pins in port 2 can drive one TTL load and a 90-pF capacitive load. They can also drive an LED or
a darlington transistor pair.
Port 2 pins
Port 2
Modes 1 to 4
P2 /A
A
(output)
7
15
15
P2 /A
A
(output)
6
14
14
P2 /A
A
(output)
5
13
13
P2 /A
A
(output)
4
12
12
P2 /A
A
(output)
3
11
11
P2 /A
A
(output)
2
10
10
P2 /A
A (output)
1
9
9
P2 /A
A (output)
0
8
8
Figure 8.2 Port 2 Pin Configuration
to A
output row and column addresses in read and
12
8
Modes 5
P2 (input)/A
7
15
P2 (input)/A
6
14
P2 (input)/A
5
13
P2 (input)/A
4
12
P2 (input)/A
3
11
P2 (input)/A
2
10
P2 (input)/A
1
9
P2 (input)/A
0
8
Rev. 4.00 Jan 26, 2006 page 275 of 938
Section 8 I/O Ports
to A
15
Mode 6 and 7
(output)
P2 (input/output)
7
(output)
P2 (input/output)
6
(output)
P2 (input/output)
5
(output)
P2 (input/output)
4
(output)
P2 (input/output)
3
(output)
P2 (input/output)
2
(output)
P2 (input/output)
1
(output)
P2 (input/output)
0
REJ09B0276-0400
) or
8
Advertisement
Table of Contents
