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9.4.5
Phase Counting Mode
In phase counting mode the phase difference between two external clock inputs (at the TCLKA
and TCLKB pins) is detected, and TCNT2 counts up or down accordingly.
In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock
input pins and TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to
TPSC0, CKEG1, and CKEG0 in TCR2. Settings of bits CCLR1, CCLR0 in TCR2, and settings in
TIOR2, TISRA, TISRB, TISRC, STR2 in TSTR, GRA2, and GRB2 are valid. The input capture
and output compare functions can be used, and interrupts can be generated.
Phase counting is available only in channel 2.
Sample Setup Procedure for Phase Counting Mode: Figure 9.29 shows a sample procedure for
setting up phase counting mode.
Phase counting mode
Select phase counting mode
Select flag setting condition
Start counter
Phase counting mode
Figure 9.29 Setup Procedure for Phase Counting Mode (Example)
1
1.
Set the MDF bit in TMDR to 1 to select
phase counting mode.
2.
Select the flag setting condition with
the FDIR bit in TMDR.
3.
Set the STR2 bit to 1 in TSTR to start
the timer counter.
2
3
Rev. 4.00 Jan 26, 2006 page 377 of 938
Section 9 16-Bit Timer
REJ09B0276-0400
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