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ADDRC H/L—A/D Data Register C H/L
15
Bit
AD9
Initial value
0
Read/Write
R
ADDRD H/L—A/D Data Register D H/L
15
Bit
AD9
Initial value
0
Read/Write
R
ADCR—A/D Control Register
Bit
TRGE
Initial value
Read/Write
14
13
12
11
10
AD8
AD7
AD6
AD5
AD4
0
0
0
0
0
R
R
R
R
R
ADDRCH
A/D conversion data
10-bit data giving an A/D conversion result
14
13
12
11
10
AD8
AD7
AD6
AD5
AD4
0
0
0
0
0
R
R
R
R
R
ADDRDH
A/D conversion data
10-bit data giving an A/D conversion result
7
6
5
0
1
1
R/W
Trigger Enable
A/D conversion start by external trigger or 8-bit timer
0
compare match is disabled
A/D conversion is started by falling edge of external
1
trigger signal (ADTRG) or 8-bit timer compare match
Appendix B Internal I/O Registers
H'FFFE4, H'FFFE5
9
8
7
6
5
AD3
AD2
AD1
AD0
0
0
0
0
0
R
R
R
R
R
H'FFFE6, H'FFFE7
9
8
7
6
5
AD3
AD2
AD1
AD0
0
0
0
0
0
R
R
R
R
R
H'FFFE9
4
3
2
1
1
1
Rev. 4.00 Jan 26, 2006 page 877 of 938
4
3
2
1
0
0
0
0
0
0
R
R
R
R
R
ADDRCL
4
3
2
1
0
0
0
0
0
0
R
R
R
R
R
ADDRDL
1
0
1
0
R/W
REJ09B0276-0400
A/D
A/D
A/D
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