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Table 9.7 (c) 16-bit timer Operating Modes (Channel 2)
Operating Mode
Synchronous preset
PWM mode
Output compare A
Output compare B
Input capture A
Input capture B
Counter By compare
clearing match/input
capture A
By compare
match/input
capture B
Syn-
chronous
clear
Phase counting
mode
Setting available (valid). Setting does not affect this mode.
Legend:
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur
simultaneously, the compare match signal is inhibited.
TSNC
TMDR
Synchro-
nization
MDF
FDIR PWM
SYNC2 = 1
SYNC2 = 1
MDF = 1
Register Settings
TIOR2
IOA
IOB
PWM2 = 1
PWM2 = 0
IOA2 = 0
Other bits
unrestricted
IOB2 = 0
Other bits
unrestricted
PWM2 = 0
IOA2 = 1
Other bits
unrestricted
PWM2 = 0
IOB2 = 1
Other bits
unrestricted
Rev. 4.00 Jan 26, 2006 page 395 of 938
Section 9 16-Bit Timer
TCR2
Clear
Clock
Select
Select
*
CCLR1 = 0
CCLR0 = 1
CCLR1 = 1
CCLR0 = 0
CCLR1 = 1
CCLR0 = 1
REJ09B0276-0400
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