Renesas H8/3067 Series User Manual page 200

Section 6 Bus Controller
Table 6.9 Correspondence between Settings of MXC1 and MXC0 Bits and ABWCR, and
Row Address Compared in Burst Access
Operating Mode MXC1
Modes 1 and 2 0
(1-Mbyte)
1
Modes 3, 4, and 5 0
(16-Mbyte)
1
Note: n = 2 to 5
RAS Down Mode and RAS Up Mode: With DRAM provided with fast page mode, as long as
accesses are to the same row address, burst operation can be continued without interruption even if
accesses are not consecutive by holding the RAS signal low.
• RAS Down Mode
To select RAS down mode, set the BE and RDM bits to 1 in DRCRA. If access to DRAM
space is interrupted and another space is accessed, the RAS signal is held low during the
access to the other space, and burst access is performed if the row address of the next DRAM
space access is the same as the row address of the previous DRAM space access. Figure 6.23
shows an example of the timing in RAS down mode.
Rev. 4.00 Jan 26, 2006 page 176 of 938
REJ09B0276-0400
DRCRB ABWCR
MXC0 ABWn
0 0
1
1 0
1
0 0
1
1 —
0 0
1
1 0
1
0 0
1
1 —
Bus Width Compared Row Address
16 bits A19 to A9
8 bits A19 to A8
16 bits A19 to A10
8 bits A19 to A9
16 bits A19 to A11
8 bits A19 to A10
— Illegal setting
16 bits A23 to A9
8 bits A23 to A8
16 bits A23 to A10
8 bits A23 to A9
16 bits A23 to A11
8 bits A23 to A10
— Illegal setting