Renesas H8/3067 Series User Manual page 609

(1)
φ
(2)
Address bus
Write signal
Input sampling
timing
ADF
Legend
(1): ADCSR write cycle
(2): ADCSR address
t : Synchronization delay
D
t : Input sampling time
SPL
t : A/D conversion time
CONV
Table 15.4 A/D Conversion Time (Single Mode)
Synchronization delay
Input sampling time
A/D conversion time
Note: Values in the table are numbers of states.
t t
D SPL
Figure 15.5 A/D Conversion Timing
Symbol
t
D
t
SPL
t
CONV
t
CONV
CKS = 0
Min Typ Max
6 — 9
— 31 —
131 — 134
Rev. 4.00 Jan 26, 2006 page 585 of 938
Section 15 A/D Converter
CKS = 1
Min Typ Max
4 — 5
— 15 —
69 — 70
REJ09B0276-0400