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Mode 5: Figure D.3 is a timing diagram for the case in which RES goes low during an external
memory access in mode 5. As soon as RES goes low, all ports are initialized to the input state. AS,
RD, HWR, and LWR go high, and the address bus and D
/φ goes to the output state at the next rise of φ after RES goes low.
Clock pin P6
7
P6
/φ
7
RES
Internal reset
signal
A
to A
23
0
AS, RD
(read)
HWR, LWR
(write)
D
to D
15
0
(write)
I/O port,
CS
to CS
7
1
Access to external
memory
T1
Figure D.3 Reset during Memory Access (Mode 5)
to D
go to the high-impedance state.
15
0
T2
T3
Rev. 4.00 Jan 26, 2006 page 923 of 938
Appendix D Pin States
High impedance
High impedance
High impedance
REJ09B0276-0400
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