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Section 17 RAM
17.2
System Control Register (SYSCR)
Bit
7
SSBY
Initial value
0
Read/Write
R/W
Software standby
One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is
enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3,
System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized at the rising edge of the input at the RES pin. It is not initialized in software standby
mode.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
Rev. 4.00 Jan 26, 2006 page 604 of 938
REJ09B0276-0400
6
5
STS2
STS1
STS0
0
0
R/W
R/W
R/W
Standby timer select 2 to 0
4
3
2
UE
NMIEG
0
1
0
R/W
R/W
NMI edge select
User bit enable
1
0
SSOE
RAME
0
1
R/W
R/W
RAM enable bit
Enables or
disables
on-chip RAM
Software standby
output port enable
(Initial value)
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