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Section 7 DMA Controller
MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or
destination address, which is incremented or decremented as each byte or word is transferred.
IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not
incremented or decremented.
Figure 7.2 illustrates how I/O mode operates.
Address T
Address B
Legend
L = initial setting of MAR
N = initial setting of ETCR
Address T = L
Address B = L + (−1)
The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at
each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared and the transfer ends.
If the DTIE bit is set to 1, a CPU interrupt is requested at this time. The maximum transfer count
is 65,536, obtained by setting ETCR to H'0000.
Rev. 4.00 Jan 26, 2006 page 232 of 938
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1 byte or word is
transferred per request
• (2
• N − 1)
DTID
DTSZ
Figure 7.2 Operation in I/O Mode
Transfer
IOAR
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