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DRCRB—DRAM Control Register B
Bit
Initial value
Read/Write
7
6
5
MXC1
MXC0
CSEL
RCYCE
0
0
0
R/W
R/W
R/W
R/W
Refresh cycle wait control
0
1
RAS-CAS wait
0
Wait state (T
1
1 wait state (T
TP cycle control
0
1-state precharge cycle is inserted
1
2-state precharge cycle is inserted
Refresh cycle enable
0
Refresh cycles are disabled
1
DRAM refresh cycles are enabled
CAS output pin select
PB4 and PB5 selected as UCAS and LCAS output pins
0
HWR and LWR selected as UCAS and LCAS output pins
1
Multiplex control 1 and 0
MXC1
MXC0
0
Column address: 8 bits
0
Compared address:
Modes 1, 2
Modes 3, 4, 5
Column address: 9 bits
1
Compared address:
Modes 1, 2
Modes 3, 4, 5
Column address: 10 bits
1
0
Compared address:
Modes 1, 2
Modes 3, 4, 5
1
Illegal setting
Appendix B Internal I/O Registers
H'EE027
4
3
2
1
TPC
RCW
0
1
0
0
R/W
R/W
Wait state (T
) insertion is disabled
RW
1 wait state (T
) is inserted
RW
) insertion is disabled
rw
) is inserted
rw
Description
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
Rev. 4.00 Jan 26, 2006 page 809 of 938
DRAM interface
0
RLW
0
R/W
A
to A
19
8
A
to A
19
9
A
to A
23
8
A
to A
23
9
A
to A
19
9
A
to A
19
10
A
to A
23
9
A
to A
23
10
A
to A
19
10
A
to A
19
11
A
to A
23
10
A
to A
23
11
REJ09B0276-0400
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