Hardware
standby
PB
5
WPBD:
Write to PBDDR
WPB:
Write to port B
RPB:
Read port B
SSOE:
Software standby output port enable
Note: In modes 6 and 7, CAS output enable is fixed at 0.
Figure C.11 (f) Port B Block Diagram (Pin PB
Appendix C I/O Port Block Diagrams
External bus release
Software standby
SSOE
Reset
R
Q
D
PB
DDR
5
C
WPBD
Reset
R
Q
D
PB
DR
5
C
WPB
RPB
Rev. 4.00 Jan 26, 2006 page 911 of 938
SCI
Clock input
enable
TPC
TPC output enable
Next data
Output trigger
Bus controller
CAS output enable
CAS output
SCI
Clock output
enable
Clock output
Clock input
)
5
REJ09B0276-0400