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6.6
Interval Timer
6.6.1
Operation
When DRAM is not connected to the H8/3067 Group chip, the refresh timer can be used as an
interval timer by clearing bits DRAS2 to DRAS0 in DRCRA to 0. After setting RTCOR, selection
a clock source with bits CKS2 to CKS0 in RTMCSR, and set the CMIE bit to 1.
Timing of Setting of Compare Match Flag and Clearing by Compare Match: The CMF flag
in RTMCSR is set to 1 by a compare match output when the RTCOR and RTCNT values match.
The compare match signal is generated in the last state in which the values match (when RTCNT
is updated from the matching value to a new value). Accordingly, when RTCNT and RTCOR
match, the compare match signal is not generated until the next counter clock pulse. Figure 6.38
shows the timing.
φ
RTCNT
RTCOR
Compare match
signal
CMF flag
N
Figure 6.38 Timing of CMF Flag Setting
Section 6 Bus Controller
H'00
N
Rev. 4.00 Jan 26, 2006 page 191 of 938
REJ09B0276-0400
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