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Section 6 Bus Controller
Table 6.4
Data Buses Used and Valid Strobes
Access
Area
Size
8-bit
Byte
access
area
16-bit
Byte
access
area
Word
Notes: 1. Undetermined data means that unpredictable data is output.
2. Invalid means that the bus is in the input state and the input is ignored.
6.4.4
Memory Areas
The initial state of each area is basic bus interface, three-state access space. The initial bus width is
selected according to the operating mode. The bus specifications described here cover basic items
only, and the following sections should be referred to for further details: 6.4, Basic Bus Interface,
6.5, DRAM Interface, 6.8, Burst ROM Interface.
Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is
external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external
space.
When area 0 external space is accessed, the CS
Either basic bus interface or burst ROM interface can be selected for area 0.
The size of area 0 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3, 4, and 5.
Areas 1 and 6: In external expansion mode, areas 1 and 6 are entirely external space.
When area 1 and 6 external space is accessed, the CS
output.
Only the basic bus interface can be used for areas 1 and 6.
The size of areas 1 and 6 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3, 4, and 5.
Rev. 4.00 Jan 26, 2006 page 154 of 938
REJ09B0276-0400
Read/Write
Address Valid Strobe
Read
—
Write
—
Read
Even
Odd
Write
Even
Odd
Read
—
Write
—
Upper Data Bus
(D
to D
15
RD
Valid
HWR
RD
Valid
Invalid
HWR
Valid
LWR
Undetermined
data
RD
Valid
HWR, LWR
Valid
signal can be output.
0
and CS
pin signals respectively can be
1
6
Lower Data Bus
)
(D
to D
)
8
7
0
Invalid
Undetermined
data
Invalid
Valid
Undetermined
data
Valid
Valid
Valid
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