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φ
Address bus
AS
,
RD HWR LWR
D
to D
15
Figure 2.16 Pin States during On-Chip Memory Access
2.9.3
On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide,
depending on the internal I/O register being accessed. Figure 2.17 shows the on-chip supporting
module access timing. Figure 2.18 indicates the pin states.
φ
Address bus
Internal read signal
Read
access
Internal data bus
Internal write signal
Write
access
Internal data bus
Figure 2.17 Access Cycle for On-Chip Supporting Modules
,
,
High
0
T state
T
1
Address
High impedance
Bus cycle
T state
1
2
Address
Read data
Write data
Rev. 4.00 Jan 26, 2006 page 61 of 938
Section 2 CPU
T
2
T state
3
REJ09B0276-0400
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