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φ
Address bus
CS
n
AS
RD
D
to D
Read access
15
D
to D
7
HWR
LWR
Write access
D
to D
15
D
to D
7
Note: n = 7 to 0
Figure 6.12 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2)
T
1
Odd external address in area n
8
0
High
8
0
(Byte Access to Odd Address)
Section 6 Bus Controller
Bus cycle
T
T
2
3
Invalid
Valid
Undetermined data
Valid
Rev. 4.00 Jan 26, 2006 page 159 of 938
REJ09B0276-0400
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