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Appendix B Internal I/O Registers
DTCR0A—Data Transfer Control Register 0A
•
Short address mode
7
Bit
DTE
Initial value
0
Read/Write
R/W
Data transfer size
0
1
Data transfer enable
0
Data transfer is disabled
1
Data transfer is enabled
Rev. 4.00 Jan 26, 2006 page 820 of 938
REJ09B0276-0400
6
5
4
DTSZ
DTID
RPE
0
0
0
R/W
R/W
R/W
Repeat enable
RPE DTIE
0
0
1
0
1
1
Data transfer increment/decrement
Incremented: If DTSZ = 0, MAR is incremented by 1 after each transfer
0
If DTSZ = 1, MAR is incremented by 2 after each transfer
Decremented: If DTSZ = 0, MAR is decremented by 1 after each transfer
1
If DTSZ = 1, MAR is decremented by 2 after each transfer
Byte-size transfer
Word-size transfer
H'FFF27
3
2
DTIE
DTS2
0
0
R/W
R/W
Data transfer select
Bit 2
Bit 1
Bit 0
DTS2
DTS1
DTS0
0
0
1
0
0
1
1
0
0
1
1
0
1
1
Data transfer interrupt enable
Interrupt requested by
0
DTE bit is disabled
Interrupt requested by
1
DTE bit is enabled
Description
I/O mode
Repeat mode
Idle mode
DMAC0
1
0
DTS1
DTS0
0
0
R/W
R/W
Data Transfer Activation Source
Compare match/input capture A
interrupt from 16-bit timer channel 0
Compare match/input capture A
interrupt from 16-bit timer channel 1
Compare match/input capture A
interrupt from 16-bit timer channel 2
A/D converter conversion end interrupt
SCI0 transmit-data-empty interrupt
SCI0 receive-data-full interrupt
Transfer in full address mode
Transfer in full address mode
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