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Renesas F-ZTAT H8 Series Hardware Manual

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REJ09B0302-0300

16

Rev. 3.00

Revision Date: Mar 21, 2006

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The revision list summarizes the locations of

revisions and additions. Details should always

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H8/3052B F-ZTAT

Renesas 16-Bit Single-Chip Microcomputer

Hardware Manual

H8 Family/H8/300H Series

H8/3052B HD64F3052BTE

HD64F3052BF

™

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Summary of Contents for Renesas F-ZTAT H8 Series

Page 1 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8/3052B F-ZTAT ™ Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series H8/3052B HD64F3052BTE HD64F3052BF Rev. 3.00 Revision Date: Mar 21, 2006...
Page 2 (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp.
Page 3 General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 4 Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Main Revisions for This Edition The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents.
Page 5 This manual describes the H8/3052BF hardware. For details of the instruction set, refer to the H8/300H Series Software Manual. Note: * F-ZTAT (Flexible–Zero Turn Around Time) is a trademark of Renesas Technology Corp. Rev. 3.00 Mar 21, 2006 page v of xxviii...
Page 6 Rev. 3.00 Mar 21, 2006 page vi of xxviii...
Page 7 Item Page Revisions (See Manual for Details)  Nortification of change in company name amended (Before) Hitachi, Ltd. → (After) Renesas Technology Corp. Products deleted H8/3052F-ZTAT (HD64F3052F and HD64F3052TE) and H8/3052F-ZTAT B mask 3 V versions (HD64F3052BVF and HD64F3052BVTE) deleted 1.1 Overview...
Page 8 Item Page Revisions (See Manual for Details) 1.3.3 Pin Functions 13, 17 Table amended and note deleted Table 1.3 Pin Functions Type Symbol Pin No. Power 35, 68 11, 22, 44, 57, 65, 92 6.3.6 Interconnections Figure amended with Memory (Example) EPROM Figure 6.18 to A...
Page 9 Item Page Revisions (See Manual for Details) 9.1 Overview Figure amended Table 9.1 Port Functions Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Port A 8-bit I/O port Output (TP ) from Address output Address TIOCB...
Page 10 Item Page Revisions (See Manual for Details) 14.3.4 Register Settings Table amended Table 14.3 Register Address * Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Settings in Smart Card H'FFB0 CKS1 Interface 18.8.2 Software Note amended Protection 2.
Page 11 Item Page Revisions (See Manual for Details) 20.4.3 Selection of Table amended Waiting Time for Exit from Waiting Software Standby Mode DIV1 DIV0 STS2 STS1 STS0 Time 18 MHz 16 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz 8192 0.91 1.02...
Page 12 Item Page Revisions (See Manual for Details) 21.2.2 AC Characteristics Condition A and Condition B deleted Table 21.7 Timing of On- Table and notes amended Chip Supporting Modules Conditions Test Item Symbol Unit Conditions DREQ setup time DMAC — Figure 21.16 DRQS DREQ hold time —...
Page 13 Item Page Revisions (See Manual for Details) E.2 Timing of Recovery Figure amended from Hardware Standby Mode STBY Figure E.1 Timing of Recovery from Hardware Standby Mode (2) Appendix F Product Table amended Code Lineup Package Product Type Product Code Mark Code (Package Code) Table F.1 H8/3052B F-...
Page 14 Rev. 3.00 Mar 21, 2006 page xiv of xxviii...
Page 15: Table Of Contents
Contents Section 1 Overview ......................Overview........................... Block Diagram ........................Pin Description........................1.3.1 Pin Arrangement ....................1.3.2 Pin Assignments in Each Mode ................1.3.3 Pin Functions ....................... 13 Section 2 CPU ........................19 Overview........................... 19 2.1.1 Features........................ 19 2.1.2 Differences from H8/300 CPU ................20 CPU Operating Modes ......................
Page 16 2.8.6 Reset State......................55 2.8.7 Power-Down State ....................55 Basic Operational Timing ....................56 2.9.1 Overview......................56 2.9.2 On-Chip Memory Access Timing................ 56 2.9.3 On-Chip Supporting Module Access Timing............57 2.9.4 Access to External Address Space ............... 58 Section 3 MCU Operating Modes ..................
Page 17 Section 5 Interrupt Controller ..................79 Overview........................... 79 5.1.1 Features........................ 79 5.1.2 Block Diagram ..................... 80 5.1.3 Pin Configuration....................81 5.1.4 Register Configuration..................81 Register Descriptions ......................82 5.2.1 System Control Register (SYSCR) ..............82 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)..........83 5.2.3 IRQ Status Register (ISR)..................
Page 18 Operation........................... 119 6.3.1 Area Division ....................... 119 6.3.2 Chip Select Signals ....................121 6.3.3 Data Bus....................... 122 6.3.4 Bus Control Signal Timing .................. 123 6.3.5 Wait Modes......................131 6.3.6 Interconnections with Memory (Example) ............137 6.3.7 Bus Arbiter Operation..................139 Usage Notes ........................
Page 19 Register Descriptions (Short Address Mode)..............191 8.2.1 Memory Address Registers (MAR) ..............192 8.2.2 I/O Address Registers (IOAR) ................193 8.2.3 Execute Transfer Count Registers (ETCR)............194 8.2.4 Data Transfer Control Registers (DTCR) ............195 Register Descriptions (Full Address Mode)..............198 8.3.1 Memory Address Registers (MAR) ..............
Page 20 9.2.2 Register Configuration..................250 Port 2..........................252 9.3.1 Overview......................252 9.3.2 Register Configuration..................253 Port 3..........................256 9.4.1 Overview......................256 9.4.2 Register Configuration..................256 Port 4..........................258 9.5.1 Overview......................258 9.5.2 Register Configuration..................259 Port 5..........................262 9.6.1 Overview......................262 9.6.2 Register Configuration..................
Page 21 10.2 Register Descriptions ......................315 10.2.1 Timer Start Register (TSTR)................315 10.2.2 Timer Synchro Register (TSNC) ................. 316 10.2.3 Timer Mode Register (TMDR) ................318 10.2.4 Timer Function Control Register (TFCR)............321 10.2.5 Timer Output Master Enable Register (TOER) ........... 323 10.2.6 Timer Output Control Register (TOCR) ..............
Page 22 11.2.1 Port A Data Direction Register (PADDR) ............401 11.2.2 Port A Data Register (PADR) ................401 11.2.3 Port B Data Direction Register (PBDDR) ............402 11.2.4 Port B Data Register (PBDR) ................402 11.2.5 Next Data Register A (NDRA) ................403 11.2.6 Next Data Register B (NDRB)................
Page 23 13.1.1 Features........................ 435 13.1.2 Block Diagram ..................... 437 13.1.3 Pin Configuration....................438 13.1.4 Register Configuration..................438 13.2 Register Descriptions ......................439 13.2.1 Receive Shift Register (RSR) ................439 13.2.2 Receive Data Register (RDR) ................439 13.2.3 Transmit Shift Register (TSR) ................440 13.2.4 Transmit Data Register (TDR)................
Page 24 Section 15 A/D Converter ....................521 15.1 Overview........................... 521 15.1.1 Features........................ 521 15.1.2 Block Diagram ..................... 522 15.1.3 Pin Configuration....................523 15.1.4 Register Configuration..................524 15.2 Register Descriptions ......................525 15.2.1 A/D Data Registers A to D (ADDRA to ADDRD)..........525 15.2.2 A/D Control/Status Register (ADCSR) ...............
Page 25 18.1 Features ..........................555 18.2 Overview........................... 556 18.2.1 Block Diagram ..................... 556 18.2.2 Mode Transitions ....................556 18.2.3 On-Board Programming Modes................559 18.2.4 Flash Memory Emulation in RAM ..............561 18.2.5 Differences between Boot Mode and User Program Mode ......... 562 18.2.6 Block Configuration.....................
Page 26 19.2.1 Connecting a Crystal Resonator................609 19.2.2 External Clock Input .................... 611 19.3 Duty Adjustment Circuit ....................613 19.4 Prescalers .......................... 613 19.5 Frequency Divider......................613 19.5.1 Register Configuration..................614 19.5.2 Division Control Register (DIVCR) ..............614 19.5.3 Usage Notes ......................615 Section 20 Power-Down State ..................
Page 27 21.2.5 Flash Memory Characteristics................642 21.3 Operational Timing ......................643 21.3.1 Bus Timing ......................643 21.3.2 Refresh Controller Bus Timing................647 21.3.3 Control Signal Timing ..................652 21.3.4 Clock Timing ....................... 654 21.3.5 TPC and I/O Port Timing..................654 21.3.6 ITU Timing ......................655 21.3.7 SCI Input/Output Timing ..................
Page 28 Timing of Recovery from Hardware Standby Mode............807 Appendix F Product Code Lineup .................. 808 Appendix G Package Dimensions .................. 809 Appendix H Differences from H8/3048F-ZTAT ............811 Rev. 3.00 Mar 21, 2006 page xxviii of xxviii...
Page 29: Section 1 Overview
The H8/3052BF has an F-ZTAT™* version with on-chip flash memory that can be programmed on-board. Table 1.1 summarizes the features of the H8/3052BF. Note: * F-ZTAT (Flexible–Zero Turn Around Time) is a trademark of Renesas Technology Corp. Rev. 3.00 Mar 21, 2006 page 1 of 814 REJ09B0302-0300...
Page 30 Section 1 Overview Table 1.1 Features Feature Description Upward-compatible with the H8/300 CPU at the object-code level • General-register machine  Sixteen 16-bit general registers (also usable as + eight 16-bit registers or eight 32-bit registers) • High-speed operation  Maximum clock rate: 25 MHz ...
Page 31 Section 1 Overview Feature Description Bus controller • Address space can be partitioned into eight areas, with independent bus specifications in each area • Chip select output available for areas 0 to 7 • 8-bit access or 16-bit access selectable for each area •...
Page 32 Section 1 Overview Feature Description 16-bit integrated • Five 16-bit timer channels, capable of processing up to 12 pulse outputs or timer unit (ITU) 10 pulse inputs • 16-bit timer counter (channels 0 to 4) • Two multiplexed output compare/input capture pins (channels 0 to 4) •...
Page 33 Section 1 Overview Feature Description D/A converter • Resolution: 8 bits • Two channels • D/A outputs can be sustained in software standby mode • I/O ports 70 input/output pins • 9 input-only pins Operating • Seven MCU operating modes modes Mode Address Space...
Page 34: Block Diagram
Section 1 Overview Block Diagram Figure 1.1 shows an internal block diagram. Port 3 Port 4 Address bus Data bus (upper) Data bus (lower) EXTAL XTAL φ H8/300H CPU STBY Interrupt controller /LWR DMA controller (DMAC) /HWR (flash memory) /BACK /BREQ Refresh /WAIT...
Page 35: Pin Description
Section 1 Overview Pin Description 1.3.1 Pin Arrangement Figure 1.2 shows the pin arrangement of the H8/3052BF. A /P2 A /P2 P7 /AN A /P2 P7 /AN A /P2 P7 /AN A /P2 A /P2 P7 /AN P7 /AN P7 /AN A /P1 P7 /AN /DA A /P1...
Page 36: Pin Assignments In Each Mode
Section 1 Overview 1.3.2 Pin Assignments in Each Mode Table 1.2 lists the pin assignments in each mode. Table 1.2 Pin Assignments in Each Mode (FP-100B or TFP-100B) Pin Name Pin No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7...
Page 37 Section 1 Overview Pin Name Pin No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Rev. 3.00 Mar 21, 2006 page 9 of 814 REJ09B0302-0300...
Page 38 Section 1 Overview Pin Name Pin No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 /WAIT /WAIT /WAIT /WAIT /WAIT /WAIT /BREQ /BREQ /BREQ /BREQ /BREQ /BREQ /BACK /BACK /BACK /BACK /BACK /BACK φ φ...
Page 39 Section 1 Overview Pin Name Pin No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 /RFSH/ /RFSH/ /RFSH/ /RFSH/ /RFSH/ /RFSH/ /IRQ /IRQ /IRQ /IRQ TEND TEND TEND TEND TEND TEND TEND TCLKA TCLKA TCLKA TCLKA TCLKA...
Page 40 Section 1 Overview Pin Name Pin No. Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 TIOCB TIOCB TIOCB TIOCB TIOCB TIOCB TIOCB TCLKD TCLKD TCLKD TCLKD TCLKD TCLKD TCLKD TIOCA TIOCA TIOCA TIOCA TIOCA TIOCA TIOCA TIOCB...
Page 41: Pin Functions
Section 1 Overview 1.3.3 Pin Functions Table 1.3 summarizes the pin functions. Table 1.3 Pin Functions Type Symbol Pin No. Name and Function Power 35, 68 Input Power: For connection to the power supply. Connect all V pins to the system power supply.
Page 42 Section 1 Overview Type Symbol Pin No. Name and Function System control Input Reset input: When driven low, this pin resets the chip Input Flash write enable: Allows program mode setting. STBY Input Standby: When driven low, this pin forces a transition to hardware standby mode BREQ Input...
Page 43 Section 1 Overview Type Symbol Pin No. Name and Function RFSH Refresh Output Refresh: Indicates a refresh cycle controller Row address strobe RAS RAS: Row address Output strobe signal for DRAM connected to area 3 Column address strobe CAS CAS: Column Output address strobe signal for DRAM connected to area 3;...
Page 44 Section 1 Overview Type Symbol Pin No. Name and Function Programmable to TP 9 to 2, Output TPC output 15 to 0: Pulse output timing pattern 100 to 93 controller (TPC) Serial , TxD 13, 12 Output Transmit data (channels 0 and 1): communication SCI data output interface (SCI)
Page 45 Section 1 Overview Type Symbol Pin No. Name and Function I/O ports to P5 56 to 53 Input/ Port 5: Four input/output pins. The direction output of each pin can be selected in the port 5 data direction register (P5DDR). to P6 72 to 69, Input/...
Page 46 Section 1 Overview Rev. 3.00 Mar 21, 2006 page 18 of 814 REJ09B0302-0300...
Page 47: Section 2 Cpu
Section 2 CPU Section 2 CPU Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. 2.1.1 Features The H8/300H CPU has the following features.
Page 48: Differences From H8/300 Cpu
Section 2 CPU  16 × 16-bit register-register multiply: 0.88 µs  32 ÷ 16-bit register-register divide: 0.88 µs • Two CPU operating modes  Normal mode (not available in the H8/3052BF)  Advanced mode • Low-power mode Transition to power-down state by SLEEP instruction 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8/300H has the following enhancements.
Page 49: Cpu Operating Modes
Section 2 CPU CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. The H8/3052BF can be used only in advanced mode. (Information from this point on will apply to advanced mode unless otherwise stated.) Maximum 64 kbytes, program Normal mode...
Page 50: Address Space
Section 2 CPU Address Space The maximum address space of the H8/300H CPU is 16 Mbytes. The H8/3052BF has various operating modes (MCU modes), some providing a 1-Mbyte address space, the others supporting the full 16 Mbytes. Figure 2.2 shows the address ranges of the H8/3052BF. For further details see section 3.6, Memory Map in Each Operating Mode.
Page 51: Register Configuration
Section 2 CPU Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers. General Registers (ERn) (SP) Control Registers (CR) 6 5 4 3 2 1 0 I UI H U N Z V C Legend: Stack pointer...
Page 52: General Registers
Section 2 CPU 2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7).
Page 53: Control Registers
Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the stack. Free area SP (ER7) Stack area Figure 2.5 Stack 2.4.3 Control Registers...
Page 54: Initial Cpu Register Values
Section 2 CPU carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise.
Page 55: Data Formats
Section 2 CPU Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 56 Section 2 CPU General Data Type Register Data Format Word data Word data Longword data Legend: ERn: General register General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.6 General Register Data Formats (2) Rev.
Page 57: Memory Data Formats
Section 2 CPU 2.5.2 Memory Data Formats Figure 2.7 shows the data formats on memory. The H8/300H CPU can access word data and longword data on memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
Page 58: Instruction Set
Section 2 CPU Instruction Set 2.6.1 Instruction Set Overview The H8/300H CPU has 62 types of instructions, which are classified in table 2.1. Table 2.1 Instruction Classification Function Instruction Types MOV, PUSH * , POP * , MOVTPE * , MOVFPE * Data transfer Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA,...
Page 59: Instructions And Addressing Modes
Section 2 CPU 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the instructions available in the H8/300H CPU. Table 2.2 Instructions and Addressing Modes Addressing Modes Function Instruction Data — — — — transfer POP, PUSH — — — — —...
Page 60: Tables Of Instructions Classified By Function
Section 2 CPU 2.6.3 Tables of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation General register (destination) * General register (source) * General register * General register (32-bit register or address register) (EAd)
Page 61 Section 2 CPU Table 2.3 Data Transfer Instructions Size * Instruction Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) →...
Page 62 Section 2 CPU Table 2.4 Arithmetic Operation Instructions Size * Instruction Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD, SUB B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register.
Page 63 Section 2 CPU Size * Instruction Function Rd ÷ Rs → Rd DIVXU Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. Rd ÷...
Page 64 Section 2 CPU Table 2.5 Logic Operation Instructions Size * Instruction Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 65 Section 2 CPU Table 2.7 Bit Manipulation Instructions Size * Instruction Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
Page 66 Section 2 CPU Size * Instruction Function C ∨ (<bit-No.> of <EAd>) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ∨ [¬ (<bit-No.> of <EAd>)] → C BIOR ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag.
Page 67 Section 2 CPU Table 2.8 Branching Instructions Instruction Size Function — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never C ∨...
Page 68 Section 2 CPU Table 2.9 System Control Instructions Size * Instruction Function TRAPA — Starts trap-instruction exception handling — Returns from an exception-handling routine SLEEP — Causes a transition to the power-down state (EAs) → CCR Moves the source operand contents to the condition code register. The condition code register size is one byte, but in transfer from memory, data is read by word access.
Page 69 Section 2 CPU Table 2.10 Block Transfer Instruction Instruction Size Function if R4L ≠ 0 then EEPMOV.B — @ER5+ → @ER6+, R4L – 1 → R4L repeat until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W — @ER5+ →...
Page 70: Basic Instruction Formats
Section 2 CPU 2.6.4 Basic Instruction Formats The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (OP field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand.
Page 71: Notes On Use Of Bit Manipulation Instructions
Section 2 CPU 2.6.5 Notes on Use of Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the byte, then write the byte back. Care is required when these instructions are used to access registers with write-only bits, or to access ports.
Page 72: Addressing Modes And Effective Address Calculation
Section 2 CPU Explanation of BCLR Instruction To execute the BCLR instruction, the CPU begins by reading P4DDR. Since P4DDR is a write- only register, it is read as H'FF, even though its true value is H'3F. Next the CPU clears bit 0 of the read data, changing the value to H'FE. Finally, the CPU writes this value (H'FE) back to DDR to complete the BCLR instruction.
Page 73 Section 2 CPU Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
Page 74 Section 2 CPU Table 2.12 Absolute Address Access Ranges Absolute Address 1-Mbyte Modes 16-Mbyte Modes 8 bits (@aa:8) H'FFF00 to H'FFFFF H'FFFF00 to H'FFFFFF (1048320 to 1048575) (16776960 to 16777215) 16 bits (@aa:16) H'00000 to H'07FFF, H'000000 to H'007FFF, H'F8000 to H'FFFFF H'FF8000 to H'FFFFFF (0 to 32767, 1015808 to 1048575) (0 to 32767, 16744448 to 16777215)
Page 75: Effective Address Calculation
Section 2 CPU Specified by @aa:8 Reserved Branch address Figure 2.9 Memory-Indirect Branch Address Specification When a word-size or longword-size memory operand is specified, or when a branch address is specified, if the specified memory address is odd, the least significant bit is regarded as 0. The accessed data or instruction code therefore begins at the preceding address.
Page 76 Section 2 CPU Table 2.13 Effective Address Calculation Addressing Mode and Effective Address Instruction Format Calculation Effective Address Register direct (Rn) Operand is general register contents rm rn Register indirect (@ERn) General register contents Register indirect with displacement @(d:16, ERn)/@(d:24, ERn) General register contents disp Sign extension...
Page 77 Section 2 CPU Addressing Mode and Effective Address Instruction Format Calculation Effective Address Absolute address @aa:8 H'FFFF @aa:16 16 15 Sign exten- sion @aa:24 Immediate Operand is immediate #xx:8, #xx:16, or #xx:32 data Program-counter relative @(d:8, PC) or @(d:16, PC) PC contents Sign disp...
Page 78 Section 2 CPU Addressing Mode and Effective Address Instruction Format Calculation Effective Address Memory indirect @@aa:8 · Normal mode H'0000 16 15 Memory contents H'00 · Advanced mode H'0000 Memory contents Legend: r, rm, rn: Register field Operation field disp: Displacement IMM: Immediate data...
Page 79: Processing States
Section 2 CPU Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2.10 classifies the processing states.
Page 80: Program Execution State
Section 2 CPU 2.8.2 Program Execution State In this state the CPU executes program instructions in normal sequence. 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and branches to that address.
Page 81 Section 2 CPU Reset External interrupts Exception Interrupt sources Internal interrupts (from on-chip supporting modules) Trap instruction Figure 2.11 Classification of Exception Sources End of bus release Bus request Program execution state End of bus SLEEP release instruction with SSBY = 0 request Exception Bus-released state...
Page 82: Exception-Handling Sequences
Section 2 CPU 2.8.4 Exception-Handling Sequences Reset Exception Handling: Reset exception handling has the highest priority. The reset state is entered when the RES signal goes low. Reset exception handling starts after that, when RES changes from low to high. When reset exception handling starts the CPU fetches a start address from the exception vector table and starts program execution from that address.
Page 83: Bus-Released State
Section 2 CPU 2.8.5 Bus-Released State In this state the bus is released to a bus master other than the CPU, in response to a bus request. The bus masters other than the CPU are the DMA controller, the refresh controller, and an external bus master.
Page 84: Basic Operational Timing
Section 2 CPU Basic Operational Timing 2.9.1 Overview The H8/300H CPU operates according to the system clock (φ). The interval from one rise of the system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of two or three states.
Page 85: On-Chip Supporting Module Access Timing
Section 2 CPU φ Address bus Address RD HWR LWR High High impedance to D Figure 2.15 Pin States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide, depending on the register being accessed.
Page 86: Access To External Address Space
Section 2 CPU φ Address bus Address RD HWR LWR High High impedance to D Figure 2.17 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings determine whether each area is accessed via an 8-bit or 16-bit bus, and whether it is accessed in two or three states.
Page 87: Section 3 Mcu Operating Modes
Section 3 MCU Operating Modes Section 3 MCU Operating Modes Overview 3.1.1 Operating Mode Selection The H8/3052BF has seven operating modes (modes 1 to 7) that are selected by the mode pins to MD ) as indicated in table 3.1. The input at these pins determines the size of the address space and the initial bus mode.
Page 88: Register Configuration
Section 3 MCU Operating Modes Modes 5 and 6 are externally expanded modes that enable access to external memory and peripheral devices and also enable access to the on-chip ROM. Mode 5 supports a maximum address space of 1 Mbyte. Mode 6 supports a maximum address space of 16 Mbytes. Mode 7 is a single-chip mode that operates using the on-chip ROM, RAM, and Internal I/O registers, and makes all I/O ports available.
Page 89: System Control Register (Syscr)
Section 3 MCU Operating Modes Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the logic levels at pins to MD (the current operating mode). MDS2 to MDS0 correspond to MD to MD . MDS2 to MDS0 are read-only bits.
Page 90 Section 3 MCU Operating Modes Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt. When using a crystal oscillator, set these bits so that the waiting time will be at least 7 ms at the system clock rate.
Page 91: Operating Mode Descriptions
Section 3 MCU Operating Modes Operating Mode Descriptions 3.4.1 Mode 1 Ports 1, 2, and 5 function as address pins A to A , permitting access to a maximum 1-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
Page 92: Mode 6
Section 3 MCU Operating Modes 3.4.6 Mode 6 Ports 1, 2, and 5 and part of port A function as address pins A to A , permitting access to a maximum 16-Mbyte address space, but following a reset they are input ports. To use ports 1, 2, and 5 as an address bus, the corresponding bits in their data direction registers (P1DDR, P2DDR, and P5DDR) must be set to 1.
Page 93: Memory Map In Each Operating Mode
Section 3 MCU Operating Modes Memory Map in Each Operating Mode Figure 3.1 shows a memory map of the H8/3052BF. The address space is divided into eight areas. The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4. The address locations of the on-chip RAM and on-chip registers differ between the 1-Mbyte modes (modes 1, 2, 5, and 7) and 16-Mbyte modes (modes 3, 4, and 6).
Page 94 Section 3 MCU Operating Modes Modes 1 and 2 Modes 3 and 4 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'20000 H'1FFFFF...
Page 95 Section 3 MCU Operating Modes Mode 5 Mode 6 Mode 7 (1-Mbyte expanded mode with (16-Mbyte expanded mode with (single-chip advanced mode) on-chip ROM enabled) on-chip ROM enabled) H'00000 H'000000 H'00000 Vector area Vector area Vector area H'000FF H'0000FF H'000FF On-chip ROM On-chip ROM On-chip ROM...
Page 96 Section 3 MCU Operating Modes Rev. 3.00 Mar 21, 2006 page 68 of 814 REJ09B0302-0300...
Page 97: Section 4 Exception Handling
Section 4 Exception Handling Section 4 Exception Handling Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in priority order.
Page 98: Exception Sources And Vector Table
Section 4 Exception Handling 4.1.3 Exception Sources and Vector Table The exception sources are classified as shown in figure 4.1. Different vectors are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. • Reset External interrupts: NMI, IRQ to IRQ Exception...
Page 99 Section 4 Exception Handling Table 4.2 Exception Vector Table Vector Address * Exception Source Vector Number Reset H'0000 to H'0003 Reserved for system use H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B External interrupt (NMI) H'001C to H'001F Trap instruction (4 sources)
Page 100: Reset
Section 4 Exception Handling Reset 4.2.1 Overview A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip supporting modules.
Page 101 Section 4 Exception Handling Figure 4.2 Reset Sequence (Modes 1 and 3) Rev. 3.00 Mar 21, 2006 page 73 of 814 REJ09B0302-0300...
Page 102 Section 4 Exception Handling Internal Vector fetch processing Prefetch of first program instruction φ Address bus High to D (1), (3) Address of reset vector: (1) = H'000000, (3) = H'000002 (2), (4) Start address (contents of reset vector) Start address First instruction of program Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Page 103: Interrupts After Reset
Section 4 Exception Handling Prefetch of Internal first program processing Vector fetch instruction φ Internal address bus Internal read signal Internal write signal Internal data bus (16 bits wide) (1), (3) Address of reset vector ((1) = H'000000, (2) = H'000002) (2), (4) Start address (contents of reset vector) Start address...
Page 104: Interrupts
Section 4 Exception Handling Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ to IRQ ) and 30 internal sources in the on-chip supporting modules. Figure 4.5 classifies the interrupt sources and indicates the number of interrupts of each type. The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), refresh controller, 16-bit integrated timer unit (ITU), DMA controller (DMAC), serial communication interface (SCI), and A/D converter.
Page 105: Trap Instruction
Section 4 Exception Handling Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1 in CCR.
Page 106: Notes On Use Of The Stack
Section 4 Exception Handling Notes on Use of the Stack When accessing word data or longword data, the H8/3052BF regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack pointer (SP, ER7) should always be kept even.
Page 107: Section 5 Interrupt Controller
Section 5 Interrupt Controller Section 5 Interrupt Controller Overview 5.1.1 Features The interrupt controller has the following features: • Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a source-by-source or module-by-module basis in interrupt priority registers A and B (IPRA and IPRB).
Page 108: Block Diagram
Section 5 Interrupt Controller 5.1.2 Block Diagram Figure 5.1 shows a block diagram of the interrupt controller. ISCR IPRA, IPRB input IRQ input IRQ input section ISR Interrupt request Priority decision logic Vector number ADIE Interrupt controller SYSCR Legend: ISCR: IRQ sense control register IER: IRQ enable register...
Page 109: Pin Configuration
Section 5 Interrupt Controller 5.1.3 Pin Configuration Table 5.1 lists the interrupt pins. Table 5.1 Interrupt Pins Name Abbreviation Function Nonmaskable interrupt Input Nonmaskable external interrupt, rising edge or falling edge selectable to IRQ External interrupt request Input Maskable external interrupts, falling 5 to 0 edge or level sensing selectable 5.1.4...
Page 110: Register Descriptions
Section 5 Interrupt Controller Register Descriptions 5.2.1 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM. Only bits 3 and 2 are described here.
Page 111: Interrupt Priority Registers A And B (Ipra, Iprb)
Section 5 Interrupt Controller Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3: UE Description UI bit in CCR is used as interrupt mask bit UI bit in CCR is used as user bit (Initial value) Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.
Page 112 Section 5 Interrupt Controller Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 Initial value Read/Write Priority level A0 Selects the priority level of ITU channel 2 interrupt...
Page 113 Section 5 Interrupt Controller Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ interrupt requests. Bit 7: IPRA7 Description interrupt requests have priority level 0 (Non-priority) (Initial value) interrupt requests have priority level 1 (Priority) Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ interrupt requests.
Page 114 Section 5 Interrupt Controller Bit 2—Priority Level A2 (IPRA2): Selects the priority level of ITU channel 0 interrupt requests. Bit 2: IPRA2 Description ITU channel 0 interrupt requests have priority level 0 (Non-priority) (Initial value) ITU channel 0 interrupt requests have priority level 1 (Priority) Bit 1—Priority Level A1 (IPRA1): Selects the priority level of ITU channel 1 interrupt requests.
Page 115 Section 5 Interrupt Controller Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRB7 IPRB6 IPRB5 — IPRB3 IPRB2 IPRB1 — Initial value Read/Write Reserved bit Priority level B1 Selects the priority level of A/D converter interrupt request Priority level B2...
Page 116 Section 5 Interrupt Controller Bit 7—Priority Level B7 (IPRB7): Selects the priority level of ITU channel 3 interrupt requests. Bit 7: IPRB7 Description ITU channel 3 interrupt requests have priority level 0 (low priority) (Initial value) ITU channel 3 interrupt requests have priority level 1 (high priority) Bit 6—Priority Level B6 (IPRB6): Selects the priority level of ITU channel 4 interrupt requests.
Page 117: Irq Status Register (Isr)
Section 5 Interrupt Controller Bit 1—Priority Level B1 (IPRB1): Selects the priority level of A/D converter interrupt requests. Bit 1: IPRB1 Description A/D converter interrupt requests have priority level 0 (low priority) (Initial value) A/D converter interrupt requests have priority level 1 (high priority) Bit 0—Reserved: This bit can be written and read, but it does not affect interrupt priority.
Page 118: Irq Enable Register (Ier)
Section 5 Interrupt Controller 5.2.4 IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ to IRQ interrupt requests. — — IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value Read/Write IRQ to IRQ enable Reserved bits These bits enable or disable IRQ to IRQ interrupts IER is initialized to H'00 by a reset and in hardware standby mode.
Page 119: Irq Sense Control Register (Iscr)
Section 5 Interrupt Controller 5.2.5 IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins IRQ to IRQ — — IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC Initial value Read/Write IRQ to IRQ sense control Reserved bits...
Page 120: Interrupt Sources
Section 5 Interrupt Controller Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ to IRQ ) and 30 internal interrupts. 5.3.1 External Interrupts There are seven external interrupts: NMI, and IRQ to IRQ . Of these, NMI, IRQ , IRQ , and IRQ can be used to exit software standby mode.
Page 121: Internal Interrupts
Section 5 Interrupt Controller Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF). φ IRQn input pin IRQnF Note: n = 5 to 0 Figure 5.3 Timing of Setting of IRQnF Interrupts IRQ to IRQ have vector numbers 12 to 17. These interrupts are detected regardless of whether the corresponding pin is set for input or output.
Page 122 Section 5 Interrupt Controller Table 5.3 Interrupt Sources, Vector Addresses, and Priority Vector Vector Address * Interrupt Source Origin Number Priority External pins H'001C to H'001F — High ↑ H'0030 to H'0033 IPRA7  H'0034 to H0037 IPRA6  H'0038 to H'003B IPRA5 ...
Page 123 Section 5 Interrupt Controller Vector Vector Address * Interrupt Source Origin Number Priority IMIA2 ITU channel 2 H'0080 to H'0083 IPRA0 High (compare match/ ↑ input capture A2)   IMIB2 H'0084 to H'0087  (compare match/  input capture B2) ...
Page 124 Section 5 Interrupt Controller Vector Vector Address * Interrupt Source Origin Number Priority ERI0 SCI channel 0 H'00D0 to H'00D3 IPRB3 High (receive error 0) ↑  RXI0 H'00D4 to H'00D7  (receive data full 0)  TXI0 (transmit data H'00D8 to H'00DB ...
Page 125: Interrupt Operation
Section 5 Interrupt Controller Interrupt Operation 5.4.1 Interrupt Handling Process The H8/3052BF handles interrupts differently depending on the setting of the UE bit. When UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI bits.
Page 126 Section 5 Interrupt Controller Program execution state Interrupt requested? Pending Priority level 1? I = 0 Save PC and CCR ← Read vector address Branch to interrupt service routine Figure 5.4 Process Up to Interrupt Acceptance when UE = 1 Rev.
Page 127 Section 5 Interrupt Controller 1. If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. When the interrupt controller receives one or more interrupt requests, it selects the highest- priority request, following the IPR interrupt priority settings, and holds other requests pending.
Page 128 Section 5 Interrupt Controller ← All interrupts are Only NMI, IRQ , and ← ← 1, UI enabled IRQ are enabled Exception handling, ← ← or I 1, UI ← ← Exception handling, ← or UI All interrupts are disabled except NMI Figure 5.5 Interrupt Enable/Disable State Transitions (Example) Figure 5.6 is a flowchart showing how interrupts are accepted when UE = 0.
Page 129 Section 5 Interrupt Controller Program execution state Interrupt requested? Pending Priority level 1? I = 0 I = 0 UI = 0 Save PC and CCR ← ← 1, UI Read vector address Branch to interrupt service routine Figure 5.6 Process Up to Interrupt Acceptance when UE = 0 Rev.
Page 130: Interrupt Exception Handling Sequence
Section 5 Interrupt Controller 5.4.2 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt sequence in mode 2 when the program area and stack area are in 16-bit, two-state access space in external memory. Figure 5.7 Interrupt Sequence (Mode 2, Two-State Access, Stack in External Memory) Rev.
Page 131: Interrupt Response Time
Section 5 Interrupt Controller 5.4.3 Interrupt Response Time Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5.5 Interrupt Response Time External Memory 8-Bit Bus 16-Bit Bus On-Chip...
Page 132: Usage Notes
Section 5 Interrupt Controller Usage Notes 5.5.1 Contention between Interrupt Generation and Disabling When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not actually disabled until after execution of the instruction is completed. Thus, if an interrupt occurs while a BCLR, MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt exception handling is carried out.
Page 133: Instructions That Inhibit Interrupts
Section 5 Interrupt Controller 5.5.2 Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting instructions, however, when the instruction is completed the CPU always continues by executing the next instruction.
Page 134 Section 5 Interrupt Controller Occurrence Conditions 1. If an ISR register read is executed to clear the IRQaF flag while IRQaF = 1, and then the IRQbF flag is cleared by the initiation of interrupt exception handling. 2. If there is contention between IRQaF flag clearing and IRQbF generation (IRQaF flag setting) (when IRQbF = 0 at the time of the ISR read to clear the IRQaF flag, but IRQbF is set to 1 before the write to ISR).
Page 135 Section 5 Interrupt Controller MOV.B @ISR,R0L MOV.B #HFE,R0L MOV.B R0L,@ISR • Solution 2 During IRQb interrupt processing, carry out IRQbF flag clear dummy processing. For example, if b = 1 IRQB MOV.B #HFD,R0L MOV.B R0L,@ISR · · · Rev. 3.00 Mar 21, 2006 page 107 of 814 REJ09B0302-0300...
Page 136 Section 5 Interrupt Controller Rev. 3.00 Mar 21, 2006 page 108 of 814 REJ09B0302-0300...
Page 137: Section 6 Bus Controller
Section 6 Bus Controller Section 6 Bus Controller Overview The H8/3052BF has an on-chip bus controller that divides the address space into eight areas and can assign different bus specifications to each. This enables different types of memory to be connected easily.
Page 138: Block Diagram
Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. CS to CS ABWCR Internal ASTCR address bus Area WCER decoder Chip select CSCR Internal signals control signals Bus mode control signal Bus control circuit Bus size control signal Access state control signal...
Page 139: Pin Configuration
Section 6 Bus Controller 6.1.3 Pin Configuration Table 6.1 summarizes the bus controller’s input/output pins. Table 6.1 Bus Controller Pins Name Abbreviation Function to CS Chip select 0 to 7 Output Strobe signals selecting areas 0 to 7 Address strobe Output Strobe signal indicating valid address output on the address bus...
Page 140: Register Configuration
Section 6 Bus Controller 6.1.4 Register Configuration Table 6.2 summarizes the bus controller’s registers. Table 6.2 Bus Controller Registers Initial Value Modes Modes Address * Name Abbreviation 1, 3, 5, 6 2, 4, 7 H'FFEC Bus width control register ABWCR H'FF H'00 H'FFED...
Page 141: Access State Control Register (Astcr)
Section 6 Bus Controller Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access or 16-bit access to the corresponding address areas. Bits 7 to 0: ABW7 to ABW0 Description Areas 7 to 0 are 16-bit access areas Areas 7 to 0 are 8-bit access areas ABWCR specifies the bus width of external memory areas.
Page 142: Wait Control Register (Wcr)
Section 6 Bus Controller 6.2.3 Wait Control Register (WCR) WCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller (WSC) and specifies the number of wait states. — — — — WMS1 WMS0 Initial value Read/Write —...
Page 143: Wait State Controller Enable Register (Wcer)
Section 6 Bus Controller 6.2.4 Wait State Controller Enable Register (WCER) WCER is an 8-bit readable/writable register that enables or disables wait-state control of external three-state-access areas by the wait-state controller. WCE7 WCE6 WCE5 WCE4 WCE3 WCE2 WCE1 WCE0 Initial value Read/Write Wait-state controller enable 7 to 0 These bits enable or disable wait-state control...
Page 144: Bus Release Control Register (Brcr)
Section 6 Bus Controller 6.2.5 Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables address output on bus lines A to A enables or disables release of the bus to an external device. A23E A22E A21E —...
Page 145 Section 6 Bus Controller Bit 5—Address 21 Enable (A21E): Enables PA to be used as the A address output pin. Writing 0 in this bit enables A address output from PA . In modes other than 3, 4, and 6 this bit cannot be modified and PA has its ordinary input/output functions.
Page 146: Chip Select Control Register (Cscr)
Section 6 Bus Controller 6.2.6 Chip Select Control Register (CSCR) CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals to CS to CS If a chip select signal (CS ) output is selected in this register, the corresponding pin to CS functions as a chip select signal (CS ) output, this function taking priority over other...
Page 147: Operation
Section 6 Bus Controller Operation 6.3.1 Area Division The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the 1-Mbyte modes, or 2 Mbytes in the 16-Mbyte modes. Figure 6.2 shows a general view of the memory map.
Page 148 Section 6 Bus Controller to CS Chip select signals (CS ) can be output for areas 7 to 0. The bus specifications for each area can be selected in ABWCR, ASTCR, WCER, and WCR as shown in table 6.3. Table 6.3 Bus Specifications ABWCR ASTCR...
Page 149: Chip Select Signals
Section 6 Bus Controller 6.3.2 Chip Select Signals to CS For each of areas 7 to 0, the H8/3052BF can output a chip select signal (CS ) that goes low to indicate when the area is selected. Figure 6.3 shows the output timing of a CS signal (n = 7 to Output of CS to CS...
Page 150: Data Bus
Section 6 Bus Controller 6.3.3 Data Bus The H8/3052BF allows either 8-bit access or 16-bit access to be designated for each of areas 0 to 7. An 8-bit-access area uses the upper data bus (D to D ). A 16-bit-access area uses both the upper data bus (D to D ) and lower data bus (D...
Page 151: Bus Control Signal Timing
Section 6 Bus Controller 6.3.4 Bus Control Signal Timing 8-Bit, Three-State-Access Areas: Figure 6.4 shows the timing of bus control signals for an 8-bit, ) is used to access these areas. The LWR three-state-access area. The upper address bus (D to D pin is always high.
Page 152 Section 6 Bus Controller 8-Bit, Two-State-Access Areas: Figure 6.5 shows the timing of bus control signals for an 8-bit, ) is used to access these areas. The LWR two-state-access area. The upper address bus (D to D pin is always high. Wait states cannot be inserted. Bus cycle φ...
Page 153 Section 6 Bus Controller 16-Bit, Three-State-Access Areas: Figures 6.6 to 6.8 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper address bus (D to D ) is used to access even addresses and the lower address bus (D to D ) is used to access odd addresses.
Page 154 Section 6 Bus Controller Bus cycle φ Address bus Odd external address in area n Read to D Invalid access D to D Valid High Write access to D Undetermined data Valid D to D Note: n = 7 to 0 Figure 6.7 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2) (Byte Access to Odd Address) Rev.
Page 155 Section 6 Bus Controller Bus cycle φ Address bus External address in area n Read to D Valid access D to D Valid Write access to D Valid D to D Valid Note: n = 7 to 0 Figure 6.8 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3) (Word Access) Rev.
Page 156 Section 6 Bus Controller 16-Bit, Two-State-Access Areas: Figures 6.9 to 6.11 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper address bus (D to D ) is used to access even addresses and the lower address bus (D to D ) is used to access odd addresses.
Page 157 Section 6 Bus Controller Bus cycle φ Address bus Odd external address in area n Read to D Invalid access Valid D to D High Write access to D Undetermined data D to D Valid Note: n = 7 to 0 Figure 6.10 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2) (Byte Access to Odd Address) Rev.
Page 158 Section 6 Bus Controller Bus cycle φ Address bus External address in area n Read to D Valid access Valid D to D Write access to D Valid D to D Valid Note: n = 7 to 0 Figure 6.11 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3) (Word Access) Rev.
Page 159: Wait Modes
Section 6 Bus Controller 6.3.5 Wait Modes Four wait modes can be selected as shown in table 6.5. Table 6.5 Wait Mode Selection ASTCR WCER ASTn Bit WCEn Bit WMS1 Bit WMS0 Bit WSC Control Wait Mode — — — Disabled No wait states —...
Page 160 Section 6 Bus Controller Wait Mode in Areas Where Wait-State Controller is Disabled: External three-state access areas in which the wait-state controller is disabled (ASTn = 1, WCEn = 0) operate in pin wait mode 0. The other wait modes are unavailable. The settings of bits WMS1 and WMS0 are ignored in these areas.
Page 161 Section 6 Bus Controller Wait Modes in Areas Where Wait-State Controller is Enabled: External three-state access areas in which the wait-state controller is enabled (ASTn = 1, WCEn = 1) can operate in pin wait mode 1, pin auto-wait mode, or programmable wait mode, as selected by bits WMS1 and WMS0. Bits WMS1 and WMS0 apply to all areas, so all areas in which the wait-state controller is enabled operate in the same wait mode.
Page 162 Section 6 Bus Controller • Pin Auto-Wait Mode If the WAIT pin is low, the number of wait states (T ) selected by bits WC1 and WC0 are inserted. In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock (φ) in the T state, the number of wait states (T ) selected by bits WC1 and WC0 are inserted.
Page 163 Section 6 Bus Controller • Programmable Wait Mode The number of wait states (T ) selected by bits WC1 and WC0 are inserted in all accesses to external three-state-access areas. Figure 6.15 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1).
Page 164 Section 6 Bus Controller Example of Wait State Control Settings: A reset initializes ASTCR and WCER to H'FF and WCR to H'F3, selecting programmable wait mode and three wait states for all areas. Software can select other wait modes for individual areas by modifying the ASTCR, WCER, and WCR settings. Figure 6.16 shows an example of wait mode settings.
Page 165: Interconnections With Memory (Example)
Section 6 Bus Controller 6.3.6 Interconnections with Memory (Example) For each area, the bus controller can select two- or three-state access and an 8- or 16-bit data bus width. In three-state-access areas, wait states can be inserted in a variety of modes, simplifying the connection of both high-speed and low-speed devices.
Page 166 Section 6 Bus Controller EPROM to A to A to I/O H8/3052BF I/O to I/O SRAM1 (even addresses) to A to A I/O to I/O WAIT SRAM2 (odd addresses) to A to A to A I/O to I/O to D SRAM3 D to D to A...
Page 167: Bus Arbiter Operation
Section 6 Bus Controller 6.3.7 Bus Arbiter Operation The bus controller has a built-in bus arbiter that arbitrates between different bus masters. There are four bus masters: the CPU, DMA controller (DMAC), refresh controller, and an external bus master. When a bus master has the bus right it can carry out read, write, or refresh access. Each bus master uses a bus request signal to request the bus right.
Page 168 Section 6 Bus Controller DMAC: When the DMAC receives an activation request, it requests the bus right from the bus arbiter. If the DMAC is bus master and the refresh controller or an external bus master requests the bus, the bus arbiter transfers the bus right from the DMAC to the bus master that requested the bus.
Page 169 Section 6 Bus Controller Figure 6.19 shows the timing when the bus right is requested by an external bus master during a read cycle in a two-state-access area. There is a minimum interval of two states from when the BREQ signal goes low until the bus is released. CPU cycles External bus released CPU cycles...
Page 170: Usage Notes
Section 6 Bus Controller Usage Notes 6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM A different bus control signal timing applies when dynamic RAM or pseudo-static RAM is connected to area 3. For details see section 7, Refresh Controller. 6.4.2 Register Write Timing ABWCR, ASTCR, and WCER Write Timing: Data written to ABWCR, ASTCR, or WCER takes effect starting from the next bus cycle.
Page 171 Section 6 Bus Controller DDR Write Timing: Data written to a data direction register (DDR) to change a CS pin from output to generic input, or vice versa, takes effect starting from the T state of the DDR write cycle. Figure 6.21 shows the timing when the CS pin is changed from generic input to CS output.
Page 172: Breq Input Timing
Section 6 Bus Controller BREQ Input Timing BREQ BREQ BREQ 6.4.3 After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high level before BACK goes low, the bus arbiter may operate incorrectly. To terminate the external-bus-released state, hold the BREQ signal high for at least three states.
Page 173: Section 7 Refresh Controller
Section 7 Refresh Controller Section 7 Refresh Controller Overview The H8/3052BF has an on-chip refresh controller that enables direct connection of 16-bit-wide DRAM or pseudo-static RAM (PSRAM). DRAM or pseudo-static RAM can be directly connected to area 3 of the external address space. A maximum 128 kbytes can be connected in modes 1 and 2 (1-Mbyte modes).
Page 174 Section 7 Refresh Controller Features as a Pseudo-Static RAM Refresh Controller • RFSH signal output for refresh control • Software-selectable refresh interval • Software-selectable self-refresh mode • Wait states can be inserted Features as an Interval Timer • Refresh timer counter (RTCNT) can be used as an 8-bit up-counter •...
Page 175: Block Diagram
Section 7 Refresh Controller 7.1.2 Block Diagram Figure 7.1 shows a block diagram of the refresh controller. φ/2, φ/8, φ/32, φ/128, φ/512, Refresh signal φ/2048, φ/4096 Clock selector Control logic CMI interrupt Comparator Module data bus Legend: RTCNT: Refresh timer counter RTCOR: Refresh time constant register RTMCSR:...
Page 176: Pin Configuration
Section 7 Refresh Controller 7.1.3 Pin Configuration Table 7.1 summarizes the refresh controller’s input/output pins. Table 7.1 Refresh Controller Pins Signal Name Abbr. Function RFSH RFSH Refresh Output Goes low during refresh cycles; used to refresh DRAM and PSRAM UW/UCAS Connects to the UW pin of 2WE Upper write/upper column Output...
Page 177: Register Descriptions
Section 7 Refresh Controller Register Descriptions 7.2.1 Refresh Control Register (RFSHCR) RFSHCR is an 8-bit readable/writable register that selects the operating mode of the refresh controller. SRFMD PSRAME DRAME CAS/WE M9/M8 RFSHE — RCYCE Initial value Read/Write — Refresh cycle enable Enables or disables...
Page 178 Section 7 Refresh Controller Bit 7—Self-Refresh Mode (SRFMD): Specifies DRAM or pseudo-static RAM self-refresh during software standby mode. When PSRAME = 1 and DRAME = 0, after the SRFMD bit is set to 1, pseudo-static RAM can be self-refreshed when the H8/3052BF enters software standby mode.
Page 179 Section 7 Refresh Controller M8): Selects 8-bit or 9-bit column addressing. Bit 3—Address Multiplex Mode Select (M9/M8 The setting of this bit is valid when PSRAME = 0 and DRAME = 1. This bit is write-disabled when the PSRAME or DRAME bit is set to 1. Bit 3: M9/M8 Description 8-bit column address mode...
Page 180: Refresh Timer Control/Status Register (Rtmcsr)
Section 7 Refresh Controller 7.2.2 Refresh Timer Control/Status Register (RTMCSR) RTMCSR is an 8-bit readable/writable register that selects the clock source for RTCNT. It also enables or disables interrupt requests when the refresh controller is used as an interval timer. CMIE CKS2 CKS1...
Page 181: Refresh Timer Counter (Rtcnt)
Section 7 Refresh Controller Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables the CMI interrupt requested when the CMF flag is set to 1 in RTMCSR. The CMIE bit is always cleared to 0 when PSRAME = 1 or DRAME = 1. Bit 6: CMIE Description The CMI interrupt requested by CMF is disabled...
Page 182: Refresh Time Constant Register (Rtcor)
Section 7 Refresh Controller RTCNT is write-disabled when the PSRAME bit or DRAME bit is set to 1. RTCNT is initialized to H'00 by a reset and in standby mode. 7.2.4 Refresh Time Constant Register (RTCOR) RTCOR is an 8-bit readable/writable register that determines the interval at which RTCNT is compare matched.
Page 183: Operation
Section 7 Refresh Controller Operation 7.3.1 Overview One of three functions can be selected for the H8/3052BF refresh controller: interfacing to DRAM connected to area 3, interfacing to pseudo-static RAM connected to area 3, or interval timing. Table 7.3 summarizes the register settings when these three functions are used. Table 7.3 Refresh Controller Settings Usage...
Page 184 Section 7 Refresh Controller DRAM Interface: To set up area 3 for connection to 16-bit-wide DRAM, initialize RTCOR, RTMCSR, and RFSHCR in that order, clearing bit PSRAME to 0 and setting bit DRAME to 1. DDR to 1 in the port 8 data direction register (P8DDR) to enable CS Set bit P8 output.
Page 185: Dram Refresh Control
Section 7 Refresh Controller 7.3.2 DRAM Refresh Control Refresh Request Interval and Refresh Cycle Execution: The refresh request interval is determined by the settings of RTCOR and bits CKS2 to CKS0 in RTMCSR. Figure 7.2 illustrates the refresh request interval. RTCOR RTCNT H'00...
Page 186 Section 7 Refresh Controller When a refresh request occurs in the refresh request pending state, the refresh controller acquires the bus right, then executes a refresh cycle. If another refresh request occurs during execution of the refresh cycle, it is ignored. Exit from reset or standby mode Refresh request End of refresh...
Page 187 Section 7 Refresh Controller Address Multiplexing: Address multiplexing depends on the setting of the M9/M8 bit in RFSHCR, as described in table 7.5. Figure 7.4 shows the address output timing. Address output is multiplexed only in area 3. Table 7.5 Address Multiplexing Address Pins Address signals during row...
Page 188 Section 7 Refresh Controller CAS and 2WE WE Modes: The CAS/WE bit in RFSHCR can select two control modes for 16-bit- 2CAS wide DRAM: one using UCAS and LCAS; the other using UW and LW. These DRAM pins correspond to H8/3052BF pins as shown in table 7.6. Table 7.6 DRAM Pins and H8/3052BF Pins DRAM Pin...
Page 189 Section 7 Refresh Controller Read cycle Write cycle Refresh cycle φ Address Column Column Area 3 top address (RAS) (UCAS) (UW) (LW) RFSH Note: 16-bit access CAS Mode) Figure 7.5 DRAM Control Signal Output Timing (2) (2CAS Refresh Cycle Priority Order: When there are simultaneous bus requests, the priority order is: (High) External bus master >...
Page 190 Section 7 Refresh Controller Self-Refresh Mode: Some DRAM devices have a self-refresh function. After the SRFMD bit is set to 1 in RFSHCR, when a transition to software standby mode occurs, the CAS and RAS outputs go low in that order so that the DRAM self-refresh function can be used. On exit from software standby mode, the CAS and RAS outputs both go high.
Page 191 Section 7 Refresh Controller Software Oscillator standby mode settling time φ High-impedance Address CS (RAS) RD (CAS) HWR (UW) High LWR (LW) High RFSH a. 2 mode (SRFMD = 1) Software Oscillator standby mode settling time φ High-impedance Address CS (RAS) (UCAS) (LCAS) RD (WE)
Page 192 Section 7 Refresh Controller Operation in Power-Down State: The refresh controller operates in sleep mode. It does not operate in hardware standby mode. In software standby mode RTCNT is initialized, but RFSHCR, RTMCSR bits 5 to 3, and RTCOR retain their settings prior to the transition to software standby mode.
Page 193 Section 7 Refresh Controller Set area 3 for 16-bit access Set P8 DDR to 1 for output Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H'23 in RFSHCR Wait for DRAM to be initialized DRAM can be accessed Figure 7.8 Setup Procedure for 2WE 1-Mbit DRAM (1-Mbyte Mode) Rev.
Page 194 Section 7 Refresh Controller Example 2: Connection to 2WE 4-Mbit DRAM (16-Mbyte Mode): Figure 7.9 shows typical interconnections to a single 2WE 4-Mbit DRAM, and the corresponding address map. Figure 7.10 shows a setup procedure to be followed by a program for this example. The DRAM in this example has 10-bit row addresses and 8-bit column addresses.
Page 195 Section 7 Refresh Controller Set area 3 for 16-bit access Set P8 DDR to 1 for output Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H'23 in RFSHCR Wait for DRAM to be initialized DRAM can be accessed Figure 7.10 Setup Procedure for 2WE 4-Mbit DRAM with 10-Bit Row Address and 8-Bit Column Address (16-Mbyte Mode) Rev.
Page 196 Section 7 Refresh Controller CAS 4-Mbit DRAM (16-Mbyte Mode): Figure 7.11 shows typical Example 3: Connection to 2CAS interconnections to a single 2CAS 4-Mbit DRAM, and the corresponding address map. Figure 7.12 shows a setup procedure to be followed by a program for this example. The DRAM in this example has 9-bit row addresses and 9-bit column addresses.
Page 197 Section 7 Refresh Controller Set area 3 for 16-bit access Set P8 DDR to 1 for output Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H'3B in RFSHCR Wait for DRAM to be initialized DRAM can be accessed CAS 4-Mbit DRAM with 9-Bit Row Address and 9-Bit Figure 7.12 Setup Procedure for 2CAS Column Address (16-Mbyte Mode)
Page 198 Section 7 Refresh Controller Example 4: Connection to Multiple 4-Mbit DRAM Chips (16-Mbyte Mode): Figure 7.13 shows an example of interconnections to two 2CAS 4-Mbit DRAM chips, and the corresponding address map. Up to four DRAM chips can be connected to area 3 by decoding upper address bits and A Figure 7.14 shows a setup procedure to be followed by a program for this example.
Page 199 Section 7 Refresh Controller Set area 3 for 16-bit access Set P8 DDR to 1 for CS output Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H'3F in RFSHCR Wait for DRAM to be initialized DRAM can be accessed CAS 4-Mbit DRAM Chips with 9-Bit Row Figure 7.14 Setup Procedure for Multiple 2CAS Address and 9-Bit Column Address (16-Mbyte Mode)
Page 200: Pseudo-Static Ram Refresh Control
Section 7 Refresh Controller 7.3.3 Pseudo-Static RAM Refresh Control Refresh Request Interval and Refresh Cycle Execution: The refresh request interval is determined as in a DRAM interface, by the settings of RTCOR and bits CKS2 to CKS0 in RTMCSR. The numbers of states required for pseudo-static RAM read/write cycles and refresh cycles are the same as for DRAM (see table 7.4).
Page 201 Section 7 Refresh Controller Refresh Cycle Priority Order: When there are simultaneous bus requests, the priority order is: (High) External bus master > refresh controller > DMA controller > CPU (Low) For details see section 6.3.7, Bus Arbiter Operation. Wait State Insertion: When bit AST3 is set to 1 in ASTCR, the wait state controller (WSC) can insert wait states into bus cycles and refresh cycles.
Page 202 Section 7 Refresh Controller Oscillator Software standby mode settling time φ High-impedance Address High High-impedance High-impedance High-impedance RFSH Figure 7.16 Signal Output Timing in Self-Refresh Mode (PSRAME = 1, DRAME = 0) Operation in Power-Down State: The refresh controller operates in sleep mode. It does not operate in hardware standby mode.
Page 203 Section 7 Refresh Controller Set P8 DDR to 1 for CS output Set RTCOR Set bits CKS2 to CKS0 in RTMCSR Write H'47 in RFSHCR Wait for PSRAM to be initialized PSRAM can be accessed Figure 7.18 Setup Procedure for Pseudo-Static RAM Rev.
Page 204: Interval Timer
Section 7 Refresh Controller 7.3.4 Interval Timer To use the refresh controller as an interval timer, clear the PSRAME and DRAME both to 0. After setting RTCOR, select a clock source with bits CKS2 to CKS0 in RTMCSR, and set the CMIE bit to 1.
Page 205 Section 7 Refresh Controller Contention between RTCNT Write and Counter Clear: If a counter clear signal occurs in the state of an RTCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure 7.20. RTCNT write cycle by CPU φ...
Page 206 Section 7 Refresh Controller Contention between RTCNT Write and Increment: If an increment pulse occurs in the T state of an RTCNT write cycle, writing takes priority and RTCNT is not incremented. See figure 7.21. RTCNT write cycle by CPU φ...
Page 207 Section 7 Refresh Controller Contention between RTCOR Write and Compare Match: If a compare match occurs in the T state of an RTCOR write cycle, writing takes priority and the compare match signal is inhibited. See figure 7.22. RTCOR write cycle by CPU φ...
Page 208 Section 7 Refresh Controller Table 7.9 Internal Clock Switchover and RTCNT Operation CKS2 to CKS0 Write Timing RTCNT Operation Low → low switchover * Old clock source New clock source RTCNT clock RTCNT N + 1 CKS bits rewritten Low → high switchover * Old clock source New clock...
Page 209 Section 7 Refresh Controller CKS2 to CKS0 Write Timing RTCNT Operation High → low switchover * Old clock source New clock source RTCNT clock RTCNT N + 1 N + 2 CKS bits rewritten High → high switchover Old clock source New clock source...
Page 210: Interrupt Source
Section 7 Refresh Controller Interrupt Source Compare match interrupts (CMI) can be generated when the refresh controller is used as an interval timer. Compare match interrupt requests are masked/unmasked with the CMIE bit of RTMCSR. Usage Notes When using the DRAM or pseudo-static RAM refresh function, note the following points: With the refresh controller, if directly connected DRAM or PSRAM is disconnected*, the /RFSH/IRQ pin and the P8...
Page 211 Section 7 Refresh Controller Bus-released state Refresh cycle CPU cycle Refresh cycle φ RFSH Refresh request BACK Figure 7.24 Refresh Cycles when Bus Is Released If a bus cycle is prolonged by insertion of wait states, the first refresh request is held, as in the bus- released state.
Page 212 Section 7 Refresh Controller External bus Software standby mode released state φ BREQ BACK Address bus Strobe Figure 7.25 Contention between Bus-Released State and Software Standby Mode Rev. 3.00 Mar 21, 2006 page 184 of 814 REJ09B0302-0300...
Page 213: Section 8 Dma Controller
Section 8 DMA Controller Section 8 DMA Controller Overview The H8/3052BF has an on-chip DMA controller (DMAC) that can transfer data on up to four channels. When the DMA controller is not used, it can be independently halted to conserve power. For details see section 20.6, Module Standby Function.
Page 214: Block Diagram
Section 8 DMA Controller 8.1.2 Block Diagram Figure 8.1 shows a DMAC block diagram. Internal address bus Address buffer Internal IMIA0 interrupts IMIA1 Arithmetic-logic unit IMIA2 IMIA3 TXI0 MAR0A RXI0 Channel IOAR0A ETCR0A Channel DREQ0 Control logic DREQ1 MAR0B TEND0 Channel IOAR0B TEND1...
Page 215: Functional Overview
Section 8 DMA Controller 8.1.3 Functional Overview Table 8.1 gives an overview of the DMAC functions. Table 8.1 DMAC Functional Overview Address Reg. Length Transfer Mode Activation Source Destination • Short I/O mode Compare match/ address input capture A • Transfers one byte or one word mode interrupts from ITU...
Page 216 Section 8 DMA Controller Address Reg. Length Transfer Mode Activation Source Destination Full Normal mode • Auto-request address • • Auto-request External request mode  Retains the transfer request internally  Executes a specified number (1 to 65,536) of transfers continuously ...
Page 217: Pin Configuration
Section 8 DMA Controller 8.1.4 Pin Configuration Table 8.2 lists the DMAC pins. Table 8.2 DMAC Pins Abbre- Input/ Channel Name viation Output Function DREQ DMA request 0 Input External request for DMAC channel 0 TEND Transfer end 0 Output Transfer end on DMAC channel 0 DREQ DMA request 1...
Page 218 Section 8 DMA Controller Table 8.3 DMAC Registers Address * Channel Name Abbreviation Initial Value H'FF20 Memory address register 0AR MAR0AR Undetermined H'FF21 Memory address register 0AE MAR0AE Undetermined H'FF22 Memory address register 0AH MAR0AH Undetermined H'FF23 Memory address register 0AL MAR0AL Undetermined H'FF26...
Page 219: Register Descriptions (Short Address Mode)
Section 8 DMA Controller Register Descriptions (Short Address Mode) In short address mode, transfers can be carried out independently on channels A and B. Short address mode is selected by bits DTS2A and DTS1A in data transfer control register A (DTCRA) as indicated in table 8.4.
Page 220: Memory Address Registers (Mar)
Section 8 DMA Controller 8.2.1 Memory Address Registers (MAR) A memory address register (MAR) is a 32-bit readable/writable register that specifies a source or destination address. The transfer direction is determined automatically from the activation source. An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits of MARR are reserved: they cannot be modified and always return an undetermined value when read.
Page 221: I/O Address Registers (Ioar)
Section 8 DMA Controller 8.2.2 I/O Address Registers (IOAR) An I/O address register (IOAR) is an 8-bit readable/writable register that specifies a source or destination address. The IOAR value is the lower 8 bits of the address. The upper 16 address bits are all 1 (H'FFFF).
Page 222: Execute Transfer Count Registers (Etcr)
Section 8 DMA Controller 8.2.3 Execute Transfer Count Registers (ETCR) An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the number of transfers to be executed. These registers function in one way in I/O mode and idle mode, and another way in repeat mode.
Page 223: Data Transfer Control Registers (Dtcr)
Section 8 DMA Controller In repeat mode, ETCRH functions as an 8-bit transfer counter and ETCRL holds the initial transfer count. ETCRH is decremented by 1 each time one transfer is executed. When ETCRH reaches H'00, the value in ETCRL is reloaded into ETCRH and the same operation is repeated. The ETCRs are not initialized by a reset or in standby mode.
Page 224 Section 8 DMA Controller If DTIE is set to 1, a CPU interrupt is requested when DTE is cleared to 0. Bit 6—Data Transfer Size (DTSZ): Selects the data size of each transfer. Bit 6: DTSZ Description Byte-size transfer (Initial value) Word-size transfer Bit 5—Data Transfer Increment/Decrement (DTID): Selects whether to increment or decrement the memory address register (MAR) after a data transfer in I/O mode or repeat mode.
Page 225 Section 8 DMA Controller Bits 2 to 0—Data Transfer Select (DTS2, DTS1, DTS0): These bits select the data transfer activation source. Some of the selectable sources differ between channels A and B. Note: Refer to 8.3.4, Data Transfer Control Registers (DTCR). Bit 2: DTS2 Bit 1: DTS1 Bit 0: DTS0...
Page 226: Register Descriptions (Full Address Mode)
Section 8 DMA Controller Register Descriptions (Full Address Mode) In full address mode the A and B channels operate together. Full address mode is selected as indicated in table 8.4. 8.3.1 Memory Address Registers (MAR) A memory address register (MAR) is a 32-bit readable/writable register. MARA functions as the source address register of the transfer, and MARB as the destination address register.
Page 227: I/O Address Registers (Ioar)
Section 8 DMA Controller 8.3.2 I/O Address Registers (IOAR) The I/O address registers (IOARs) are not used in full address mode. 8.3.3 Execute Transfer Count Registers (ETCR) An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the number of transfers to be executed.
Page 228 Section 8 DMA Controller • Block transfer mode ETCRA Initial value Undetermined Read/Write ETCRAH Block size counter Initial value Undetermined Read/Write ETCRAL Initial block size ETCRB Undetermined Initial value Read/Write Block transfer counter In block transfer mode, ETCRAH functions as an 8-bit block size counter. ETCRAL holds the initial block size.
Page 229: Data Transfer Control Registers (Dtcr)
Section 8 DMA Controller 8.3.4 Data Transfer Control Registers (DTCR) The data transfer control registers (DTCRs) are 8-bit readable/writable registers that control the operation of the DMAC channels. A channel operates in full address mode when bits DTS2A and DTS1A are both set to 1 in DTCRA. DTCRA and DTCRB have different functions in full address mode.
Page 230 Section 8 DMA Controller Bit 7—Data Transfer Enable (DTE): Together with the DTME bit in DTCRB, this bit enables or disables data transfer on the channel. When the DTME and DTE bits are both set to 1, the channel is enabled. If auto-request is specified, data transfer begins immediately. Otherwise, the channel waits for transfers to be requested.
Page 231 Section 8 DMA Controller Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND) requested when the DTE bit is cleared to 0. Bit 3: DTIE Description The DEND interrupt requested by DTE is disabled (Initial value) The DEND interrupt requested by DTE is enabled Bits 2 and 1—Data Transfer Select 2A and 1A (DTS2A, DTS1A): A channel operates in full address mode when DTS2A and DTS1A are both set to 1.
Page 232 Section 8 DMA Controller Bit 7—Data Transfer Master Enable (DTME): Together with the DTE bit in DTCRA, this bit enables or disables data transfer. When the DTME and DTE bits are both set to 1, the channel is enabled. When an NMI interrupt occurs DTME is cleared to 0, suspending the transfer so that the CPU can use the bus.
Page 233 Section 8 DMA Controller Bits 2 to 0—Data Transfer Select 2B to 0B (DTS2B, DTS1B, DTS0B): These bits select the data transfer activation source. The selectable activation sources differ between normal mode and block transfer mode. • Normal mode Bit 2: Bit 1: Bit 0: DTS2B...
Page 234: Operation
Section 8 DMA Controller Operation 8.4.1 Overview Table 8.5 summarizes the DMAC modes. Table 8.5 DMAC Modes Transfer Mode Activation Notes • Short address I/O mode Compare match/input Up to four channels can mode capture A interrupt from operate independently Idle mode ITU channels 0 to 3 •...
Page 235 Section 8 DMA Controller Normal Mode • Auto-request The DMAC is activated by register setup alone, and continues executing transfers until the designated number of transfers have been completed. A CPU interrupt can be requested at completion of the transfers. Both addresses are 24-bit addresses. ...
Page 236: I/O Mode
Section 8 DMA Controller 8.4.2 I/O Mode I/O mode can be selected independently for each channel. One byte or word is transferred at each transfer request in I/O mode. A designated number of these transfers are executed. One address is specified in the memory address register (MAR), the other in the I/O address register (IOAR).
Page 237 Section 8 DMA Controller Figure 8.2 illustrates how I/O mode operates. Transfer Address T IOAR 1 byte or word is transferred per request Address B Legend: L = initial setting of MAR N = initial setting of ETCR Address T = L ⋅...
Page 238: Idle Mode
Section 8 DMA Controller For the detailed settings see section 8.2.4, Data Transfer Control Registers (DTCR). Figure 8.3 shows a sample setup procedure for I/O mode. 1. Set the source and destination addresses I/O mode setup in MAR and IOAR. The transfer direction is determined automatically from the activation source.
Page 239 Section 8 DMA Controller Table 8.7 Register Functions in Idle Mode Function Activated by SCI 0 Receive- Data-Full Other Register Interrupt Activation Initial Setting Operation Destination Source Destination or Held fixed address address source address register register Source Destination Source or Held fixed address address...
Page 240 Section 8 DMA Controller The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared, the transfer ends, and a CPU interrupt is requested.
Page 241: Repeat Mode
Section 8 DMA Controller 8.4.4 Repeat Mode Repeat mode is useful for cyclically transferring a bit pattern from a table to the programmable timing pattern controller (TPC) in synchronization, for example, with ITU compare match. Repeat mode can be selected for each channel independently. One byte or word is transferred per request in repeat mode, as in I/O mode.
Page 242 Section 8 DMA Controller Table 8.8 Register Functions in Repeat Mode Function Activated by SCI 0 Receive- Data-Full Other Register Interrupt Activation Initial Setting Operation Destination Source Destination or Incremented or address address source address decremented at register register each transfer until H'0000, then restored to initial value...
Page 243 Section 8 DMA Controller As in I/O mode, MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not incremented or decremented. Figure 8.6 illustrates how repeat mode operates.
Page 244 Section 8 DMA Controller Figure 8.7 shows a sample setup procedure for repeat mode. 1. Set the source and destination addresses Repeat mode in MAR and IOAR. The transfer direction is determined automatically from the activation source. Set source and destination addresses 2.
Page 245: Normal Mode
Section 8 DMA Controller 8.4.5 Normal Mode In normal mode the A and B channels are combined. One byte or word is transferred per request. A designated number of these transfers are executed. Addresses are specified in MARA and MARB. Table 8.9 indicates the register functions in I/O mode. Table 8.9 Register Functions in Normal Mode Register...
Page 246 Section 8 DMA Controller Address T Transfer Address T Address B Address B Legend: = initial setting of MARA = initial setting of MARB = initial setting of ETCRA SAID DTSZ = L + SAIDE (–1) N – 1) • •...
Page 247 Section 8 DMA Controller Figure 8.9 shows a sample setup procedure for normal mode. 1. Set the initial source address in MARA. Normal mode 2. Set the initial destination address in MARB. 3. Set the transfer count in ETCRA. Set initial source address 4.
Page 248: Block Transfer Mode
Section 8 DMA Controller 8.4.6 Block Transfer Mode In block transfer mode the A and B channels are combined. One block of a specified size is transferred per request. A designated number of block transfers are executed. Addresses are specified in MARA and MARB. The block area address can be either held fixed or cycled. Table 8.10 indicates the register functions in block transfer mode.
Page 249 Section 8 DMA Controller If M (1 to 255) is the size of the block transferred at each request and N (1 to 65,536) is the number of blocks to be transferred, then ETCRAH and ETCRAL should initially be set to M and ETCRB should initially be set to N.
Page 250 Section 8 DMA Controller When activated by a transfer request, the DMAC executes a burst transfer. During the transfer MARA and MARB are updated according to the DTCR settings, and ETCRAH is decremented. When ETCRAH reaches H'00, it is reloaded from ETCRAL to restore the initial value. The memory address register of the block area is also restored to its initial value, and ETCRB is decremented.
Page 251 Section 8 DMA Controller Start Start (DTE = DTME = 1) (DTE = DTME = 1) Transfer requested? Transfer requested? Get bus Get bus Read from MARA address Read from MARA address MARA = MARA + 1 MARA = MARA + 1 Write to MARB address Write to MARB address MARB = MARB + 1...
Page 252 Section 8 DMA Controller Figure 8.12 shows a sample setup procedure for block transfer mode. 1. Set the source address in MARA. Block transfer mode 2. Set the destination address in MARB. 3. Set the block transfer count in ETCRB. Set source address 4.
Page 253: Dmac Activation
Section 8 DMA Controller 8.4.7 DMAC Activation The DMAC can be activated by an internal interrupt, external request, or auto-request. The available activation sources differ depending on the transfer mode and channel as indicated in table 8.11. Table 8.11 DMAC Activation Sources Short Address Mode Full Address Mode Channels...
Page 254 Section 8 DMA Controller Activation by External Request: If an external request (DREQ pin) is selected as an activation source, the DREQ pin becomes an input pin and the corresponding TEND pin becomes an output pin, regardless of the port data direction register (DDR) settings. The DREQ input can be level- sensitive or edge-sensitive.
Page 255: Dmac Bus Cycle
Section 8 DMA Controller 8.4.8 DMAC Bus Cycle Figure 8.13 shows an example of the timing of the basic DMAC bus cycle. This example shows a word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the DMAC gets the bus from the CPU, after one dead cycle (Td), it reads from the source address and writes to the destination address.
Page 256 Section 8 DMA Controller Figure 8.14 shows the timing when the DMAC is activated by low input at a DREQ pin. This example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-state access area. The DMAC continues the transfer while the DREQ pin is held low. DMAC cycle CPU cycle DMAC cycle...
Page 257 Section 8 DMA Controller Figure 8.15 shows an auto-requested burst-mode transfer. This example shows a transfer of three words from a 16-bit two-state access area to another 16-bit two-state access area. CPU cycle DMAC cycle CPU cycle φ Source Destination address address Address...
Page 258 Section 8 DMA Controller Figure 8.16 shows the timing when the DMAC is activated by the falling edge of DREQ in normal mode. CPU cycle DMAC cycle cycle DMAC cycle φ DREQ Address HWR, LWR Minimum 4 states Next sampling point Figure 8.16 Timing of DMAC Activation by Falling Edge of DREQ DREQ in Normal Mode DREQ...
Page 259 Section 8 DMA Controller Figure 8.17 shows the timing when the DMAC is activated by level-sensitive low DREQ input in normal mode. CPU cycle DMAC cycle CPU cycle φ DREQ Address Minimum 4 states Next sampling point Figure 8.17 Timing of DMAC Activation by Low DREQ DREQ Level in Normal Mode DREQ DREQ...
Page 260 Section 8 DMA Controller Figure 8.18 shows the timing when the DMAC is activated by the falling edge of DREQ in block transfer mode. End of 1 block transfer DMAC cycle CPU cycle DMAC cycle φ DREQ Address TEND Next sampling Minimum 4 states Figure 8.18 Timing of DMAC Activation by Falling Edge of DREQ DREQ in Block Transfer Mode...
Page 261: Dmac Multiple-Channel Operation
Section 8 DMA Controller 8.4.9 DMAC Multiple-Channel Operation The DMAC channel priority order is: channel 0 > channel 1 and channel A > channel B. Table 8.12 shows the complete priority order. Table 8.12 Channel Priority Order Short Address Mode Full Address Mode Priority Channel 0A...
Page 262: External Bus Requests, Refresh Controller, And Dmac
Section 8 DMA Controller DMAC cycle DMAC cycle DMAC cycle (channel 1) cycle (channel 0A) cycle (channel 1) φ Address Figure 8.19 Timing of Multiple-Channel Operations 8.4.10 External Bus Requests, Refresh Controller, and DMAC During a DMA transfer, if the bus right is requested by an external bus request signal (BREQ) or by the refresh controller, the DMAC releases the bus after completing the transfer of the current byte or word.
Page 263: Nmi Interrupts And Dmac
Section 8 DMA Controller 8.4.11 NMI Interrupts and DMAC NMI interrupts do not affect DMAC operations in short address mode. If an NMI interrupt occurs during a transfer in full address mode, the DMAC suspends operations. In full address mode, a channel is enabled when its DTE and DTME bits are both set to 1. NMI input clears the DTME bit to 0.
Page 264: Aborting A Dma Transfer
Section 8 DMA Controller 8.4.12 Aborting a DMA Transfer When the DTE bit in an active channel is cleared to 0, the DMAC halts after transferring the current byte or word. The DMAC starts again when the DTE bit is set to 1. In full address mode, the DTME bit can be used for the same purpose.
Page 265: Exiting Full Address Mode
Section 8 DMA Controller 8.4.13 Exiting Full Address Mode Figure 8.23 shows the procedure for exiting full address mode and initializing the pair of channels. To set the channels up in another mode after exiting full address mode, follow the setup procedure for the relevant mode.
Page 266: Dmac States In Reset State, Standby Modes, And Sleep Mode
Section 8 DMA Controller 8.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode When the chip is reset or enters hardware or software standby mode, the DMAC is initialized and halts. DMAC operations continue in sleep mode. Figure 8.24 shows the timing of a cycle-steal transfer in sleep mode.
Page 267: Interrupts
Section 8 DMA Controller Interrupts The DMAC generates only DMA-end interrupts. Table 8.13 lists the interrupts and their priority. Table 8.13 DMAC Interrupts Description Interrupt Interrupt Short Address Mode Full Address Mode Priority DEND0A End of transfer on channel 0A End of transfer on channel 0 High ↑...
Page 268: Usage Notes
Section 8 DMA Controller Usage Notes 8.6.1 Note on Word Data Transfer Word data cannot be accessed starting at an odd address. When word-size transfer is selected, set even values in the memory and I/O address registers (MAR and IOAR). 8.6.2 DMAC Self-Access The DMAC itself cannot be accessed during a DMAC cycle.
Page 269 Section 8 DMA Controller 1. While the DTE bit is cleared to Enabling of DMAC 0, interrupt requests are sent to the CPU. 2. Clear the interrupt enable bit to 0 in the interrupt-generating Selected interrupt on-chip supporting module. requested? Interrupt handling 3.
Page 270: Nmi Interrupts And Block Transfer Mode
Section 8 DMA Controller 8.6.6 NMI Interrupts and Block Transfer Mode If an NMI interrupt occurs in block transfer mode, the DMAC operates as follows. • When the NMI interrupt occurs, the DMAC finishes transferring the current byte or word, then clears the DTME bit to 0 and halts.
Page 271: Bus Cycle When Transfer Is Aborted
Section 8 DMA Controller 8.6.8 Bus Cycle when Transfer Is Aborted When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME bit, if this halts a channel for which the DMAC has a transfer request pending internally, a dead cycle may occur.
Page 272 Section 8 DMA Controller Rev. 3.00 Mar 21, 2006 page 244 of 814 REJ09B0302-0300...
Page 273: Section 9 I/O Ports
Section 9 I/O Ports Section 9 I/O Ports Overview The H8/3052BF has 10 input/output ports (ports 1, 2, 3, 4, 5, 6, 8, 9, A, and B) and one input port (port 7). Table 9.1 summarizes the port functions. The pins in each port are multiplexed as shown in table 9.1.
Page 274 Section 9 I/O Ports Table 9.1 Port Functions Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Port 1 • 8-bit I/O port to P1 Address output pins (A to A Address output (A Generic to A to A...
Page 275 Section 9 I/O Ports Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Port 8 • 5-bit I/O port DDR = 0: generic input Generic input/ DDR = 1 (reset value): CS •...
Page 276 Section 9 I/O Ports Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 , TEND Port A • 8-bit I/O port TPC output (TP to TP ), output (TEND ) from DMA controller TIOCB (DMAC), ITU input and output (TCLKD, TCLKC, TCLKB, TCLKA, •...
Page 277: Port 1
Section 9 I/O Ports Port 1 9.2.1 Overview Port 1 is an 8-bit input/output port with the pin configuration shown in figure 9.1. The pin functions differ between the expanded modes with on-chip ROM disabled, expanded modes with on-chip ROM enabled, and single-chip mode. In modes 1 to 4 (expanded modes with on-chip ROM disabled), they are address bus output pins (A to A In modes 5 and 6 (expanded modes with on-chip ROM enabled), settings in the port 1 data...
Page 278 Section 9 I/O Ports 9.2.2 Register Configuration Table 9.2 summarizes the registers of port 1. Table 9.2 Port 1 Registers Initial Value Address * Name Abbreviation Modes 1 to 4 Modes 5 to 7 H'FFC0 Port 1 data direction P1DDR H'FF H'00 register...
Page 279 Section 9 I/O Ports P1DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. If a P1DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode.
Page 280: Overview
Section 9 I/O Ports Port 2 9.3.1 Overview Port 2 is an 8-bit input/output port with the pin configuration shown in figure 9.2. The pin functions differ according to the operating mode. In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 2 consists of address bus output pins (A to A ).
Page 281: Register Configuration
Section 9 I/O Ports 9.3.2 Register Configuration Table 9.3 summarizes the registers of port 2. Table 9.3 Port 2 Registers Initial Value Address * Name Abbreviation Modes 1 to 4 Modes 5 to 7 H'FFC1 Port 2 data direction P2DDR H'FF H'00 register...
Page 282 Section 9 I/O Ports In modes 5 to 7, P2DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P2DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting.
Page 283 Section 9 I/O Ports P2PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Table 9.4 Input Pull-Up MOS States (Port 2) Hardware Software Mode Reset Standby Mode Standby Mode Other Modes On/off...
Page 284: Port 3
Section 9 I/O Ports Port 3 9.4.1 Overview Port 3 is an 8-bit input/output port with the pin configuration shown in figure 9.3. Port 3 is a data bus in modes 1 to 6 (expanded modes) and a generic input/output port in mode 7 (single-chip mode).
Page 285 Section 9 I/O Ports Port 3 Data Direction Register (P3DDR) P3DDR is an 8-bit write-only register that can select input or output for each pin in port 3. P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR Initial value...
Page 286: Port 4
Section 9 I/O Ports Port 4 9.5.1 Overview Port 4 is an 8-bit input/output port with the pin configuration shown in figure 9.4. The pin functions differ according to the operating mode. In modes 1 to 6 (expanded modes), when the bus width control register (ABWCR) designates areas 0 to 7 all as 8-bit-access areas, the chip operates in 8-bit bus mode and port 4 is a generic input/output port.
Page 287 Section 9 I/O Ports 9.5.2 Register Configuration Table 9.6 summarizes the registers of port 4. Table 9.6 Port 4 Registers Address * Name Abbreviation Initial Value H'FFC5 Port 4 data direction register P4DDR H'00 H'FFC7 Port 4 data register P4DR H'00 H'FFDA Port 4 input pull-up MOS control...
Page 288 Section 9 I/O Ports ABWCR and P4DDR are not initialized in software standby mode. When port 4 functions as a generic input/output port, if a P4DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. Port 4 Data Register (P4DR) P4DR is an 8-bit readable/writable register that stores output data for pins P4 to P4...
Page 289 Section 9 I/O Ports Table 9.7 summarizes the states of the input pull-ups MOS in the 8-bit and 16-bit bus modes. Table 9.7 Input Pull-Up MOS Transistor States (Port 4) Hardware Software Mode Reset Standby Mode Standby Mode Other Modes 1 to 6 8-bit bus mode On/off...
Page 290: Port 5
Section 9 I/O Ports Port 5 9.6.1 Overview Port 5 is a 4-bit input/output port with the pin configuration shown in figure 9.5. The pin functions differ depending on the operating mode. In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 5 consists of address output pins (A to A ).
Page 291 Section 9 I/O Ports 9.6.2 Register Configuration Table 9.8 summarizes the registers of port 5. Table 9.8 Port 5 Registers Initial Value Address * Name Abbreviation Modes 1 to 4 Modes 5 to 7 H'FFC8 Port 5 data direction P5DDR H'FF H'F0 register...
Page 292 Section 9 I/O Ports P5DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P5DDR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting, so if a P5DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode.
Page 293 Section 9 I/O Ports In modes 5 to 7, when a P5DDR bit is cleared (selecting the input port function), if the corresponding bit in P5PCR is set up 1, the input pull-up MOS transistor is turned on. P5PCR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting.
Page 294: Port 6
Section 9 I/O Ports Port 6 9.7.1 Overview Port 6 is a 7-bit input/output port that is also used for input and output of bus control signals (LWR, HWR, RD, AS, BACK, BREQ, and WAIT). When DRAM is connected to area 3, LWR, HWR, and RD also function as LW, UW, and CAS, or LCAS, UCAS, and WE, respectively.
Page 295: Register Configuration
Section 9 I/O Ports 9.7.2 Register Configuration Table 9.10 summarizes the registers of port 6. Table 9.10 Port 6 Registers Initial Value Address * Name Abbreviation Mode 1 to 5 Mode 6, 7 H'FFC9 Port 6 data direction P6DDR H'F8 H'80 register H'FFCB...
Page 296 Section 9 I/O Ports Port 6 Data Register (P6DR) P6DR is an 8-bit readable/writable register that stores output data for pins P6 to P6 . When this register is read, the pin logic level is read for a bit with the corresponding P6DDR bit cleared to 0, and the P6DR value is read for a bit with the corresponding P6DDR bit set to 1.
Page 297 Section 9 I/O Ports Pin Functions and Selection Method Functions as follows regardless of P6 AS output Pin function /BACK Bit BRLE in BRCR and bit P6 DDR select the pin function as follows BRLE — BACK output Pin function input output /BREQ...
Page 298: Port 7
Section 9 I/O Ports Port 7 9.8.1 Overview Port 7 is an 8-bit input port that is also used for analog input to the A/D converter and analog output from the D/A converter. The pin functions are the same in all operating modes. Figure 9.7 shows the pin configuration of port 7.
Page 299: Register Configuration
Section 9 I/O Ports 9.8.2 Register Configuration Table 9.12 summarizes the port 7 register. Port 7 is an input-only port, so it has no data direction register. Table 9.12 Port 7 Data Register Address * Name Abbreviation Initial Value H'FFCE Port 7 data register P7DR Undetermined...
Page 300: Port 8
Section 9 I/O Ports Port 8 9.9.1 Overview Port 8 is a 5-bit input/output port that is also used for CS to CS output, RFSH output, and IRQ to IRQ input. Figure 9.8 shows the pin configuration of port 8. In modes 1 to 6 (expanded modes), port 8 can provide CS to CS output, RFSH output, and IRQ...
Page 301: Register Configuration
Section 9 I/O Ports 9.9.2 Register Configuration Table 9.13 summarizes the registers of port 8. Table 9.13 Port 8 Registers Initial Value Address * Name Abbreviation Mode 1 to 4 Mode 5 to 7 H'FFCD Port 8 data direction P8DDR H'F0 H'E0 register...
Page 302 Section 9 I/O Ports • Mode 7 (Single-Chip Mode) Port 8 is a generic input/output port. A pin in port 8 becomes an output port if the corresponding P8DDR bit is set to 1, and an input port if this bit is cleared to 0. P8DDR is a write-only register.
Page 303 Section 9 I/O Ports Table 9.14 Port 8 Pin Functions in Modes 1 to 6 Pin Functions and Selection Method Bit P8 DDR selects the pin function as follows Pin function input output /IRQ Bit P8 DDR selects the pin function as follows Pin function input output...
Page 304 Section 9 I/O Ports Table 9.15 Port 8 Pin Functions in Mode 7 Pin Functions and Selection Method Bit P8 DDR selects the pin function as follows Pin function input output /IRQ Bit P8 DDR selects the pin function as follows Pin function input output...
Page 305: Port 9
Section 9 I/O Ports 9.10 Port 9 9.10.1 Overview Port 9 is a 6-bit input/output port that is also used for input and output (TxD , TxD , RxD , RxD ) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for IRQ , SCK and IRQ input.
Page 306: Register Configuration
Section 9 I/O Ports 9.10.2 Register Configuration Table 9.16 summarizes the registers of port 9. Table 9.16 Port 9 Registers Address * Name Abbreviation Initial Value H'FFD0 Port 9 data direction register P9DDR H'C0 H'FFD2 Port 9 data register P9DR H'C0 Note: * Lower 16 bits of the address.
Page 307 Section 9 I/O Ports Port 9 Data Register (P9DR) P9DR is an 8-bit readable/writable register that stores output data for pins P9 to P9 . When a bit in P9DDR is set to 1, if port 9 is read the value of the corresponding P9DR bit is returned. When a bit in P9DDR is cleared to 0, if port 9 is read the corresponding pin level is read.
Page 308 Section 9 I/O Ports Table 9.17 Port 9 Pin Functions Pin Functions and Selection Method /SCK /IRQ Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR of SCI1, and bit P9 select the pin function as follows CKE1 —...
Page 309: Port A
Section 9 I/O Ports Pin Functions and Selection Method /TxD Bit TE in SCR of SCI1 and bit P9 DDR select the pin function as follows — Pin function input output output /TxD Bit TE in SCR of SCI0, bit SMIF in SCMR, and bit P9 DDR select the pin function as follows SMIF...
Page 310 Section 9 I/O Ports Port A pins PA /TP /TIOCB /A PA /TP /TIOCA /A PA /TP /TIOCB /A PA /TP /TIOCA /A Port A PA /TP /TIOCB /TCLKD PA /TP /TIOCA /TCLKC PA /TP /TEND /TCLKB PA /TP /TEND /TCLKA Pin functions in modes 1, 2, and 5 PA (input/output)/TP (output)/TIOCB (input/output) PA (input/output)/TP (output)/TIOCA (input/output)/CS...
Page 311: Register Configuration
Section 9 I/O Ports 9.11.2 Register Configuration Table 9.18 summarizes the registers of port A. Table 9.18 Port A Registers Initial Value Modes Modes Address * Name Abbreviation 1, 2, 5 and 7 3, 4, and 6 H'FFD1 Port A data direction PADDR H'00 H'80...
Page 312 Section 9 I/O Ports Port A Data Register (PADR) PADR is an 8-bit readable/writable register that stores output data for pins PA to PA . When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned. When a bit in PADDR is cleared to 0, if port A is read the corresponding pin level is read.
Page 313: Pin Functions
Section 9 I/O Ports 9.11.3 Pin Functions Table 9.19 describes the selection of pin functions. Table 9.19 Port A Pin Functions Pin Functions and Selection Method The mode setting, ITU channel 2 settings (bit PWM2 in TMDR and bits IOB2 to IOB0 in TIOCB TIOR2), bit NDER7 in NDERA, and bit PA DDR in PADDR select the pin function as...
Page 314 Section 9 I/O Ports Pin Functions and Selection Method The mode setting, bit A E in BRCR, bit CS4E in CSCR, ITU channel 2 settings (bit TIOCA PWM2 in TMDR and bits IOA2 to IOA0 in TIOR2), bit NDER6 in NDERA, and bit DDR in PADDR select the pin function as follows Mode 1, 2, 5...
Page 315 Section 9 I/O Ports Pin Functions and Selection Method The mode setting, bit A E in BRCR, bit CS5E in CSCR, ITU channel 1 settings (bit TIOCB PWM1 in TMDR and bits IOB2 to IOB0 in TIOR1), bit NDER5 in NDERA, and bit DDR in PADDR select the pin function as follows Mode 1, 2, 5...
Page 316 Section 9 I/O Ports Pin Functions and Selection Method The mode setting, bit A E in BRCR, bit CS6E in CSCR, ITU channel 1 settings (bit TIOCA PWM1 in TMDR and bits IOA2 to IOA0 in TIOR1), bit NDER4 in NDERA, and bit DDR in PADDR select the pin function as follows Mode 1, 2, 5...
Page 317 Section 9 I/O Ports Pin Functions and Selection Method ITU channel 0 settings (bit PWM0 in TMDR and bits IOB2 to IOB0 in TIOR0), bits TIOCB TPSC2 to TPSC0 in TCR4 to TCR0, bit NDER3 in NDERA, and bit PA DDR in PADDR TCLKD select the pin function as follows...
Page 318 Section 9 I/O Ports Pin Functions and Selection Method ITU channel 0 settings (bit PWM0 in TMDR and bits IOA2 to IOA0 in TIOR0), bits TIOCA TPSC2 to TPSC0 in TCR4 to TCR0, bit NDER2 in NDERA, and bit PA DDR in PADDR TCLKC select the pin function as follows...
Page 319 Section 9 I/O Ports Pin Functions and Selection Method DMAC channel 1 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR1A and DTCR1B), TCLKB/ bit NDER1 in NDERA, and bit PA DDR in PADDR select the pin function as follows TEND DMAC (1) in table (2) in table channel 1...
Page 320 Section 9 I/O Ports Pin Functions and Selection Method DMAC channel 0 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR0A and DTCR0B), TCLKA/ bit NDER0 in NDERA, and bit PA DDR in PADDR select the pin function as follows TEND DMAC (1) in table (2) in table channel 0...
Page 321: Port B
Section 9 I/O Ports 9.12 Port B 9.12.1 Overview Port B is an 8-bit input/output port that is also used for output (TP to TP ) from the programmable timing pattern controller (TPC), input/output (TIOCB , TIOCB , TIOCA TIOCA ) and output (TOCXB , TOCXA ) by the 16-bit integrated timer unit (ITU), input...
Page 322 Section 9 I/O Ports Port B pins /DREQ /ADTRG /DREQ /TOCXB /TOCXA Port B /TIOCB /TIOCA /TIOCB /TIOCA Pin functions in modes 1 to 6 (input/output)/TP (output)/DREQ (input)/ADTRG (input) (input/output)/TP (output)/DREQ (input)/CS (output) (input/output)/TP (output)/TOCXB (output) (input/output)/TP (output)/TOCXA (output) (input/output)/TP (output)/TIOCB (input/output) (input/output)/TP...
Page 323: Register Configuration
Section 9 I/O Ports 9.12.2 Register Configuration Table 9.20 summarizes the registers of port B. Table 9.20 Port B Registers Address * Name Abbreviation Initial Value H'FFD4 Port B data direction register PBDDR H'00 H'FFD6 Port B data register PBDR H'00 Note: * Lower 16 bits of the address.
Page 324 Section 9 I/O Ports Port B Data Register (PBDR) PBDR is an 8-bit readable/writable register that stores output data for pins PB7 to PB0. When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is returned. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin level is read.
Page 325: Pin Functions
Section 9 I/O Ports 9.12.3 Pin Functions Table 9.21 describes the selection of pin functions. Table 9.21 Port B Pin Functions Pin Functions and Selection Method DMAC channel 1 settings (bits DTS2/1/0A and DTS2/1/0B in DTCR1A and DTCR1B), DREQ bit TRGE in ADCR, bit NDER15 in NDERB, and bit PB DDR in PBDDR select the pin ADTRG function as follows...
Page 326 Section 9 I/O Ports Pin Functions and Selection Method Bit CS7E in CSCR, DMAC channel 0 settings (bits DTS2/1/0A and DTS2/1/0B in DREQ DTCR0A and DTCR0B), bit NDER14 in NDERB, and bit PB DDR in PBDDR select the pin function as follows —...
Page 327 Section 9 I/O Ports Pin Functions and Selection Method ITU channel 4 settings (bit PWM4 in TMDR, bit CMD1 in TFCR, bit EB4 in TOER, and TIOCB bits IOB2 to IOB0 in TIOR4), bit NDER11 in NDERB, and bit PB DDR in PBDDR select the pin function as follows ITU channel 4...
Page 328 Section 9 I/O Ports Pin Functions and Selection Method ITU channel 4 settings (bit CMD1 in TFCR, bit EA4 in TOER, bit PWM4 in TMDR, and TIOCA bits IOA2 to IOA0 in TIOR4), bit NDER10 in NDERB, and bit PB DDR in PBDDR select the pin function as follows ITU channel 4...
Page 329 Section 9 I/O Ports Pin Functions and Selection Method ITU channel 3 settings (bit PWM3 in TMDR, bit CMD1 in TFCR, bit EB3 in TOER, and TIOCB bits IOB2 to IOB0 in TIOR3), bit NDER9 in NDERB, and bit PB DDR in PBDDR select the pin function as follows ITU channel 3...
Page 330 Section 9 I/O Ports Pin Functions and Selection Method ITU channel 3 settings (bit CMD1 in TFCR, bit EA3 in TOER, bit PWM3 in TMDR, and TIOCA bits IOA2 to IOA0 in TIOR3), bit NDER8 in NDERB, and bit PB DDR in PBDDR select the pin function as follows ITU channel 3...
Page 331: Section 10 16-Bit Integrated Timer Unit (Itu)
Section 10 16-Bit Integrated Timer Unit (ITU) Section 10 16-Bit Integrated Timer Unit (ITU) 10.1 Overview The H8/3052BF has a built-in 16-bit integrated timer unit (ITU) with five 16-bit timer channels. When the ITU is not used, it can be independently halted to conserve power. For details see section 20.6, Module Standby Function.
Page 332 Section 10 16-Bit Integrated Timer Unit (ITU) • Three additional modes selectable in channels 3 and 4  Reset-synchronized PWM mode If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of complementary waveforms.  Complementary PWM mode If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of non-overlapping complementary waveforms.
Page 333 Section 10 16-Bit Integrated Timer Unit (ITU) Table 10.1 summarizes the ITU functions. Table 10.1 ITU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Internal clocks: φ, φ/2, φ/4, φ/8 Clock sources External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable independently General registers GRA0, GRB0 GRA1, GRB1...
Page 334: Block Diagrams
Section 10 16-Bit Integrated Timer Unit (ITU) 10.1.2 Block Diagrams ITU Block Diagram (Overall): Figure 10.1 is a block diagram of the ITU. IMIA0 to IMIA4 TCLKA to TCLKD Clock selector IMIB0 to IMIB4 φ, φ/2, φ/4, φ/8 OVI0 to OVI4 Control logic TOCXA , TOCXB...
Page 335 Section 10 16-Bit Integrated Timer Unit (ITU) Block Diagram of Channels 0 and 1: ITU channels 0 and 1 are functionally identical. Both have the structure shown in figure 10.2. TCLKA to TCLKD TIOCA Clock selector TIOCB φ, φ/2, φ/4, φ/8 Control logic IMIA0 Comparator...
Page 336 Section 10 16-Bit Integrated Timer Unit (ITU) Block Diagram of Channel 2: Figure 10.3 is a block diagram of channel 2. This is the channel that provides only 0 output and 1 output. TCLKA to TCLKD TIOCA Clock selector TIOCB φ, φ/2, φ/4, φ/8 Control logic IMIA2...
Page 337 Section 10 16-Bit Integrated Timer Unit (ITU) Block Diagrams of Channels 3 and 4: Figure 10.4 is a block diagram of channel 3. Figure 10.5 is a block diagram of channel 4. TIOCA TCLKA to TIOCB TCLKD Clock selector φ, φ/2, φ/4, φ/8 Control logic IMIA3...
Page 338 Section 10 16-Bit Integrated Timer Unit (ITU) TOCXA TCLKA to TOCXB TCLKD Clock selector φ, φ/2, TIOCA φ/4, φ/8 TIOCB Control logic IMIA4 Comparator IMIB4 OVI4 Module data bus Legend: TCNT4: Timer counter 4 (16 bits) GRA4, GRB4: General registers A4 and B4 (input capture/output compare registers) ×...
Page 339: Pin Configuration
Section 10 16-Bit Integrated Timer Unit (ITU) 10.1.3 Pin Configuration Table 10.2 summarizes the ITU pins. Table 10.2 ITU Pins Abbre- Input/ Channel Name viation Output Function Common Clock input A TCLKA Input External clock A input pin (phase-A input pin in phase counting mode) Clock input B TCLKB Input...
Page 340: Register Configuration
Section 10 16-Bit Integrated Timer Unit (ITU) 10.1.4 Register Configuration Table 10.3 summarizes the ITU registers. Table 10.3 ITU Registers Abbre- Initial Address * Channel Name viation Value Common H'FF60 Timer start register TSTR H'E0 H'FF61 Timer synchro register TSNC H'E0 H'FF62 Timer mode register...
Page 341 Section 10 16-Bit Integrated Timer Unit (ITU) Abbre- Initial Address * viation Value Channel Name H'FF78 Timer control register 2 TCR2 H'80 H'FF79 Timer I/O control register 2 TIOR2 H'88 H'FF7A Timer interrupt enable register 2 TIER2 H'F8 R/(W) * H'FF7B Timer status register 2 TSR2...
Page 342 Section 10 16-Bit Integrated Timer Unit (ITU) Abbre- Initial Address * viation Value Channel Name H'FF92 Timer control register 4 TCR4 H'80 H'FF93 Timer I/O control register 4 TIOR4 H'88 H'FF94 Timer interrupt enable register 4 TIER4 H'F8 R/(W) * H'FF95 Timer status register 4 TSR4...
Page 343: Register Descriptions
Section 10 16-Bit Integrated Timer Unit (ITU) 10.2 Register Descriptions 10.2.1 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that starts and stops the timer counter (TCNT) in channels 0 to 4. — — — STR4 STR3 STR2 STR1 STR0 Initial value...
Page 344: Timer Synchro Register (Tsnc)
Section 10 16-Bit Integrated Timer Unit (ITU) Bit 1—Counter Start 1 (STR1): Starts and stops timer counter 1 (TCNT1). Bit 1: STR1 Description TCNT1 is halted (Initial value) TCNT1 is counting Bit 0—Counter Start 0 (STR0): Starts and stops timer counter 0 (TCNT0). Bit 0: STR0 Description TCNT0 is halted...
Page 345 Section 10 16-Bit Integrated Timer Unit (ITU) Bit 3—Timer Sync 3 (SYNC3): Selects whether channel 3 operates independently or synchronously. Bit 3: SYNC3 Description Channel 3’s timer counter (TCNT3) operates independently (Initial value) TCNT3 is preset and cleared independently of other channels Channel 3 operates synchronously TCNT3 can be synchronously preset and cleared Bit 2—Timer Sync 2 (SYNC2): Selects whether channel 2 operates independently or...
Page 346: Timer Mode Register (Tmdr)
Section 10 16-Bit Integrated Timer Unit (ITU) 10.2.3 Timer Mode Register (TMDR) TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 4. It also selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2. —...
Page 347 Section 10 16-Bit Integrated Timer Unit (ITU) When MDF is set to 1 to select phase counting mode, TCNT2 operates as an up/down-counter and pins TCLKA and TCLKB become counter clock input pins. TCNT2 counts both rising and falling edges of TCLKA and TCLKB, and counts up or down as follows. Counting Direction Down-Counting Up-Counting...
Page 348 Section 10 16-Bit Integrated Timer Unit (ITU) Bit 3—PWM Mode 3 (PWM3): Selects whether channel 3 operates normally or in PWM mode. Bit 3: PWM3 Description Channel 3 operates normally (Initial value) Channel 3 operates in PWM mode When bit PWM3 is set to 1 to select PWM mode, pin TIOCA becomes a PWM output pin.
Page 349: Timer Function Control Register (Tfcr)
Section 10 16-Bit Integrated Timer Unit (ITU) 10.2.4 Timer Function Control Register (TFCR) TFCR is an 8-bit readable/writable register that selects complementary PWM mode, reset- synchronized PWM mode, and buffering for channels 3 and 4. — — CMD1 CMD0 BFB4 BFA4 BFB3 BFA3...
Page 350 Section 10 16-Bit Integrated Timer Unit (ITU) Before selecting reset-synchronized PWM mode or complementary PWM mode, halt the timer counter or counters that will be used in these modes. When these bits select complementary PWM mode or reset-synchronized PWM mode, they take precedence over the setting of the PWM mode bits (PWM4 and PWM3) in TMDR.
Page 351: Timer Output Master Enable Register (Toer)
Section 10 16-Bit Integrated Timer Unit (ITU) 10.2.5 Timer Output Master Enable Register (TOER) TOER is an 8-bit readable/writable register that enables or disables output settings for channels 3 and 4. — — EXB4 EXA4 Initial value Read/Write — — Reserved bits Master enable TOCXA , TOCXB...
Page 352 Section 10 16-Bit Integrated Timer Unit (ITU) Bit 3—Master Enable TIOCB3 (EB3): Enables or disables ITU output at pin TIOCB Bit 3: EB3 Description TIOCB output is disabled regardless of TIOR3 and TFCR settings (TIOCB operates as a generic input/output pin). If XTGD = 0, EB3 is cleared to 0 when input capture A occurs in channel 1.
Page 353: Timer Output Control Register (Tocr)
Section 10 16-Bit Integrated Timer Unit (ITU) 10.2.6 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that selects externally triggered disabling of output in complementary PWM mode and reset-synchronized PWM mode, and inverts the output levels. — —...
Page 354: Timer Counters (Tcnt)
Section 10 16-Bit Integrated Timer Unit (ITU) Bit 1—Output Level Select 4 (OLS4): Selects output levels in complementary PWM mode and reset-synchronized PWM mode. Bit 1: OLS4 Description TIOCA , TIOCA , and TIOCB outputs are inverted TIOCA , TIOCA , and TIOCB outputs are not inverted (Initial value)
Page 355: General Registers (Gra, Grb)
Section 10 16-Bit Integrated Timer Unit (ITU) TCNT can be cleared to H'0000 by compare match with GRA or GRB or by input capture to GRA or GRB (counter clearing function) in the same channel. When TCNT overflows (changes from H'FFFF to H'0000), the OVF flag is set to 1 in TSR of the corresponding channel.
Page 356: Buffer Registers (Bra, Brb)
Section 10 16-Bit Integrated Timer Unit (ITU) general register. The corresponding IMFA or IMFB flag in TSR is set to 1 at the same time. The valid edge or edges of the input capture signal are selected in TIOR. TIOR settings are ignored in PWM mode, complementary PWM mode, and reset-synchronized PWM mode.
Page 357: Timer Control Registers (Tcr)
Section 10 16-Bit Integrated Timer Unit (ITU) The buffer registers are linked to the CPU by an internal 16-bit bus and can be written or read by either word or byte access. Buffer registers are initialized to H'FFFF by a reset and in standby mode. 10.2.10 Timer Control Registers (TCR) TCR is an 8-bit register.
Page 358 Section 10 16-Bit Integrated Timer Unit (ITU) Bits 6 and 5—Counter Clear 1/0 (CCLR1, CCLR0): These bits select how TCNT is cleared. Bit 6: CCLR1 Bit 5: CCLR0 Description TCNT is not cleared (Initial value) TCNT is cleared by GRA compare match or input capture * TCNT is cleared by GRB compare match or input capture *...
Page 359: Timer I/O Control Register (Tior)
Section 10 16-Bit Integrated Timer Unit (ITU) When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer counts the edge or edges selected by bits CKEG1 and CKEG0.
Page 360 Section 10 16-Bit Integrated Timer Unit (ITU) Bits 6 to 4—I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function. Bit 6: Bit 5: Bit 4: IOB2 IOB1 IOB0 Description GRB is an output No output at compare match (Initial value) compare register 0 output at GRB compare match * 1 output at GRB compare match *...
Page 361: Timer Status Register (Tsr)
Section 10 16-Bit Integrated Timer Unit (ITU) 10.2.12 Timer Status Register (TSR) TSR is an 8-bit register. The ITU has five TSRs, one in each channel. Channel Abbreviation Function TSR0 Indicates input capture, compare match, and overflow status TSR1 TSR2 TSR3 TSR4 —...
Page 362 Section 10 16-Bit Integrated Timer Unit (ITU) Bit 2—Overflow Flag (OVF): This status flag indicates TCNT overflow or underflow. Bit 2: OVF Description [Clearing condition] (Initial value) Read OVF when OVF = 1, then write 0 in OVF [Setting condition] TCNT overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF * Notes: * TCNT underflow occurs when TCNT operates as an up/down-counter.
Page 363: Timer Interrupt Enable Register (Tier)
Section 10 16-Bit Integrated Timer Unit (ITU) 10.2.13 Timer Interrupt Enable Register (TIER) TIER is an 8-bit register. The ITU has five TIERs, one in each channel. Channel Abbreviation Function TIER0 Enables or disables interrupt requests. TIER1 TIER2 TIER3 TIER4 —...
Page 364 Section 10 16-Bit Integrated Timer Unit (ITU) Bit 2—Overflow Interrupt Enable (OVIE): Enables or disables the interrupt requested by the OVF flag in TSR when OVF is set to 1. Bit 2: OVIE Description OVI interrupt requested by OVF is disabled (Initial value) OVI interrupt requested by OVF is enabled Bit 1—Input Capture/Compare Match Interrupt Enable B (IMIEB): Enables or disables the...
Page 365: Cpu Interface
Section 10 16-Bit Integrated Timer Unit (ITU) 10.3 CPU Interface 10.3.1 16-Bit Accessible Registers The timer counters (TCNTs), general registers A and B (GRAs and GRBs), and buffer registers A and B (BRAs and BRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data bus.
Page 366 Section 10 16-Bit Integrated Timer Unit (ITU) On-chip data bus Module Bus interface data bus TCNTH TCNTL Figure 10.8 Access to Timer Counter (CPU Writes to TCNT, Upper Byte) On-chip data bus Module Bus interface data bus TCNTH TCNTL Figure 10.9 Access to Timer Counter (CPU Writes to TCNT, Lower Byte) On-chip data bus Module Bus interface...
Page 367: 8-Bit Accessible Registers
Section 10 16-Bit Integrated Timer Unit (ITU) On-chip data bus Module Bus interface data bus TCNTH TCNTL Figure 10.11 Access to Timer Counter (CPU Reads TCNT, Lower Byte) 10.3.2 8-Bit Accessible Registers The registers other than the timer counters (TCNTS), general registers A and B (GRAs and GRBs), and buffer registers A and B (BRAs and BRBs) are 8-bit registers.
Page 368: Operation
Section 10 16-Bit Integrated Timer Unit (ITU) On-chip data bus Module Bus interface data bus Figure 10.13 Access to Timer Counter (CPU Reads TCR) 10.4 Operation 10.4.1 Overview A summary of operations in the various modes is given below. Normal Operation: Each channel has a timer counter and general registers. The timer counter counts up, and can operate as a free-running counter, periodic counter, or external event counter.
Page 369: Basic Functions
Section 10 16-Bit Integrated Timer Unit (ITU) Complementary PWM Mode: Channels 3 and 4 are paired for three-phase PWM output with non-overlapping complementary waveforms. When complementary PWM mode is selected GRA3, GRB3, GRA4, and GRB4 automatically function as output compare registers, and TIOCA , TIOCB , TIOCA...
Page 370 Section 10 16-Bit Integrated Timer Unit (ITU) Counter setup Select counter clock Type of counting? Free-running counting Periodic counting Select counter clear source Select output compare register function Set period Start counter Start counter Periodic counter Free-running counter 1. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge(s) of the external clock signal.
Page 371 Section 10 16-Bit Integrated Timer Unit (ITU) • Free-running and periodic counter operation A reset leaves the counters (TCNTs) in ITU channels 0 to 4 all set as free-running counters. A free-running counter starts counting up when the corresponding bit in TSTR is set to 1. When the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TSR.
Page 372 Section 10 16-Bit Integrated Timer Unit (ITU) TCNT value Counter cleared by general register compare match H'0000 Time STR bit Figure 10.16 Periodic Counter Operation • TCNT count timing  Internal clock source Bits TPSC2 to TPSC0 in TCR select the system clock (φ) or one of three internal clock sources obtained by prescaling the system clock (φ/2, φ/4, φ/8).
Page 373 Section 10 16-Bit Integrated Timer Unit (ITU) φ External clock input TCNT input TCNT N – 1 N + 1 Figure 10.18 Count Timing for External Clock Sources (when Both Edges Are Detected) Waveform Output by Compare Match: In ITU channels 0, 1, 3, and 4, compare match A or B can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle.
Page 374 Section 10 16-Bit Integrated Timer Unit (ITU) • Examples of waveform output Figure 10.20 shows examples of 0 and 1 output. TCNT operates as a free-running counter, 0 output is selected for compare match A, and 1 output is selected for compare match B. When the pin is already at the selected output level, the pin level does not change.
Page 375 Section 10 16-Bit Integrated Timer Unit (ITU) • Output compare timing The compare match signal is generated in the last state in which TCNT and the general register match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the output compare pin (TIOCA or TIOCB).
Page 376 Section 10 16-Bit Integrated Timer Unit (ITU) Input selection Set TIOR to select the input capture function of a general register and the rising edge, falling edge, or both edges of the input capture signal. Clear the port data direction bit to 0 before making these Select input-capture input TIOR settings.
Page 377 Section 10 16-Bit Integrated Timer Unit (ITU) • Input capture signal timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in TIOR. Figure 10.25 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges.
Page 378: Synchronization
Section 10 16-Bit Integrated Timer Unit (ITU) 10.4.3 Synchronization The synchronization function enables two or more timer counters to be synchronized by writing the same data to them simultaneously (synchronous preset). With appropriate TCR settings, two or more timer counters can also be cleared simultaneously (synchronous clear). Synchronization enables additional general registers to be associated with a single time base.
Page 379: Pwm Mode
Section 10 16-Bit Integrated Timer Unit (ITU) Example of Synchronization: Figure 10.27 shows an example of synchronization. Channels 0, 1, and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by compare match with GRB0.
Page 380 Section 10 16-Bit Integrated Timer Unit (ITU) Table 10.4 PWM Output Pins and Registers Channel Output Pin 1 Output 0 Output TIOCA GRA0 GRB0 TIOCA GRA1 GRB1 TIOCA GRA2 GRB2 TIOCA GRA3 GRB3 TIOCA GRA4 GRB4 Sample Setup Procedure for PWM Mode: Figure 10.28 shows a sample procedure for setting up PWM mode.
Page 381 Section 10 16-Bit Integrated Timer Unit (ITU) Examples of PWM Mode: Figure 10.29 shows examples of operation in PWM mode. In PWM mode TIOCA becomes an output pin. The output goes to 1 at compare match with GRA, and to 0 at compare match with GRB.
Page 382 Section 10 16-Bit Integrated Timer Unit (ITU) Figure 10.30 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%. If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB, the duty cycle is 0%.
Page 383: Reset-Synchronized Pwm Mode
Section 10 16-Bit Integrated Timer Unit (ITU) 10.4.5 Reset-Synchronized PWM Mode In reset-synchronized PWM mode channels 3 and 4 are combined to produce three pairs of complementary PWM waveforms, all having one waveform transition point in common. When reset-synchronized PWM mode is selected TIOCA , TIOCB , TIOCA , TOCXA...
Page 384 Section 10 16-Bit Integrated Timer Unit (ITU) Sample Setup Procedure for Reset-Synchronized PWM Mode: Figure 10.31 shows a sample procedure for setting up reset-synchronized PWM mode. 1. Clear the STR3 bit in TSTR to 0 to halt TCNT3. Reset-synchronized PWM mode Reset-synchronized PWM mode must be set up while TCNT3 is halted.
Page 385 Section 10 16-Bit Integrated Timer Unit (ITU) Example of Reset-Synchronized PWM Mode: Figure 10.32 shows an example of operation in reset-synchronized PWM mode. TCNT3 operates as an up-counter in this mode. TCNT4 operates independently, detached from GRA4 and GRB4. When TCNT3 matches GRA3, TCNT3 is cleared and resumes counting from H'0000.
Page 386: Complementary Pwm Mode
Section 10 16-Bit Integrated Timer Unit (ITU) 10.4.6 Complementary PWM Mode In complementary PWM mode channels 3 and 4 are combined to output three pairs of complementary, non-overlapping PWM waveforms. When complementary PWM mode is selected TIOCA , TIOCB , TIOCA , TOCXA , TIOCB and TOCXB...
Page 387 Section 10 16-Bit Integrated Timer Unit (ITU) Setup Procedure for Complementary PWM Mode: Figure 10.33 shows a sample procedure for setting up complementary PWM mode. 1. Clear bits STR3 and STR4 to 0 in Complementary PWM mode TSTR to halt the timer counters. Complementary PWM mode must be set up while TCNT3 and TCNT4 are halted.
Page 388 Section 10 16-Bit Integrated Timer Unit (ITU) Clearing Procedure for Complementary PWM Mode: Figure 10.34 shows the steps to clear complementary PWM mode. Complementary PWM mode 1. Clear the CMD1 bit of TFCR to 0 to set channels 3 and 4 to normal operating mode.
Page 389 Section 10 16-Bit Integrated Timer Unit (ITU) Examples of Complementary PWM Mode: Figure 10.35 shows an example of operation in complementary PWM mode. TCNT3 and TCNT4 operate as up/down-counters, counting down from compare match between TCNT3 and GRA3 and counting up from the point at which TCNT4 underflows.
Page 390 Section 10 16-Bit Integrated Timer Unit (ITU) Figure 10.36 shows examples of waveforms with 0% and 100% duty cycles (in one phase) in complementary PWM mode. In this example the outputs change at compare match with GRB3, so waveforms with duty cycles of 0% or 100% can be output by setting GRB3 to a value larger than GRA3.
Page 391 Section 10 16-Bit Integrated Timer Unit (ITU) In complementary PWM mode, TCNT3 and TCNT4 overshoot and undershoot at the transitions between up-counting and down-counting. The setting conditions for the IMFA bit in channel 3 and the OVF bit in channel 4 differ from the usual conditions. In buffered operation the buffer transfer conditions also differ.
Page 392 Section 10 16-Bit Integrated Timer Unit (ITU) Underflow Overflow TCNT4 H'0001 H'0000 H'FFFF H'0000 Flag not set Set to 1 Buffer transfer signal (BR to GR) Buffer transfer No buffer transfer Figure 10.38 Undershoot Timing In channel 3, IMFA is set to 1 only during up-counting. In channel 4, OVF is set to 1 only when an underflow occurs.
Page 393 Section 10 16-Bit Integrated Timer Unit (ITU) GRA3 H'0000 Not allowed Figure 10.39 Changing a General Register Setting by Buffer Transfer (Example 1)  Buffer transfer at transition from up-counting to down-counting If the general register value is in the range from GRA3 – T + 1 to GRA3, do not transfer a buffer register value outside this range.
Page 394 Section 10 16-Bit Integrated Timer Unit (ITU) TCNT3 TCNT4 T – 1 Illegal changes H'0000 H'FFFF Figure 10.41 Changing a General Register Setting by Buffer Transfer (Caution 2)  General register settings outside the counting range (H'0000 to GRA3) Waveforms with a duty cycle of 0% or 100% can be output by setting a general register to a value outside the counting range.
Page 395: Phase Counting Mode
Section 10 16-Bit Integrated Timer Unit (ITU) 10.4.7 Phase Counting Mode In phase counting mode the phase difference between two external clock inputs (at the TCLKA and TCLKB pins) is detected, and TCNT2 counts up or down accordingly. In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock input pins and TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to TPSC0, CKEG1, and CKEG0 in TCR2.
Page 396 Section 10 16-Bit Integrated Timer Unit (ITU) Example of Phase Counting Mode: Figure 10.44 shows an example of operations in phase counting mode. Table 10.9 lists the up-counting and down-counting conditions for TCNT2. In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must also be at least 1.5 states, and the pulse width must be at least 2.5 states.
Page 397: Buffering
Section 10 16-Bit Integrated Timer Unit (ITU) 10.4.8 Buffering Buffering operates differently depending on whether a general register is an output compare register or an input capture register, with further differences in reset-synchronized PWM mode and complementary PWM mode. Buffering is available only in channels 3 and 4. Buffering operations under the conditions mentioned above are described next.
Page 398 Section 10 16-Bit Integrated Timer Unit (ITU) • Complementary PWM mode The buffer register value is transferred to the general register when TCNT3 and TCNT4 change counting direction. This occurs at the following two times:  When TCNT3 compare matches GRA3 ...
Page 399 Section 10 16-Bit Integrated Timer Unit (ITU) Examples of Buffering: Figure 10.49 shows an example in which GRA is set to function as an output compare register buffered by BRA, TCNT is set to operate as a periodic counter cleared by GRB compare match, and TIOCA and TIOCB are set to toggle at compare match A and B.
Page 400 Section 10 16-Bit Integrated Timer Unit (ITU) φ TCNT n + 1 Compare match signal Buffer transfer signal Figure 10.50 Compare Match and Buffer Transfer Timing (Example) Rev. 3.00 Mar 21, 2006 page 372 of 814 REJ09B0302-0300...
Page 401 Section 10 16-Bit Integrated Timer Unit (ITU) Figure 10.51 shows an example in which GRA is set to function as an input capture register buffered by BRA, and TCNT is cleared by input capture B. The falling edge is selected as the input capture edge at TIOCB.
Page 402 Section 10 16-Bit Integrated Timer Unit (ITU) φ TIOC pin Input capture signal TCNT n + 1 N + 1 Figure 10.52 Input Capture and Buffer Transfer Timing Rev. 3.00 Mar 21, 2006 page 374 of 814 REJ09B0302-0300...
Page 403 Section 10 16-Bit Integrated Timer Unit (ITU) Figure 10.53 shows an example in which GRB3 is buffered by BRB3 in complementary PWM mode. Buffering is used to set GRB3 to a higher value than GRA3, generating a PWM waveform with 0% duty cycle. The BRB3 value is transferred to GRB3 when TCNT3 matches GRA3, and when TCNT4 underflows.
Page 404: Itu Output Timing
Section 10 16-Bit Integrated Timer Unit (ITU) 10.4.9 ITU Output Timing The ITU outputs from channels 3 and 4 can be disabled by bit settings in TOER or by an external trigger, or inverted by bit settings in TOCR. Timing of Enabling and Disabling of ITU Output by TOER: In this example an ITU output is disabled by clearing a master enable bit to 0 in TOER.
Page 405 Section 10 16-Bit Integrated Timer Unit (ITU) Timing of Disabling of ITU Output by External Trigger: If the XTGD bit is cleared to 0 in TOCR in reset-synchronized PWM mode or complementary PWM mode, when an input capture A signal occurs in channel 1, the master enable bits are cleared to 0 in TOER, disabling ITU output. Figure 10.55 shows the timing.
Page 406: Interrupts
Section 10 16-Bit Integrated Timer Unit (ITU) 10.5 Interrupts The ITU has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 10.5.1 Setting of Status Flags Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a compare match signal generated when TCNT matches a general register (GR).
Page 407 Section 10 16-Bit Integrated Timer Unit (ITU) Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an input capture signal. The TCNT contents are simultaneously transferred to the corresponding general register. Figure 10.58 shows the timing. φ...
Page 408: Clearing Of Status Flags
Section 10 16-Bit Integrated Timer Unit (ITU) Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when TCNT overflows from H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 10.59 shows the timing. φ TCNT H'FFFF H'0000 Overflow signal...
Page 409: Interrupt Sources And Dma Controller Activation
Section 10 16-Bit Integrated Timer Unit (ITU) 10.5.3 Interrupt Sources and DMA Controller Activation Each ITU channel can generate a compare match/input capture A interrupt, a compare match/input capture B interrupt, and an overflow interrupt. In total there are 15 interrupt sources, all independently vectored.
Page 410: Usage Notes
Section 10 16-Bit Integrated Timer Unit (ITU) 10.6 Usage Notes This section describes contention and other matters requiring special attention during ITU operations. Contention between TCNT Write and Clear: If a counter clear signal occurs in the T state of a TCNT write cycle, clearing of the counter takes priority and the write is not performed.
Page 411 Section 10 16-Bit Integrated Timer Unit (ITU) Contention between TCNT Word Write and Increment: If an increment pulse occurs in the T state of a TCNT word write cycle, writing takes priority and TCNT is not incremented. See figure 10.62. TCNT word write cycle φ...
Page 412 Section 10 16-Bit Integrated Timer Unit (ITU) Contention between TCNT Byte Write and Increment: If an increment pulse occurs in the T or T state of a TCNT byte write cycle, writing takes priority and TCNT is not incremented. The TCNT byte that was not written retains its previous value.
Page 413 Section 10 16-Bit Integrated Timer Unit (ITU) Contention between General Register Write and Compare Match: If a compare match occurs in the T state of a general register write cycle, writing takes priority and the compare match signal is inhibited. See figure 10.64. General register write cycle φ...
Page 414 Section 10 16-Bit Integrated Timer Unit (ITU) Contention between TCNT Write and Overflow or Underflow: If an overflow occurs in the T state of a TCNT write cycle, writing takes priority and the counter is not incremented. OVF is set to 1.The same holds for underflow.
Page 415 Section 10 16-Bit Integrated Timer Unit (ITU) Contention between General Register Read and Input Capture: If an input capture signal occurs during the T state of a general register read cycle, the value before input capture is read. See figure 10.66. General register read cycle φ...
Page 416 Section 10 16-Bit Integrated Timer Unit (ITU) Contention between Counter Clearing by Input Capture and Counter Increment: If an input capture signal and counter increment signal occur simultaneously, the counter is cleared according to the input capture signal. The counter is not incremented by the increment signal. The value before the counter is cleared is transferred to the general register.
Page 417 Section 10 16-Bit Integrated Timer Unit (ITU) Contention between General Register Write and Input Capture: If an input capture signal occurs in the T state of a general register write cycle, input capture takes priority and the write to the general register is not performed. See figure 10.68. General register write cycle φ...
Page 418 Section 10 16-Bit Integrated Timer Unit (ITU) Contention between Buffer Register Write and Input Capture: If a buffer register is used for input capture buffering and an input capture signal occurs in the T state of a write cycle, input capture takes priority and the write to the buffer register is not performed.
Page 419 Section 10 16-Bit Integrated Timer Unit (ITU) Note on Write Operations when Using Synchronous Operation: When channels are synchronized, if a TCNT value is modified by byte write access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. Example: When channels 2 and 3 are synchronized •...
Page 420 Section 10 16-Bit Integrated Timer Unit (ITU) ITU Operating Modes Table 10.11 (1) ITU Operating Modes (Channel 0) Rev. 3.00 Mar 21, 2006 page 392 of 814 REJ09B0302-0300...
Page 421 Section 10 16-Bit Integrated Timer Unit (ITU) Table 10.11 (2) ITU Operating Modes (Channel 1) Rev. 3.00 Mar 21, 2006 page 393 of 814 REJ09B0302-0300...
Page 422 Section 10 16-Bit Integrated Timer Unit (ITU) Table 10.11 (3) ITU Operating Modes (Channel 2) Rev. 3.00 Mar 21, 2006 page 394 of 814 REJ09B0302-0300...
Page 423 Section 10 16-Bit Integrated Timer Unit (ITU) Table 10.11 (4) ITU Operating Modes (Channel 3) Rev. 3.00 Mar 21, 2006 page 395 of 814 REJ09B0302-0300...
Page 424 Section 10 16-Bit Integrated Timer Unit (ITU) Table 10.11 (5) ITU Operating Modes (Channel 4) Rev. 3.00 Mar 21, 2006 page 396 of 814 REJ09B0302-0300...
Page 425: Section 11 Programmable Timing Pattern Controller
Section 11 Programmable Timing Pattern Controller Section 11 Programmable Timing Pattern Controller 11.1 Overview The H8/3052BF has a built-in programmable timing pattern controller (TPC) that provides pulse outputs by using the 16-bit integrated timer unit (ITU) as a time base. The TPC pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and independently.
Page 426: Block Diagram
Section 11 Programmable Timing Pattern Controller 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the TPC. ITU compare match signals PADDR PBDDR NDERA NDERB Control logic TPMR TPCR Internal data bus Pulse output pins, group 3 PBDR NDRB Pulse output pins, group 2 Pulse output...
Page 427: Pin Configuration
Section 11 Programmable Timing Pattern Controller 11.1.3 Pin Configuration Table 11.1 summarizes the TPC output pins. Table 11.1 TPC Pins Name Symbol Function TPC output 0 Output Group 0 pulse output TPC output 1 Output TPC output 2 Output TPC output 3 Output TPC output 4 Output...
Page 428: Register Configuration
Section 11 Programmable Timing Pattern Controller 11.1.4 Register Configuration Table 11.2 summarizes the TPC registers. Table 11.2 TPC Registers Address * Name Abbreviation Initial Value H'FFD1 Port A data direction register PADDR H'00 R/(W) * H'FFD3 Port A data register PADR H'00 H'FFD4...
Page 429: Register Descriptions
Section 11 Programmable Timing Pattern Controller 11.2 Register Descriptions 11.2.1 Port A Data Direction Register (PADDR) PADDR is an 8-bit write-only register that selects input or output for each pin in port A. PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR...
Page 430: Port B Data Direction Register (Pbddr)
Section 11 Programmable Timing Pattern Controller 11.2.3 Port B Data Direction Register (PBDDR) PBDDR is an 8-bit write-only register that selects input or output for each pin in port B. PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR...
Page 431: Next Data Register A (Ndra)
Section 11 Programmable Timing Pattern Controller 11.2.5 Next Data Register A (NDRA) NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups 1 and 0 (pins TP to TP ). During TPC output, when an ITU compare match event specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR.
Page 432 Section 11 Programmable Timing Pattern Controller Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFA5 and the address of the lower 4 bits (group 0) is H'FFA7.
Page 433: Next Data Register B (Ndrb)
Section 11 Programmable Timing Pattern Controller 11.2.6 Next Data Register B (NDRB) NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups 3 and 2 (pins TP to TP ). During TPC output, when an ITU compare match event specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR.
Page 434 Section 11 Programmable Timing Pattern Controller Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFA4 and the address of the lower 4 bits (group 2) is H'FFA6.
Page 435: Next Data Enable Register A (Ndera)
Section 11 Programmable Timing Pattern Controller 11.2.7 Next Data Enable Register A (NDERA) NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0 to TP ) on a bit-by-bit basis. NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1...
Page 436: Next Data Enable Register B (Nderb)
Section 11 Programmable Timing Pattern Controller 11.2.8 Next Data Enable Register B (NDERB) NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2 to TP ) on a bit-by-bit basis. NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9...
Page 437: Tpc Output Control Register (Tpcr)
Section 11 Programmable Timing Pattern Controller 11.2.9 TPC Output Control Register (TPCR) TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a group-by-group basis. G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 3 compare match select 1 and 0...
Page 438 Section 11 Programmable Timing Pattern Controller Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits select the compare match event that triggers TPC output group 2 (TP to TP Bit 5: G2CMS1 Bit 4: G2CMS0 Description TPC output group 2 (TP to TP...
Page 439: Tpc Output Mode Register (Tpmr)
Section 11 Programmable Timing Pattern Controller 11.2.10 TPC Output Mode Register (TPMR) TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for each group. — — — — G3NOV G2NOV G1NOV G0NOV Initial value Read/Write — —...
Page 440 Section 11 Programmable Timing Pattern Controller Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for group 3 (TP to TP Bit 3: G3NOV Description Normal TPC output in group 3 (output values change at compare match A in the selected ITU channel) (Initial value) Non-overlapping TPC output in group 3 (independent 1 and 0 output at...
Page 441: Operation
Section 11 Programmable Timing Pattern Controller 11.3 Operation 11.3.1 Overview When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents. When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit contents are transferred to PADR or PBDR to update the output values.
Page 442: Output Timing
Section 11 Programmable Timing Pattern Controller 11.3.2 Output Timing If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output when the selected compare match event occurs. Figure 11.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. φ...
Page 443: Normal Tpc Output
Section 11 Programmable Timing Pattern Controller 11.3.3 Normal TPC Output Sample Setup Procedure for Normal TPC Output: Figure 11.4 shows a sample procedure for setting up normal TPC output. Normal TPC output 1. Set TIOR to make GRA an output compare register (with output inhibited).
Page 444 Section 11 Programmable Timing Pattern Controller Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 11.5 shows an example in which the TPC is used for cyclic five-phase pulse output. TCNT value Compare match TCNT H'0000 Time NDRB PBDR 1.
Page 445: Non-Overlapping Tpc Output
Section 11 Programmable Timing Pattern Controller 11.3.4 Non-Overlapping TPC Output Sample Setup Procedure for Non-Overlapping TPC Output: Figure 11.6 shows a sample procedure for setting up non-overlapping TPC output. Non-overlapping 1. Set TIOR to make GRA and GRB TPC output output compare registers (with output inhibited).
Page 446 Section 11 Programmable Timing Pattern Controller Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non- Overlapping Output): Figure 11.7 shows an example of the use of TPC output for four-phase complementary non-overlapping pulse output. TCNT value TCNT H'0000 Time NDRB PBDR Non-overlap margin...
Page 447: Tpc Output Triggering By Input Capture
Section 11 Programmable Timing Pattern Controller • H'FF is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in TPCR to select compare match in the ITU channel set up in step 1 as the output trigger.
Page 448: Usage Notes
Section 11 Programmable Timing Pattern Controller 11.4 Usage Notes 11.4.1 Operation of TPC Output Pins to TP are multiplexed with ITU, DMAC, address bus, and other pin functions. When ITU, DMAC, or address output is enabled, the corresponding pins cannot be used for TPC output. The data transfer from NDR bits to DR bits takes place, however, regardless of the usage of the pin.
Page 449 Section 11 Programmable Timing Pattern Controller Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the IMFA interrupt service routine write the next data in NDR, or by having the IMFA interrupt activate the DMAC.
Page 450 Section 11 Programmable Timing Pattern Controller Rev. 3.00 Mar 21, 2006 page 422 of 814 REJ09B0302-0300...
Page 451: Section 12 Watchdog Timer
Section 12 Watchdog Timer Section 12 Watchdog Timer 12.1 Overview The H8/3052BF has an on-chip watchdog timer (WDT). The WDT has two selectable functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an interval timer.
Page 452: Block Diagram
Section 12 Watchdog Timer 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the WDT. Overflow Internal TCNT data bus Read/ Interrupt Interrupt signal write control (interval timer) control TCSR Internal clock sources φ/2 RSTCSR φ/32 φ/64 Reset (internal) Reset control Clock φ/128...
Page 453: Register Descriptions
Section 12 Watchdog Timer 12.2 Register Descriptions 12.2.1 Timer Counter (TCNT) TCNT is an 8-bit readable and writable* up-counter. Initial value Read/Write When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal clock source selected by bits CKS2 to CKS0 in TCSR.
Page 454: Timer Control/Status Register (Tcsr)
Section 12 Watchdog Timer 12.2.2 Timer Control/Status Register (TCSR) TCSR is an 8-bit readable and writable * register. Its functions include selecting the timer mode and clock source. WT/IT — — CKS2 CKS1 CKS0 Initial value Read/Write R/(W) — — Clock select These bits select the TCNT clock source...
Page 455 Section 12 Watchdog Timer Bit 6—Timer Mode Select (WT/IT IT IT IT): Selects whether to use the WDT as a watchdog timer or interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request when TCNT overflows. If used as a watchdog timer, the WDT generates a reset signal when TCNT overflows.
Page 456: Reset Control/Status Register (Rstcsr)
Section 12 Watchdog Timer 12.2.3 Reset Control/Status Register (RSTCSR) RSTCSR is an 8-bit readable/writable * register that monitors the state of the reset signal generated by watchdog timer overflow. WRST — — — — — — — Initial value Read/Write R/(W) —...
Page 457: Notes On Register Access
Section 12 Watchdog Timer Bit 6—Reserved: Do not set to 1. Bits 5 to 0—Reserved: Read-only bits, always read as 1. 12.2.4 Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write.
Page 458: Operation
Section 12 Watchdog Timer Reading TCNT, TCSR, and RSTCSR: These registers are read like other registers. Byte access instructions can be used. The read addresses are H'FFA8 for TCSR, H'FFA9 for TCNT, and H'FFAB for RSTCSR, as listed in table 12.2. Table 12.2 Read Addresses of TCNT, TCSR, and RSTCSR Address * Register...
Page 459: Interval Timer Operation
Section 12 Watchdog Timer WDT overflow H'FF TME set to 1 TCNT count value H'00 OVF = 1 Start H'00 written Reset H'00 written in TCNT in TCNT Internal reset signal 518 states Figure 12.4 Watchdog Timer Operation 12.3.2 Interval Timer Operation Figure 12.5 illustrates interval timer operation.
Page 460: Timing Of Setting Of Overflow Flag (Ovf)
Section 12 Watchdog Timer 12.3.3 Timing of Setting of Overflow Flag (OVF) Figure 12.6 shows the timing of setting of the OVF flag in TCSR. The OVF flag is set to 1 when TCNT overflows. At the same time, a reset signal is generated in watchdog timer operation, or an interval timer interrupt is generated in interval timer operation.
Page 461: Timing Of Setting Of Watchdog Timer Reset Bit (Wrst)
Section 12 Watchdog Timer 12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR. Figure 12.7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is set to 1 when TCNT overflows and OVF is set to 1.
Page 462: Interrupts
Section 12 Watchdog Timer 12.4 Interrupts During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR. 12.5 Usage Notes Contention between TCNT Write and Increment: If a timer counter clock pulse is generated during the T state of a write cycle to TCNT, the write takes priority and the timer count is not incremented.
Page 463: Section 13 Serial Communication Interface
Section 13 Serial Communication Interface Section 13 Serial Communication Interface 13.1 Overview The H8/3052BF has a serial communication interface (SCI) with two independent channels. The two channels are functionally identical. The SCI can communicate in asynchronous or synchronous mode. It also has a multiprocessor communication function for serial communication among two or more processors.
Page 464 Section 13 Serial Communication Interface • Data length: 8 bits • Receive error detection: overrun errors • Full duplex communication The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. The transmitting and receiving sections are both double-buffered, so serial data can be transmitted and received continuously.
Page 465: Block Diagram
Section 13 Serial Communication Interface 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the SCI. Internal data bus Module data bus φ φ/4 Baud rate generator φ/16 Transmit/ receive control φ/64 Parity generate Clock Parity check External clock Legend: RSR: Receive shift register...
Page 466: Pin Configuration
Section 13 Serial Communication Interface 13.1.3 Pin Configuration The SCI has serial pins for each channel as listed in table 13.1. Table 13.1 SCI Pins Channel Name Abbreviation Function Serial clock pin Input/output clock input/output Receive data pin Input receive data input Transmit data pin Output transmit data output...
Page 467: Register Descriptions
Section 13 Serial Communication Interface 13.2 Register Descriptions 13.2.1 Receive Shift Register (RSR) RSR is the register that receives serial data. Read/Write — — — — — — — — The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first, thereby converting the data to parallel data.
Page 468: Transmit Shift Register (Tsr)
Section 13 Serial Communication Interface 13.2.3 Transmit Shift Register (TSR) TSR is the register that transmits serial data. Read/Write — — — — — — — — The SCI loads transmit data from TDR into TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first.
Page 469: Serial Mode Register (Smr)
Section 13 Serial Communication Interface 13.2.5 Serial Mode Register (SMR) SMR is an 8-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. STOP CKS1 CKS0 Initial value Read/Write Clock select 1/0 These bits select the baud rate generator’s clock source...
Page 470 Section 13 Serial Communication Interface Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data length in asynchronous mode. In synchronous mode the data length is 8 bits regardless of the CHR setting. Bit 6: CHR Description 8-bit data (Initial value) 7-bit data * Note: * When 7-bit data is selected, the MSB (bit 7) in TDR is not transmitted.
Page 471 Section 13 Serial Communication Interface Bit 3—Stop Bit Length (STOP): Selects one or two stop bits in asynchronous mode. This setting is used only in asynchronous mode. In synchronous mode no stop bit is added, so the STOP bit setting is ignored. Bit 3: STOP Description One stop bit *...
Page 472: Serial Control Register (Scr)
Section 13 Serial Communication Interface 13.2.6 Serial Control Register (SCR) SCR enables the SCI transmitter and receiver, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source. MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock enable 1/0...
Page 473 Section 13 Serial Communication Interface Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from TDR to TSR. Bit 7: TIE Description Transmit-data-empty interrupt request (TXI) is disabled * (Initial value)
Page 474 Section 13 Serial Communication Interface Bit 4—Receive Enable (RE): Enables or disables the start of SCI serial receiving operations. Bit 4: RE Description Receiving disabled * (Initial value) Receiving enabled * Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These flags retain their previous values.
Page 475 Section 13 Serial Communication Interface Bits 1 and 0—Clock Enable 1 and 0 (CKE1/0): These bits select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the settings of CKE1 and CKE0, the SCK pin can be used for generic input/output, serial clock output, or serial clock input. The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally clocked (CKE1 = 0).
Page 476: Serial Status Register (Ssr)
Section 13 Serial Communication Interface 13.2.7 Serial Status Register (SSR) SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate SCI operating status. TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit transfer Value of multi-...
Page 477 Section 13 Serial Communication Interface SSR is initialized to H'84 by a reset and in standby mode. Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data from TDR into TSR and the next serial transmit data can be written in TDR. Bit 7: TDRE Description TDR contains valid transmit data...
Page 478 Section 13 Serial Communication Interface Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error. Bit 5: ORER Description (Initial value) * Receiving is in progress or has ended normally [Clearing conditions] • The chip is reset or enters standby mode. •...
Page 479 Section 13 Serial Communication Interface Bit 3—Parity Error (PER): Indicates that data reception ended abnormally due to a parity error in asynchronous mode. Bit 3: PER Description Receiving is in progress or has ended normally * (Initial value) [Clearing conditions] •...
Page 480: Bit Rate Register (Brr)
Section 13 Serial Communication Interface Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit and cannot be written. Bit 1: MPB Description Multiprocessor bit value in receive data is 0 * (Initial value)
Page 481 Section 13 Serial Communication Interface Table 13.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode φ φ φ φ (MHz) 2.097152 2.4576 Bit Rate Error Error Error Error (bits/s) 0.03 –0.04 –0.26 0.03 0.16 0.21 0.16 0.16 0.21 0.16 0.16 0.21...
Page 482 Section 13 Serial Communication Interface φ φ φ φ (MHz) 6.144 7.3728 Bit Rate Error Error Error Error (bits/s) –0.44 0.08 –0.07 0.03 0.16 0.16 0.16 0.16 0.16 0.16 1200 0.16 0.16 2400 0.16 0.16 4800 0.16 0.16 9600 –2.34 0.16 19200 –2.34...
Page 483 Section 13 Serial Communication Interface φ φ φ φ (MHz) 14.7456 Bit Rate Error Error Error Error (bits/s) –0.08 –0.17 0.70 0.03 0.16 0.16 0.16 –0.43 0.16 0.16 0.16 0.16 0.16 1200 –0.43 0.16 0.16 2400 0.16 0.16 0.16 4800 –0.43 0.16 0.16...
Page 484 Section 13 Serial Communication Interface Table 13.4 Examples of Bit Rates and BRR Settings in Synchronous Mode φ φ φ φ (MHz) Bit Rate (bits/s) — — — — — — — — — — — — — — 2.5 k 10 k 25 k 50 k...
Page 485 Section 13 Serial Communication Interface φ φ φ φ (MHz) Bit Rate (bits/s) — — — — — — — — — — — — — — — — 2.5 k 10 k 25 k 50 k 100 k 250 k 500 k —...
Page 486 Section 13 Serial Communication Interface The BRR setting is calculated as follows: Asynchronous mode: φ × 10 – 1 64 × 2 × B 2n–1 Synchronous mode: φ × 10 – 1 8 × 2 × B 2n–1 B: Bit rate (bits/s) N: BRR setting for baud rate generator (0 ≤...
Page 487 Section 13 Serial Communication Interface Table 13.5 indicates the maximum bit rates in asynchronous mode for various system clock frequencies. Tables 13.6 and 13.7 indicate the maximum bit rates with external clock input. Table 13.5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode) Settings φ...
Page 488 Section 13 Serial Communication Interface Table 13.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) φ φ φ φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000...
Page 489 Section 13 Serial Communication Interface Table 13.7 Maximum Bit Rates with External Clock Input (Synchronous Mode) φ φ φ φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.3333 333333.3 0.6667 666666.7 1.0000 1000000.0 1.3333 1333333.3 1.6667 1666666.7 2.0000 2000000.0 2.3333 2333333.3...
Page 490: Operation
Section 13 Serial Communication Interface 13.3 Operation 13.3.1 Overview The SCI has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. Serial communication is possible in either mode. Asynchronous or synchronous mode and the communication format are selected in SMR, as shown in table 13.8.
Page 491 Section 13 Serial Communication Interface Table 13.8 SMR Settings and Serial Communication Formats SMR Settings SCI Communication Format Multi- Stop Bit 7: Bit 6: Bit 2: Bit 5: Bit 3: Data processor Parity C/A A A A STOP Mode Length Length Asynchronous 8-bit data...
Page 492: Operation In Asynchronous Mode
Section 13 Serial Communication Interface 13.3.2 Operation in Asynchronous Mode In asynchronous mode each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible.
Page 493 Section 13 Serial Communication Interface Communication Formats: Table 13.10 shows the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in SMR. Table 13.10 Serial Communication Formats (Asynchronous Mode) SMR Settings Serial Communication Format and Frame Length STOP 8-bit data STOP...
Page 494 Section 13 Serial Communication Interface Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in SMR and bits CKE1 and CKE0 in SCR. See table 13.9. When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate.
Page 495 Section 13 Serial Communication Interface Start of initialization 1. Select the clock source in SCR. Clear the RIE, TIE, TEIE, MPIE, TE, and RE bits to 0. If clock output is selected in asynchronous mode, clock output starts Clear TE and RE bits immediately after the setting is made in SCR.
Page 496 Section 13 Serial Communication Interface • Transmitting Serial Data (Asynchronous Mode) Figure 13.5 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. 1. SCI initialization: the transmit data output function of Initialize the TxD pin is selected automatically. After the TE bit is set to 1, one frame of 1 is output, then transmission is possible.
Page 497 Section 13 Serial Communication Interface In transmitting serial data, the SCI operates as follows. 1. The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. 2.
Page 498 Section 13 Serial Communication Interface • Receiving Serial Data (Asynchronous Mode) Figure 13.7 shows a sample flowchart for receiving serial data and indicates the procedure to follow. 1. SCI initialization: the receive data function of Initialize the RxD pin is selected automatically. 2, 3.
Page 499 Section 13 Serial Communication Interface Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit to 0 in SCR PER = 1? Parity error handling Clear ORER, PER, and FER flags to 0 in SSR Figure 13.7 Sample Flowchart for Receiving Serial Data (2) Rev.
Page 500 Section 13 Serial Communication Interface In receiving, the SCI operates as follows. 1. The SCI monitors the receive data line. When it detects a start bit, the SCI synchronizes internally and starts receiving. 2. Receive data is stored in RSR in order from LSB to MSB. 3.
Page 501: Multiprocessor Communication
Section 13 Serial Communication Interface Figure 13.8 shows an example of SCI receive operation in asynchronous mode. Start Parity Stop Start Parity Stop Data Data Idle (mark) state RDRF RXI interrupt handler request reads data in RDR and Framing error, clears RDRF flag to 0 ERI request 1 frame...
Page 502 Section 13 Serial Communication Interface Communication Formats: Four formats are available. Parity-bit settings are ignored when a multiprocessor format is selected. For details see table 13.10. Clock: See the description of asynchronous mode. Transmitting processor Serial communication line Receiving Receiving Receiving Receiving processor A...
Page 503 Section 13 Serial Communication Interface Transmitting and Receiving Data • Transmitting Multiprocessor Serial Data Figure 13.10 shows a sample flowchart for transmitting multiprocessor serial data and indicates the procedure to follow. Initialize 1. SCI initialization: the transmit data output function of the TxD pin is selected automatically.
Page 504 Section 13 Serial Communication Interface In transmitting serial data, the SCI operates as follows. 1. The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. 2.
Page 505 Section 13 Serial Communication Interface • Receiving Multiprocessor Serial Data Figure 13.12 shows a sample flowchart for receiving multiprocessor serial data and indicates the procedure to follow. 1. SCI initialization: the receive data Initialize function of the RxD pin is selected automatically.
Page 506 Section 13 Serial Communication Interface Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit to 0 in SCR Clear ORER, PER, and FER flags to 0 in SSR Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (2) Rev.
Page 507 Section 13 Serial Communication Interface Figure 13.13 shows an example of SCI receive operation using a multiprocessor format. Start Stop Start Stop Data (ID1) Data (data1) Idle (mark) state MPIE RDRF RDR value MPB detection RXI request RXI interrupt handler Not own ID, so No RXI request, (multiprocessor...
Page 508: Synchronous Operation
Section 13 Serial Communication Interface 13.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible.
Page 509 Section 13 Serial Communication Interface operation, the serial clock is output until an overrun error occurs or the RE bit is cleared to 0. For character-by-character reception, an external clock should be selected as the clock source. Transmitting and Receiving Data •...
Page 510 Section 13 Serial Communication Interface • Transmitting Serial Data (Synchronous Mode) Figure 13.16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. 1. SCI initialization: the transmit data output function Initialize of the TxD pin is selected automatically. 2.
Page 511 Section 13 Serial Communication Interface In transmitting serial data, the SCI operates as follows. 1. The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. 2.
Page 512 Section 13 Serial Communication Interface • Receiving Serial Data Figure 13.18 shows a sample flowchart for receiving serial data and indicates the procedure to follow. When switching from asynchronous mode to synchronous mode, make sure that the ORER, PER, and FER flags are cleared to 0. If the FER or PER flag is set to 1 the RDRF flag will not be set and both transmitting and receiving will be disabled.
Page 513 Section 13 Serial Communication Interface Error handling Overrun error handling Clear ORER flag to 0 in SSR Figure 13.18 Sample Flowchart for Serial Receiving (2) In receiving, the SCI operates as follows. 1. The SCI synchronizes with serial clock input or output and initializes internally. 2.
Page 514 Section 13 Serial Communication Interface Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt request handler reads Overrun error, request data in RDR ERI request and clears RDRF flag to 0 1 frame Figure 13.19 Example of SCI Receive Operation...
Page 515 Section 13 Serial Communication Interface 1. SCI initialization: the transmit data output Initialize function of the TxD pin and receive data input function of the RxD pin are selected, enabling simultaneous transmitting and Start transmitting and receiving receiving. 2. SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, Read TDRE flag in SSR then write transmit data in TDR and clear...
Page 516: Sci Interrupts
Section 13 Serial Communication Interface 13.4 SCI Interrupts The SCI has four interrupt request sources: TEI (transmit-end interrupt), ERI (receive-error interrupt), RXI (receive-data-full interrupt), and TXI (transmit-data-empty interrupt). Table 13.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, TEIE, and RIE bits in SCR.
Page 517: Usage Notes
Section 13 Serial Communication Interface 13.5 Usage Notes Note the following points when using the SCI. TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of transmit data from TDR into TSR. The SCI sets the TDRE flag to 1 when it transfers data from TDR to TSR.
Page 518 Section 13 Serial Communication Interface Sending a Break Signal: When the TE bit is cleared to 0 the TxD pin becomes an I/O port, the level and direction (input or output) of which are determined by DR and DDR bits. This feature can be used to send a break signal.
Page 519 Section 13 Serial Communication Interface The receive margin in asynchronous mode can therefore be expressed as in equation (1). D – 0.5 (1 + F) × 100% ....(1) M = (0.5 – ) – (L – 0.5) F – M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 16) D: Clock duty cycle (D = 0 to 1.0)
Page 520 Section 13 Serial Communication Interface Switching SCK Pin to Port Output Pin Function in Synchronous Mode: When the SCK pin is used as the serial clock output in synchronous mode, and is then switched to its output port function at the end of transmission, a low level may be output for one half-cycle. Half-cycle low- level output occurs when SCK is switched to its port function with the following settings when DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1.
Page 521 Section 13 Serial Communication Interface Sample Procedure for Avoiding Low-Level Output As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown.
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Page 523: Section 14 Smart Card Interface
Section 14 Smart Card Interface Section 14 Smart Card Interface 14.1 Overview As an extension of its serial communication interface functions, SCI0 supports a smart card (IC card) interface conforming to the ISO/IEC7816-3 (Identification Card) standard. Switchover between normal serial communication and the smart card interface is controlled by a register setting.
Page 524: Block Diagram
Section 14 Smart Card Interface 14.1.2 Block Diagram Figure 14.1 shows a block diagram of the smart card interface. Internal data Module data bus SCMR φ φ/4 φ/16 Transmit/receive Baud rate φ/64 control generator Parity generate Clock Parity check Legend: SCMR: Smart card mode register RSR:...
Page 525: Pin Configuration
Section 14 Smart Card Interface 14.1.3 Pin Configuration Table 14.1 lists the smart card interface pins. Table 14.1 Smart Card Interface Pins Name Abbreviation Function Serial clock pin Output Clock output Receive data pin Input Receive data input Transmit data pin Output Transmit data output 14.1.4...
Page 526: Register Descriptions
Section 14 Smart Card Interface 14.2 Register Descriptions This section describes the new or modified registers and bit functions in the smart card interface. 14.2.1 Smart Card Mode Register (SCMR) SCMR is an 8-bit readable/writable register that selects smart card interface functions. —...
Page 527: Serial Status Register (Ssr)
Section 14 Smart Card Interface Bit 2—Smart Card Data Inverter (SINV): Inverts data logic levels. This function is used in combination with bit 3 to communicate with inverse-convention cards. SINV does not affect the logic level of the parity bit. For parity settings, see section 14.3.4, Register Settings. Bit 2: SINV Description Unmodified TDR contents are transmitted...
Page 528 Section 14 Smart Card Interface Bits 7 to 5: These bits operate as in normal serial communication. For details see section 13, Serial Communication Interface. Bit 4—Error Signal Status (ERS): In smart card interface mode, this flag indicates the status of the error signal sent from the receiving device to the transmitting device.
Page 529: Serial Mode Register (Smr)
Section 14 Smart Card Interface 14.2.3 Serial Mode Register (SMR) Bit 7 of SMR has a different function in smart card interface mode. The related serial control register (SCR) changes from bit 1 to bit 0. STOP CKS1 CKS0 Initial value Read/Write Bit 7—GSM Mode (GM): Set at 0 when using the regular smart card interface.
Page 530: Serial Control Register (Scr)
Section 14 Smart Card Interface 14.2.4 Serial Control Register (SCR) Bits 1 and 0 have different functions in smart card interface mode. MPIE TEIE CKE1 CKE0 Initial value Read/Write Bits 7 to 2: Operate in the same way as for the normal SCI. For details, see section 13.2.6, Serial Control Register (SCR).
Page 531: Operation
Section 14 Smart Card Interface 14.3 Operation 14.3.1 Overview The main features of the smart-card interface are as follows. • One frame consists of eight data bits and a parity bit. • In transmitting, a guard time of at least two elementary time units (2 etu) is provided between the end of the parity bit and the start of the next frame.
Page 532 Section 14 Smart Card Interface Data line Clock line Px (port) H8/3052BF Reset line Smart card Chip Card-processing device Figure 14.2 Smart Card Interface Connection Diagram Note: A loop-back test can be performed by setting both RE and TE to 1 without connecting a smart card.
Page 533: Data Format
Section 14 Smart Card Interface 14.3.3 Data Format Figure 14.3 shows the data format of the smart card interface. In receive mode, parity is checked once per frame. If a parity error is detected, an error signal is returned to the transmitting device to request retransmission.
Page 534: Register Settings
Section 14 Smart Card Interface designated interval, the receiving device returns the signal line to the high-impedance state. The signal line is pulled back up to the high level through the pull-up resistor. 5. If the transmitting device does not receive an error signal, it proceeds to transmit the next data. If it receives an error signal, it returns to step 2 and transmits the same data again.
Page 535 Section 14 Smart Card Interface Smart Card Mode Register (SCMR): If the smart card follows the direct convention, clear the SDIR and SINV bits to 0. If the smart card follows the indirect convention, set the SDIR and SINV bits to 1. To use the smart card interface, set the SMIF bit to 1. The register settings and examples of starting character waveforms are shown below for two smart cards, one following the direct convention and one the inverse convention.
Page 536: Clock
Section 14 Smart Card Interface 14.3.5 Clock As its serial communication clock, the smart card interface can use only the internal clock generated by the on-chip baud rate generator. The bit rate can be selected by setting the bit rate register (BRR) and bits CKS1 and CKS0 in the serial mode register (SMR).
Page 537 Section 14 Smart Card Interface The following equation calculates the bit rate register (BRR) setting from the system clock frequency and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error. φ × 10 –...
Page 538: Transmitting And Receiving Data
Section 14 Smart Card Interface 14.3.6 Transmitting and Receiving Data Initialization: Before transmitting or receiving data, initialize the smart card interface by the procedure below. Initialization is also necessary when switching from transmit mode to receive mode or from receive mode to transmit mode. 1.
Page 539 Section 14 Smart Card Interface to enable interrupt requests, when a transmit error occurs and the ERS flag is set to 1, a transmit/receive-error interrupt (ERI) is requested. The timing of TEND flag setting depends on the GM bit in SMR. The timing is shown in figure 14.6.
Page 540 Section 14 Smart Card Interface (shift register) (1) Data write Data 1 (2) Transfer from Data 1 Data 1 ; Data remains in TDR TDR to TSR Data 1 I/O signal line output Data 1 (3) Serial data output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set...
Page 541 Section 14 Smart Card Interface Receiving Serial Data: The receiving procedure in smart card mode is the same as the normal SCI procedure. Figure 14.7 shows a flowchart for receiving. 1. Initialize the smart card interface by the procedure given in Initialization at the beginning of this section.
Page 542 Section 14 Smart Card Interface This procedure may include interrupt handling and DMA transfer. If the RIE bit is set to 1 to enable interrupt requests, when receiving is completed and the RDRF flag is set to 1, a receive-data-full interrupt (RXI) is requested. If a receive error occurs, either the ORER or PER flag is set to 1 and a transmit/receive-error interrupt (ERI) is requested.
Page 543 Section 14 Smart Card Interface Interrupt Operations: The smart card interface has three interrupt sources: transmit-data-empty (TXI), transmit/receive-error (ERI), and receive-data-full (RXI). The transmit-end interrupt request (TEI) is not available in smart card mode. A TXI interrupt is requested when the TEND flag is set to 1 in SSR. An RXI interrupt is requested when the RDRF flag is set to 1 in SSR.
Page 544 Section 14 Smart Card Interface Examples of Operation in GSM Mode: When switching between smart card interface mode and software standby mode, use the following procedures to maintain the clock duty cycle. • Switching from smart card interface mode to software standby mode 1.
Page 545: Usage Notes
Section 14 Smart Card Interface 14.4 Usage Notes When using the SCI as a smart card interface, note the following points. Receive Data Sampling Timing in Smart Card Mode and Receive Margin: In smart card mode the SCI operates on a base clock with 372 times the bit rate frequency. In receiving, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock.
Page 546 Section 14 Smart Card Interface From this equation, if F = 0 and D = 0.5 the receive margin is as follows. D = 0.5, F = 0 M = {0.5 – 1/(2 × 372)} × 100% = 49.866% Retransmission: Retransmission is described below for the separate cases of transmit mode and receive mode.
Page 547 Section 14 Smart Card Interface • Retransmission when SCI is in Transmit Mode (See Figure 14.12) 6. After transmitting one frame, if the receiving device returns an error signal, the SCI sets the ERS flag to 1 in SSR. If the RIE bit in SCR is set to the enable state, an ERI interrupt is requested.
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Page 549: Section 15 A/D Converter
Section 15 A/D Converter Section 15 A/D Converter 15.1 Overview The H8/3052BF includes a 10-bit successive-approximations A/D converter with a selection of up to eight analog input channels. When the A/D converter is not used, it can be halted independently to conserve power. For details see section 20.6, Module Standby Function.
Page 550: Block Diagram
Section 15 A/D Converter 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the A/D converter. Internal Module data bus data bus 10-bit D/A – φ/8 Comparator Analog Control circuit multi- plexer Sample-and- φ/16 hold circuit interrupt ADTRG signal Legend: ADCR: A/D control register...
Page 551: Pin Configuration
Section 15 A/D Converter 15.1.3 Pin Configuration Table 15.1 summarizes the A/D converter’s input pins. The eight analog input pins are divided into two groups: group 0 (AN to AN ), and group 1 (AN to AN ). AV and AV are the power supply for the analog circuits in the A/D converter.
Page 552: Register Configuration
Section 15 A/D Converter 15.1.4 Register Configuration Table 15.2 summarizes the A/D converter’s registers. Table 15.2 A/D Converter Registers Address * Name Abbreviation Initial Value H'FFE0 A/D data register A (high) ADDRAH H'00 H'FFE1 A/D data register A (low) ADDRAL H'00 H'FFE2 A/D data register B (high)
Page 553: Register Descriptions
Section 15 A/D Converter 15.2 Register Descriptions 15.2.1 A/D Data Registers A to D (ADDRA to ADDRD) — — — — — — ADDRn Initial value Read/Write (n = A to D) A/D conversion data Reserved bits 10-bit data giving an A/D conversion result The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion.
Page 554: A/D Control/Status Register (Adcsr)
Section 15 A/D Converter 15.2.2 A/D Control/Status Register (ADCSR) ADIE ADST SCAN Initial value Read/Write R/(W) Channel select 2 to 0 These bits select analog input channels Clock select Selects the A/D conversion time Scan mode Selects single mode or scan mode A/D start Starts or stops A/D conversion A/D interrupt enable...
Page 555 Section 15 A/D Converter Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the end of A/D conversion. Bit 6: ADIE Description A/D end interrupt request (ADI) is disabled (Initial value) A/D end interrupt request (ADI) is enabled Bit 5—A/D Start (ADST): Starts or stops A/D conversion.
Page 556: A/D Control Register (Adcr)
Section 15 A/D Converter Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog input channels. Clear the ADST bit to 0 before changing the channel selection. Group Selection Channel Selection Description Single Mode Scan Mode...
Page 557: Cpu Interface
Section 15 A/D Converter Bit 0—Reserved: Do not set to 1. 15.3 CPU Interface ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read through an 8-bit temporary register (TEMP).
Page 558: Operation
Section 15 A/D Converter 15.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 15.4.1 Single Mode (SCAN = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input.
Page 559 Section 15 A/D Converter Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) Rev. 3.00 Mar 21, 2006 page 531 of 814 REJ09B0302-0300...
Page 560: Scan Mode (Scan = 1)
Section 15 A/D Converter 15.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN when CH2 = 0, AN when CH2 = 1).
Page 561 Section 15 A/D Converter Figure 15.4 Example of A/D Converter Operation (Scan Mode, Channels AN to AN Selected) Rev. 3.00 Mar 21, 2006 page 533 of 814 REJ09B0302-0300...
Page 562: Input Sampling And A/D Conversion Time
Section 15 A/D Converter 15.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time t after the ADST bit is set to 1, then starts conversion. Figure 15.5 shows the A/D conversion timing.
Page 563: External Trigger Input Timing
Section 15 A/D Converter Table 15.4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Symbol Synchronization delay — — Input sampling time — — — — A/D conversion time — — CONV Note: Values in the table are numbers of states. 15.4.4 External Trigger Input Timing A/D conversion can be externally triggered.
Page 564: Interrupts
Section 15 A/D Converter 15.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. 15.6 Usage Notes When using the A/D converter, note the following points: 1.
Page 565 Section 15 A/D Converter 100 Ω in *2 to AN 0.1 µF Notes: 1. Numeric values are approximate. 10 µF 0.01 µF 2. R : input impedance Figure 15.7 Example of Analog Input Protection Circuit Table 15.5 Analog Input Pin Ratings Item Unit Analog input capacitance...
Page 566 Section 15 A/D Converter 3. A/D Conversion Accuracy Definitions A/D conversion accuracy in the H8/3052BF is defined as follows: • Resolution Digital output code length of A/D converter • Offset error Deviation from ideal A/D conversion characteristic of analog input voltage required to raise digital output from minimum voltage value 0000000000 to 0000000001 (figure 15.10) •...
Page 567 Section 15 A/D Converter Digital output Ideal A/D conversion characteristic Quantization error 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS Analog input voltage Figure 15.9 A/D Converter Accuracy Definitions (1) Rev. 3.00 Mar 21, 2006 page 539 of 814 REJ09B0302-0300...
Page 568 Section 15 A/D Converter Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog input Offset error voltage Figure 15.10 A/D Converter Accuracy Definitions (2) 4. Allowable Signal-Source Impedance The analog inputs of the H8/3052BF are designed to assure accurate conversion of input signals with a signal-source impedance not exceeding 10 kΩ.
Page 569 Section 15 A/D Converter 5. Effect on Absolute Accuracy Attaching an external capacitor creates a coupling with ground, so if there is noise on the ground line, it may degrade absolute accuracy. The capacitor must be connected to an electrically stable ground, such as AV If a filter circuit is used, be careful of interference with digital signals on the same board, and make sure the circuit does not act as an antenna.
Page 570 Section 15 A/D Converter Rev. 3.00 Mar 21, 2006 page 542 of 814 REJ09B0302-0300...
Page 571: Section 16 D/A Converter
Section 16 D/A Converter Section 16 D/A Converter 16.1 Overview The H8/3052BF includes a D/A converter with two channels. 16.1.1 Features D/A converter features are listed below. • Eight-bit resolution • Two output channels • Conversion time: maximum 10 µs (with 20-pF capacitive load) •...
Page 572: Block Diagram
Section 16 D/A Converter 16.1.2 Block Diagram Figure 16.1 shows a block diagram of the D/A converter. Internal Module data bus data bus 8-bit D/A Control circuit Legend: DACR: D/A control register DADR0: D/A data register 0 DADR1: D/A data register 1 DASTCR: D/A standby control register Figure 16.1 D/A Converter Block Diagram...
Page 573: Pin Configuration
Section 16 D/A Converter 16.1.3 Pin Configuration Table 16.1 summarizes the D/A converter’s input and output pins. Table 16.1 D/A Converter Pins Pin Name Abbreviation Function Analog power supply pin Input Analog power supply Analog ground pin Input Analog ground and reference voltage Analog output pin 0 Output Analog output, channel 0...
Page 574: Register Descriptions
Section 16 D/A Converter 16.2 Register Descriptions 16.2.1 D/A Data Registers 0 and 1 (DADR0/1) Initial value Read/Write The D/A data registers (DADR0 and DADR1) are 8-bit readable/writable registers that store the data to be converted. When analog output is enabled, the D/A data register values are constantly converted and output at the analog output pins.
Page 575 Section 16 D/A Converter Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output. Bit 7: DAOE1 Description analog output is disabled (Initial value) Channel-1 D/A conversion and DA analog output are enabled Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6: DAOE0 Description analog output is disabled...
Page 576: D/A Standby Control Register (Dastcr)
Section 16 D/A Converter 16.2.3 D/A Standby Control Register (DASTCR) DASTCR is an 8-bit readable/writable register that enables or disables D/A output in software standby mode. — — — — — — — DASTE Initial value Read/Write — — — —...
Page 577: Operation
Section 16 D/A Converter 16.3 Operation The D/A converter has two built-in D/A conversion circuits that can perform conversion independently. D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value is modified, conversion of the new data begins immediately. The conversion results are output when bits DAOE0 and DAOE1 are set to 1.
Page 578: D/A Output Control
Section 16 D/A Converter 16.4 D/A Output Control In the H8/3052BF, D/A converter output can be enabled or disabled in software standby mode. When the DASTE bit is set to 1 in DASTCR, D/A converter output is enabled in software standby mode.
Page 579: Section 17 Ram
Section 17 RAM Section 17 RAM 17.1 Overview The H8/3052BF has 8 kbytes of high-speed static RAM on-chip. The RAM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states, making the RAM useful for rapid data transfer.
Page 580: Block Diagram
Section 17 RAM 17.1.1 Block Diagram Figure 17.1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) Bus interface SYSCR H'FDF10* H'FDF11* H'FDF12* H'FDF13* On-chip RAM H'FFF0E* H'FFF0F* Even addresses Odd addresses Legend: SYSCR: System control register...
Page 581: Register Configuration
Section 17 RAM 17.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 17.1 gives the address and initial value of SYSCR. Table 17.1 System Control Register Address * Name Abbreviation Initial Value H'FFF2 System control register SYSCR H'0B Note: * Lower 16 bits of the address.
Page 582: Operation
Section 17 RAM Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized at the rising edge of the input at the RES pin. It is not initialized in software standby mode. Bit 0: RAME Description On-chip RAM is disabled On-chip RAM is enabled...
Page 583: Section 18 Rom
Section 18 ROM Section 18 ROM 18.1 Features The H8/3052BF has 512 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode ...
Page 584: Overview
Section 18 ROM • PROM mode Flash memory can be programmed/erased in PROM mode, using a PROM programmer, as well as in on-board programming mode. 18.2 Overview 18.2.1 Block Diagram Internal address bus Internal data bus (16 bits) FLMCR1 FLMCR2 Operating FWE pin Bus interface/controller...
Page 585 Section 18 ROM The boot, user program and PROM modes are provided as modes to write and erase the flash memory. Reset state * 1, * 3 RES = 0 User mode RES = 0 RES = 0 RES = 0 FWE = 1 FWE = 0 PROM mode...
Page 586 Section 18 ROM State transitions between the normal user mode and on-board programming mode are performed by changing the FWE pin level from high to low or from low to high. To prevent misoperation (erroneous programming or erasing) in these cases, the bits in the flash memory control registers (FLMCR1, FLMCR2) should be cleared to 0 before making such a transition.
Page 587: On-Board Programming Modes
Section 18 ROM 18.2.3 On-Board Programming Modes Boot Mode 1. Initial state 2. Programming control program transfer The old program version or data remains written When boot mode is entered, the boot program in in the flash memory. The user should prepare the the H8/3052F (originally incorporated in the chip) programming control program and new is started and the programming control program...
Page 588 Section 18 ROM User Program Mode 1. Initial state 2. Programming/erase control program transfer The FWE assessment program that confirms that When user program mode is entered, user user program mode has been entered, and the software confirms this fact, executes transfer program that will transfer the programming/erase program in the flash memory, and transfers the control program from flash memory to on-chip...
Page 589: Flash Memory Emulation In Ram
Section 18 ROM 18.2.4 Flash Memory Emulation in RAM In the H8/3052BF, flash memory programming can be emulated in real time by overlapping the flash memory with part of RAM ("overlap RAM"). When the emulation block set in RAMCR is accessed while the emulation function is being executed, data written in the overlap RAM is read.
Page 590: Differences Between Boot Mode And User Program Mode
Section 18 ROM Flash memory Programming data Overlap RAM Application program (programming data) Programming control program execution state Figure 18.4 Writing Overlap RAM Data in User Program Mode 18.2.5 Differences between Boot Mode and User Program Mode Item Boot Mode User Program Mode Total erase Block erase...
Page 591: Block Configuration
Section 18 ROM 18.2.6 Block Configuration The flash memory in the H8/3052BF is divided into seven 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. Address H'7FFFF 64 kbytes 64 kbytes 64 kbytes 64 kbytes 512 kB 64 kbytes 64 kbytes 64 kbytes 32 kbytes ×...
Page 592: Pin Configuration
Section 18 ROM 18.3 Pin Configuration The flash memory is controlled by means of the pins shown in table 18.1. Table 18.1 Pin Configuration Pin Name Abbreviation Function Reset Input Reset Flash write enable Input Flash program/erase protection by hardware Mode 2 Input Sets LSI operating mode...
Page 593: Register Descriptions
Section 18 ROM 18.5 Register Descriptions 18.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'00000 to H'3FFFF is entered by setting SWE1 bit to 1 when FWE = 1, then setting the PV1 or EV1 bit.
Page 594 Section 18 ROM Bit 5—Erase Setup Bit 1 (ESU1): Prepares for a transition to erase mode (applicable addresses: H'00000 to H'3FFFF). Do not set the SWE1, PSU1, EV1, PV1, E1, or P1 bit at the same time. Set this bit to 1 before setting bit E1 to 1 in FLMCR1. Bit 5: ESU1 Description Erase setup cleared...
Page 595 Section 18 ROM Bit 2—Program-Verify 1 (PV1): Selects program-verify mode transition or clearing (applicable addresses: H'00000 to H'3FFFF). Do not set the SWE1, ESU1, PSU1, EV1, E1, or P1 bit at the same time. Bit 2: PV1 Description Program-verify mode cleared (Initial value) Transition to program-verify mode [Setting condition]...
Page 596: Flash Memory Control Register 2 (Flmcr2)
Section 18 ROM 18.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'40000 to H'7FFFF is entered by setting SWE2 to 1 when FWE (FLMCR1) = 1, then setting the EV2 or PV2 bit.
Page 597 Section 18 ROM Bit 6—Software Write Enable Bit 2 (SWE2): Enables or disables flash memory programming and erasing (applicable addresses: H'40000 to H'7FFFF). Set this bit when setting bits 5 to 0 and bits 7 to 4 of EBR2. Bit 6: SWE2 Description Writes disabled (Initial value)
Page 598 Section 18 ROM Bit 3—Erase-Verify 2 (EV2): Selects erase-verify mode transition or clearing (applicable addresses: H'40000 to H'7FFFF). Do not set the ESU2, PSU2, PV2, E2, or P2 bit at the same time. Bit 3: EV2 Description Erase-verify mode cleared (Initial value) Transition to erase-verify mode [Setting condition]...
Page 599: Erase Block Register 1 (Ebr1)
Section 18 ROM 18.5.3 Erase Block Register 1 (EBR1) EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE1 bit in FLMCR1 is not set.
Page 600: Ram Control Register (Ramcr)
Section 18 ROM Table 18.3 Flash Memory Erase Blocks Block (Size) Addresses EB0 (4 kbytes) H'000000–H'000FFF EB1 (4 kbytes) H'001000–H'001FFF EB2 (4 kbytes) H'002000–H'002FFF EB3 (4 kbytes) H'003000–H'003FFF EB4 (4 kbytes) H'004000–H'004FFF EB5 (4 kbytes) H'005000–H'005FFF EB6 (4 kbytes) H'006000–H'006FFF EB7 (4 kbytes) H'007000–H'007FFF EB8 (32 kbytes)
Page 601 Section 18 ROM Bits 7 to 4—Reserved: These bits always read 1. Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory block are program/erase-protected. Bit 3: RAMS Description Emulation not selected (Initial value) Program/erase-protection of all flash memory blocks is disabled...
Page 602: On-Board Programming Modes
Section 18 ROM 18.6 On-Board Programming Modes When pins are set to on-board programming mode and a reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode.
Page 603 Section 18 ROM Flash memory Host Write data reception RXD1 SCI1 On-chip RAM Verify data transmission TXD1 Figure 18.6 System Configuration in Boot Mode Rev. 3.00 Mar 21, 2006 page 575 of 814 REJ09B0302-0300...
Page 604 Section 18 ROM 1. Set this LSI to the boot mode and reset starts the LSI. Start 2. Set the host to the prescribed bit rate (4800, 9600, 19200) and consecutively send H'00 data in 8-bit data, Set pins to boot program mode and execute reset-start 1 stop bit format.
Page 605 Section 18 ROM Automatic SCI Bit Rate Adjustment Start Stop Low period (9 bits) measured (H'00 data) High period (1 or more bits) When boot mode is initiated, the LSI measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity.
Page 606 Section 18 ROM On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the programming control program is transferred via the SCI, as shown in figure 18.8. The boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host.
Page 607 Section 18 ROM 5. This LSI terminates transmit and receive operations by the on-chip SCI(channel 1) (by clearing the RE and TE bits in serial control register (SCR)) before branching to the user program. However, the adjusted bit rate is held in the bit rate register (BRR). At this time, the TXD is in the high level output state (P9DDR P9 DDR=1, P9DR P9 DR=1).
Page 608: User Program Mode
Section 18 ROM H8/3052B F-ZTAT External memory, etc. System control unit Figure 18.9 Recommended System Block Diagram Notes: 1. The mode pin and FWE pin input must satisfy the mode programming setup time ) relative to the reset clear timing. 2.
Page 609 Section 18 ROM Procedure – MD = 101, 110, 111 The user writes a program that executes steps 3 to 8 in advance as shown below. 1. Sets the mode pin to an on-chip ROM enable mode (mode 5, 6, or 7). Reset start 2.
Page 610: Programming/Erasing Flash Memory
Section 18 ROM Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. 18.7 Programming/Erasing Flash Memory A software method, using the CPU, is employed to program and erase flash memory in the on- board programming modes.
Page 611 Section 18 ROM E1(2) = 1 Erase setup Erase mode state E1(2) = 0 Normal mode FWE = 1 FWE = 0 Erase-verify mode On-board SWE1(2) = 1 Software programming mode programming Software programming enable disable state SWE1(2) = 0 state P1(2) = 1 Program...
Page 612: Program Mode
Section 18 ROM 18.7.1 Program Mode When writing data or programs to flash memory, the program/program-verify flowchart shown in figure 18.12 should be followed. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability.
Page 613: Program-Verify Mode
Section 18 ROM 18.7.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of the given programming time, clear the P1 and P2 bits in FLMCR1 and FLMCR2, then wait for at least (tcp) µs before clearing the PSU1 and PSU2 bits to exit program mode.
Page 614 Section 18 ROM program/program-verify procedure is completed. In the H8/3052BF, the number of loops in reprogramming processing is guaranteed not to exceed the maximum programming count (N). b. After write pulse application, a verify-read is performed in program-verify mode, and programming is judged to have been completed for bits read as 0.
Page 615 Section 18 ROM Table 18.8 Reprogram Data Computation Table Result of Verify-Read after Write Pulse Application (V) Result of Operation Comments Programming completed: reprogramming processing not to be executed Programming incomplete: reprogramming processing to be executed  Still in erased state: no action Source data of bits on which programming is executed: (D) Data of bits on which reprogramming is executed: (X) Table 18.9 Additional-Programming Data Computation Table...
Page 616 Section 18 ROM Write pulse application subroutine Start of programming Perform programming in the erased state. START Sub-Routine Write Pulse Do not perform additional programming on previously programmed addresses. Set SWE1 (2) bit in FLMCR1 (2) WDT enable Wait (tsswe) µ...
Page 617: Erase Mode
Section 18 ROM 18.7.4 Erase Mode To erase an individual flash memory block, follow the erase/erase-verify flowchart (single-block erase) shown in figure 18.13. The wait times after bits are set or cleared in the flash memory control register (FLMCR1, FLMCR2) and the maximum number of erase operations (N) are shown in table 21.10 in section 21.2.5, Flash Memory Characteristics.
Page 618 Section 18 ROM If erasing multiple blocks, set a single bit in EBR1/EBR2 for the next block to be erased, and repeat the erase/erase-verify sequence as before. Start Perform erasing in block units. Set SWE1 (2) bit in FLMCR1 (2) Wait tsswe µs n = 1 Set EBR1 or EBR2...
Page 619: Protection
Section 18 ROM 18.8 Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 18.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2).
Page 620 Section 18 ROM Table 18.10 Hardware Protection Functions Verify * Item Description Program Erase No * No * • FWE pin — When a low level is input to the FWE pin, protection FLMCR1, FLMCR2, (except bit FLER) EBR1, and EBR2 are initialized, and the program/ erase-protected state is entered.
Page 621: Software Protection
Section 18 ROM 18.8.2 Software Protection Software protection can be implemented by setting the SWE1 bit in FLMCR1, the SWE2 bit in FLMCR2, erase block register 1 (EBR1), erase block register 2 (EBR2), and the RAMS bit in the RAM control register (RAMCR). When software protection is in effect, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), or the P2 or E2 bit in flash memory control register 2 (FLMCR2) does not cause a transition to program mode or erase mode.
Page 622: Error Protection
Section 18 ROM 18.8.3 Error Protection In error protection, an error is detected when H8/3052BF runaway occurs during flash memory programming/erasing * , or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing.
Page 623: Nmi Input Disable Conditions
Section 18 ROM Figure 18.14 shows the flash memory state transition diagram. Memory read verify mode RD VF PR ER FLER = 0 P = 1 or P = 0 and E = 1 E = 0 Reset or standby Program mode (hardware protection) Erase mode...
Page 624 Section 18 ROM This is done to avoid the following operation states: 1. Generation of an NMI input during programming/erasing violates the program/erase algorithms and normal operation can not longer be assured. 2. Vector-read cannot be carried out normally * during NMI exception handling during programming/erasing and the microcomputer runs away as a result.
Page 625: Flash Memory Emulation In Ram
Section 18 ROM 18.9 Flash Memory Emulation in RAM Making a setting in the RAM control register (RAMCR) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time.
Page 626 Section 18 ROM This area can be accessed from both the RAM area and flash memory area H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 H'FDF10 H'FE000 H'FEFFF Flash memory EB8 to EB15 On-chip RAM H'FFF0F H'7FFFF Figure 18.16 Example of RAM Overlap Operation Example in which Flash Memory Block Area EB0 is Overlapped 1.
Page 627: Flash Memory Prom Mode
The H8/3052BF has a PROM mode as well as the on-board programming modes for programming and erasing flash memory. In PROM mode, the on-chip ROM can be freely programmed using a general-purpose PROM writer that supports the Renesas Technology microcomputer device type with 512-kbyte on-chip flash memory.
Page 628: 18.10.2 Notes On Use Of Prom Mode
The memory is initially in the erased state when the device is shipped by Renesas. For samples for which the erasure history is unknown, it is recommended that erasing be executed to check and correct the initialization (erase) level.
Page 629: Notes On Flash Memory Programming/Erasing
1. Program/erase with the specified voltage and timing. Applied voltages in excess of the rating can permanently damage the device. Use a PROM writer that supports the Renesas 512 kbytes flash memory on-board microcomputer device type. If the wrong device type is set, a high level may be input to the FWE pin, resulting in permanent damage to the device.
Page 630 Section 18 ROM c. In the boot mode, perform FWE pin High/Low switching during reset. while the RES In transition to the boot mode, input FWE = High level and set MD to MD input is low. At this time, the FWE and MD to MD inputs must satisfy the mode programming setup time (t...
Page 631 Section 18 ROM Similarly perform flash memory program execution and data read after clearing the SWE bit even when using the RAM emulation function with a high level input to the FWE pin. However, RAM area that overlaps flash memory space can be read/programmed whether the SWE bit is set or cleared.
Page 632 Section 18 ROM Programming and erase possible Wait time: x φ Min 0 µs OSC1 Min 0 µs 200 ns to MD SWE1 (2) SWE1 (2) clear SWE1(2) bit Flash memory access disabled period (x: Wait time after SWE1 (2) setting) Flash memory reprogrammable period (Flash memory program execution and data read, other than verify, are disabled.) Notes:...
Page 633 Section 18 ROM Programming and erase possible Wait time: x φ Min 0 µs OSC1 to MD SWE1 (2) SWE1 (2) clear SWE1(2) bit Flash memory access disabled period (x: Wait time after SWE1(2) setting) Flash memory reprogrammable period (Flash memory program execution and data read, other than verify, are disabled.) Notes: 1.
Page 634 Section 18 ROM Programming Programming Programming Programming Wait Wait erase Wait Wait and erase and erase and erase time: x time: x possible time: x time: x possible possible possible φ OSC1 Min 0 µs to MD RESW SWE1 (2) set SWE1 (2) clear SWE1 (2) bit Mode switching...
Page 635: Section 19 Clock Pulse Generator
Section 19 Clock Pulse Generator Section 19 Clock Pulse Generator 19.1 Overview The H8/3052BF has a built-in clock pulse generator (CPG) that generates the system clock (φ) and other internal clock signals (φ/2 to φ/4096). After duty adjustment, a frequency divider divides the clock frequency to generate the system clock (φ).
Page 636: Block Diagram
Section 19 Clock Pulse Generator 19.1.1 Block Diagram Figure 19.1 shows a block diagram of the clock pulse generator. XTAL Duty φ Frequency Oscillator Prescalers adjustment divider circuit EXTAL Division control register Data bus φ φ/2 to φ/4096 Figure 19.1 Block Diagram of Clock Pulse Generator Rev.
Page 637: Oscillator Circuit
Section 19 Clock Pulse Generator 19.2 Oscillator Circuit Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock signal. 19.2.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as in the example in figure 19.2. The damping resistance Rd should be selected according to table 19.1 (1).
Page 638 Section 19 Clock Pulse Generator Table 19.1 (2) External Capacitance Values External Capacitance Values 5V operation 3V operation 20 < f ≤ 25 2≤ f ≤ 20 2≤ f ≤ 13 13≤ f ≤ 25 Frequency f (MHz) (pF) 10 to 22 10 to 22 Crystal Resonator: Figure 19.3 shows an equivalent circuit of the crystal resonator.
Page 639: External Clock Input
Section 19 Clock Pulse Generator Avoid Signal A Signal B H8/3052BF XTAL EXTAL Figure 19.4 Example of Incorrect Board Design 19.2.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 19.5.
Page 640 Section 19 Clock Pulse Generator External Clock: The external clock frequency should be equal to the system clock frequency (φ) when not divided by the on-chip frequency divider. Table 19.3 shows the clock timing, and figure 19.6 shows the external clock input timing. Figure 19.7 shows the external clock output stabilization delay timing.
Page 641: Duty Adjustment Circuit
Section 19 Clock Pulse Generator 2.7 V STBY EXTAL φ (internal or external) DEXT of RES pulse width (t Note: * t includes 10 t DEXT RESW Figure 19.7 External Clock Output Settling Delay Timing 19.3 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the signal that becomes the system clock.
Page 642: Register Configuration
Section 19 Clock Pulse Generator 19.5.1 Register Configuration Table 19.4 summarizes the frequency division register. Table 19.4 Frequency Division Register Address * Name Abbreviation Initial Value H'FF5D Division control register DIVCR H'FC Note: * The lower 16 bits of the address are shown. 19.5.2 Division Control Register (DIVCR) DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency...
Page 643: Usage Notes
Section 19 Clock Pulse Generator 19.5.3 Usage Notes The DIVCR setting changes the φ frequency, so note the following points. • Select a frequency division ratio that stays within the assured operation range specified for the in the AC electrical characteristics. Note that φ clock cycle time t = 2 MHz.
Page 644 Section 19 Clock Pulse Generator Rev. 3.00 Mar 21, 2006 page 616 of 814 REJ09B0302-0300...
Page 645: Section 20 Power-Down State
Section 20 Power-Down State Section 20 Power-Down State 20.1 Overview The H8/3052BF has a power-down state that greatly reduces power consumption by halting the CPU, and a module standby function that reduces power consumption by selectively halting on- chip modules. The power-down state includes the following three modes: •...
Page 646 Section 20 Power-Down State Table 20.1 Power-Down State and Module Standby Function Rev. 3.00 Mar 21, 2006 page 618 of 814 REJ09B0302-0300...
Page 647: Register Configuration
Section 20 Power-Down State 20.2 Register Configuration The H8/3052BF has a system control register (SYSCR) that controls the power-down state, and a module standby control register (MSTCR) that controls the module standby function. Table 20.2 summarizes these registers. Table 20.2 Control Register Address * Name Abbreviation...
Page 648 Section 20 Power-Down State Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal operation. To clear this bit, write 0. Bit 7: SSBY Description SLEEP instruction causes transition to sleep mode...
Page 649: Module Standby Control Register (Mstcr)
Section 20 Power-Down State 20.2.2 Module Standby Control Register (MSTCR) MSTCR is an 8-bit readable/writable register that controls output of the system clock (φ). It also controls the module standby function, which places individual on-chip supporting modules in the standby state. Module standby can be designated for the ITU, SCI0, SCI1, DMAC, refresh controller, and A/D converter modules.
Page 650 Section 20 Power-Down State Bit 4—Module Standby 4 (MSTOP4): Selects whether to place SCI0 in standby. Bit 4: MSTOP4 Description SCI0 operates normally (Initial value) SCI0 is in standby state Bit 3—Module Standby 3 (MSTOP3): Selects whether to place SCI1 in standby. Bit 3: MSTOP3 Description SCI1 operates normally...
Page 651: Sleep Mode
Section 20 Power-Down State 20.3 Sleep Mode 20.3.1 Transition to Sleep Mode When the SSBY bit is cleared to 0 in SYSCR, execution of the SLEEP instruction causes a transition from the program execution state to sleep mode. Immediately after executing the SLEEP instruction the CPU halts, but the contents of its internal registers are retained.
Page 652: Software Standby Mode
Section 20 Power-Down State 20.4 Software Standby Mode 20.4.1 Transition to Software Standby Mode To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in SYSCR. In software standby mode, current dissipation is reduced to an extremely low level because the CPU, clock, and on-chip supporting modules all halt.
Page 653: Selection Of Waiting Time For Exit From Software Standby Mode
Section 20 Power-Down State 20.4.3 Selection of Waiting Time for Exit from Software Standby Mode Bits STS2 to STS0 in SYSCR and bits DIV1 and DIV0 in DIVCR should be set as follows. Crystal Resonator: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time (for the clock to stabilize) is at least 7 ms.
Page 654 Section 20 Power-Down State Waiting DIV1 DIV0 STS2 STS1 STS0 Time 18 MHz 16 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz 1 MHz Unit 8192 16.4 32.8 states 16384 10.9 16.4 32.8 65.5 states 32768 10.9 13.1...
Page 655: Sample Application Of Software Standby Mode
Section 20 Power-Down State 20.4.4 Sample Application of Software Standby Mode Figure 20.1 shows an example in which software standby mode is entered at the fall of NMI and exited at the rise of NMI. With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an NMI interrupt occurs.
Page 656: Hardware Standby Mode
Section 20 Power-Down State 20.5 Hardware Standby Mode 20.5.1 Transition to Hardware Standby Mode Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin goes low. Hardware standby mode reduces power consumption drastically by halting all functions of the CPU, DMAC, refresh controller, and on-chip supporting modules.
Page 657: Module Standby Function
Section 20 Power-Down State 20.6 Module Standby Function 20.6.1 Module Standby Timing The module standby function can halt several of the on-chip supporting modules (the ITU, SCI0, SCI1, DMAC, refresh controller, and A/D converter) independently of the power-down state. This standby function is controlled by bits MSTOP5 to MSTOP0 in MSTCR.
Page 658: System Clock Output Disabling Function
Section 20 Power-Down State MSTCR Access from DMAC Disabled: To prevent malfunctions, MSTCR can only be accessed from the CPU. It can be read by the DMAC, but it cannot be written by the DMAC. 20.7 System Clock Output Disabling Function Output of the system clock (φ) can be controlled by the PSTOP bit in MSTCR.
Page 659: Section 21 Electrical Characteristics
Section 21 Electrical Characteristics Section 21 Electrical Characteristics 21.1 Absolute Maximum Ratings Table 21.1 lists the absolute maximum ratings. Table 21.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +7.0 Programming voltage HD64F3052B –0.3 to V + 0.3 (FWE) Input voltage (except for port 7)
Page 660: Electrical Characteristics
Section 21 Electrical Characteristics 21.2 Electrical Characteristics 21.2.1 DC Characteristics Table 21.2 lists the DC characteristics. Table 21.3 lists the permissible output currents. Table 21.2 DC Characteristics Conditions: V = 5.0 V ±10%, AV = 5.0 V ±10%, V = 4.5 V to AV = 0 V * = AV = –20°C to +75°C...
Page 661 Section 21 Electrical Characteristics Item Symbol Min Unit Test Conditions STBY, NMI, Input — — µA = 0.5 to RES, FWE, leakage – 0.5 V current to MD Port 7 — — µA = 0.5 to – 0.5 V Three-state Ports 1, 2, 3, —...
Page 662 Section 21 Electrical Characteristics Item Symbol Unit Test Conditions Reference During A/D — = 5.0 V current conversion During A/D and — D/A conversion Idle — 0.01 µA DASTE = 0 RAM standby voltage — — Notes: 1. If the A/D and D/A converters are not used, do not leave the AV , AV , and V pins...
Page 663 Section 21 Electrical Characteristics H8/3052BF 2 kΩ Port Darlington pair Figure 21.1 Darlington Pair Drive Circuit (Example) H8/3052BF Ports 1, 2, 5, 600 Ω and B Figure 21.2 LED Drive Circuit (Example) Rev. 3.00 Mar 21, 2006 page 635 of 814 REJ09B0302-0300...
Page 664: Ac Characteristics
Section 21 Electrical Characteristics 21.2.2 AC Characteristics Bus timing parameters are listed in table 21.4. Refresh controller bus timing parameters are listed in table 21.5. Control signal timing parameters are listed in table 21.6. Timing parameters of the on-chip supporting modules are listed in table 21.7. Table 21.4 Bus Timing Conditions: = 5.0 V ±10%, AV...
Page 665 Section 21 Electrical Characteristics Conditions Test Item Symbol Unit Conditions Read data access time 3 — 1.0 t - 28 Figure 21.4, ACC3 Figure 21.5 Read data access time 4 — 2.0 t - 32 ACC4 Precharge time 1.0 t - 20 —...
Page 666 Section 21 Electrical Characteristics Table 21.6 Control Signal Timing Conditions: = 5.0 V ±10%, AV = 5.0 V ±10%, V = 4.5 V to AV = 0 V, φ = 2 MHz to 25 MHz, T = AV = –20°C to +75°C Conditions Test Item...
Page 667 Section 21 Electrical Characteristics Table 21.7 Timing of On-Chip Supporting Modules Conditions: = 5.0 V ±10%, AV = 5.0 V ±10%, V = 4.5 V to AV = 0 V, φ = 2 MHz to 25 MHz, T = AV = –20°C to +75°C Conditions Test...
Page 668: A/D Conversion Characteristics
Section 21 Electrical Characteristics C = 90 pF: ports 4, 5, 6, 8, A (19 to 0), D (15 to 8), φ H8/3052B F-ZTAT C = 30 pF: ports 9, A, B output pin Ω R = 2.4 k Ω R = 12 k Input/output timing measurement levels •...
Page 669: D/A Conversion Characteristics
Section 21 Electrical Characteristics 21.2.4 D/A Conversion Characteristics Table 21.9 lists the D/A conversion characteristics. Table 21.9 D/A Converter Characteristics Conditions: = 5.0 V ±10%, AV = 5.0 V ±10%, V = 4.5 V to AV = 0 V, φ = 2 MHz to 25 MHz, T = AV = –20°C to +75°C Conditions...
Page 670: Flash Memory Characteristics
Section 21 Electrical Characteristics 21.2.5 Flash Memory Characteristics Table 21.10 Flash Memory Characteristics Conditions: = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, V = AV = 0 V, T = 0°C to +75°C (program/erase operating temperature range) Conditions Item Symbol Min...
Page 671: Operational Timing
Section 21 Electrical Characteristics Notes: 1. Set the times according to the program/erase algorithms. 2. Programming time per 128 bytes. (Shows the total time the P1 bit or P2 bit in the flash memory control register (FLMCR1 or FLMCR2) is set. It does not include the programming verification time.) 3.
Page 672 Section 21 Electrical Characteristics • Basic bus cycle: three-state access with one wait state Figure 21.6 shows the timing of the external three-state access cycle with one wait state inserted. φ to A to CS ACC3 ACC3 (read) ACC1 to D (read) HWR, LWR (write)
Page 673 Section 21 Electrical Characteristics φ to A ACC4 ACC4 RD (read) ACC2 to D (read) WSW2 HWR, LWR (write) WDS2 to D (write) Figure 21.5 Basic Bus Cycle: Three-State Access Rev. 3.00 Mar 21, 2006 page 645 of 814 REJ09B0302-0300...
Page 674 Section 21 Electrical Characteristics φ to A RD (read) to D (read) HWR, LWR (write) to D (write) WAIT Figure 21.6 Basic Bus Cycle: Three-State Access with One Wait State Rev. 3.00 Mar 21, 2006 page 646 of 814 REJ09B0302-0300...
Page 675: Refresh Controller Bus Timing
Section 21 Electrical Characteristics 21.3.2 Refresh Controller Bus Timing Refresh controller bus timing is shown as follows: • DRAM bus timing Figures 21.7 to 21.12 show the DRAM bus timing in each operating mode. • PSRAM bus timing Figures 21.13 and 21.14 show the pseudo-static RAM bus timing in each operating mode. φ...
Page 676 Section 21 Electrical Characteristics φ to A RAD3 (RAS) RAD2 RD (CAS) HWR (UW), LWR (LW) RAD2 RAD3 RFSH Figure 21.8 DRAM Bus Timing (Refresh Cycle): Three-State Access WE Mode — — 2WE φ CS (RAS) RD (CAS) RFSH Figure 21.9 DRAM Bus Timing (Self-Refresh Mode) —...
Page 677 Section 21 Electrical Characteristics φ to A RAD3 RAD1 CS (RAS HWR (UCAS), LWR (LCAS) RD (WE) (read) RD (WE) (write) RFSH to D (read) WDS3 to D (write) Figure 21.10 DRAM Bus Timing (Read/Write): Three-State Access CAS Mode — —...
Page 678 Section 21 Electrical Characteristics φ to A RAD3 CS (RAS) RAD2 HWR (UCAS), LWR (LCAS) RD (WE) RAD2 RAD3 RFSH Figure 21.11 DRAM Bus Timing (Refresh Cycle): Three-State Access — 2 CAS CAS Mode — φ CS (RAS) UCAS LCAS) RFSH Figure 21.12 DRAM Bus Timing (Self-Refresh Mode) —...
Page 679 Section 21 Electrical Characteristics φ to A RAD1 RAD3 RD (read) to D (read) HWR, LWR (write) WDS2 to D (write) RFSH Figure 21.13 PSRAM Bus Timing (Read/Write): Three-State Access φ to A , HWR, LWR, RD RAD2 RAD3 RFSH Figure 21.14 PSRAM Bus Timing (Refresh Cycle): Three-State Access Rev.
Page 680: Control Signal Timing
Section 21 Electrical Characteristics 21.3.3 Control Signal Timing Control signal timing is shown as follows: • Reset input timing Figure 21.15 shows the reset input timing. • Interrupt input timing Figure 21.16 shows the input timing for NMI and IRQ to IRQ •...
Page 681 Section 21 Electrical Characteristics φ NMIS NMIH NMIS NMIH NMIS IRQ : Edge-sensitive IRQ : Level-sensitive IRQ (i = 0 to 5) NMIW (j = 0 to 2) Figure 21.16 Interrupt Input Timing φ BRQS BRQS BREQ BACD2 BACD1 BACK to A AS, RD, HWR, LWR...
Page 682: Clock Timing
Section 21 Electrical Characteristics 21.3.4 Clock Timing Clock timing is shown as follows: • Oscillator settling timing Figure 21.18 shows the oscillator settling timing. φ STBY OSC1 OSC1 Figure 21.18 Oscillator Settling Timing 21.3.5 TPC and I/O Port Timing Figure 21.19 shows the TPC and I/O port timing. φ...
Page 683: Itu Timing
Section 21 Electrical Characteristics 21.3.6 ITU Timing ITU timing is shown as follows: • ITU input/output timing Figure 21.20 shows the ITU input/output timing. • ITU external clock input timing Figure 21.21 shows the ITU external clock input timing. φ TOCD Output compare...
Page 684: Sci Input/Output Timing
Section 21 Electrical Characteristics 21.3.7 SCI Input/Output Timing SCI timing is shown as follows: • SCI input clock timing Figure 21.22 shows the SCK input clock timing. • SCI input/output timing (synchronous mode) Figure 21.23 shows the SCI input/output timing in synchronous mode. SCKW SCKr SCKf...
Page 685: Dmac Timing
Section 21 Electrical Characteristics 21.3.8 DMAC Timing DMAC timing is shown as follows. • DMAC TEND output timing for 2 state access Figure 21.24 shows the DMAC TEND output timing for 2 state access. • DMAC TEND output timing for 3 state access Figure 21.25 shows the DMAC TEND output timing for 3 state access.
Page 686 Section 21 Electrical Characteristics Rev. 3.00 Mar 21, 2006 page 658 of 814 REJ09B0302-0300...
Page 687: Appendix A Instruction Set
Appendix A Instruction Set Appendix A Instruction Set Instruction List Operand Notation Symbol Description General destination register General source register General register General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) (EAd) Destination operand (EAs)
Page 688 Appendix A Instruction Set Condition Code Notation Symbol Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes Rev.
Page 689 Appendix A Instruction Set Table A.1 Instruction Set 1. Data transfer instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation #xx:8 → Rd8 MOV.B #xx:8, Rd — — — Rs8 → Rd8 MOV.B Rs, Rd —...
Page 690 Appendix A Instruction Set Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation ERd32–2 → ERd32 MOV.W Rs, @–ERd — — — Rs16 → @ERd Rs16 → @aa:16 MOV.W Rs, @aa:16 — — — Rs16 → @aa:24 MOV.W Rs, @aa:24 —...
Page 691 Appendix A Instruction Set 2. Arithmetic instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Rd8+#xx:8 → Rd8 ADD.B #xx:8, Rd — Rd8+Rs8 → Rd8 ADD.B Rs, Rd — Rd16+#xx:16 → Rd16 ADD.W #xx:16, Rd —...
Page 692 Appendix A Instruction Set Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation ERd32–1 → ERd32 DEC.L #1, ERd — — — ERd32–2 → ERd32 DEC.L #2, ERd — — — DAS.Rd Rd8 decimal adjust — —...
Page 693 Appendix A Instruction Set Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation 0–Rd8 → Rd8 NEG.B Rd — 0–Rd16 → Rd16 NEG.W Rd — 0–ERd32 → ERd32 NEG.L ERd — 0 → (<bits 15 to 8> EXTU.W Rd —...
Page 694 Appendix A Instruction Set 3. Logic instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Rd8∧#xx:8 → Rd8 AND.B #xx:8, Rd — — — Rd8∧Rs8 → Rd8 AND.B Rs, Rd — — — Rd16∧#xx:16 → Rd16 AND.W #xx:16, Rd —...
Page 695 Appendix A Instruction Set 4. Shift instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation SHAL.B Rd — — SHAL.W Rd — — SHAL.L ERd — — SHAR.B Rd — — SHAR.W Rd — — SHAR.L ERd —...
Page 696 Appendix A Instruction Set 5. Bit manipulation instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation (#xx:3 of Rd8) ← 1 BSET #xx:3, Rd — — — — — — (#xx:3 of @ERd) ← 1 BSET #xx:3, @ERd —...
Page 697 Appendix A Instruction Set Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation (#xx:3 of @ERd) → C BLD #xx:3, @ERd — — — — — (#xx:3 of @aa:8) → C BLD #xx:3, @aa:8 — — —...
Page 698 Appendix A Instruction Set 6. Branching instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Branch Condition BRA d:8 (BT d:8) — If condition Always — — — — — — is true then BRA d:16 (BT d:16) —...
Page 699 Appendix A Instruction Set Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation PC ← ERn JMP @ERn — — — — — — — PC ← aa:24 JMP @aa:24 — — — — — — —...
Page 700 Appendix A Instruction Set 7. System control instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation PC → @–SP TRAPA #x:2 — — — — — — CCR → @–SP <vector> → PC CCR ← @SP+ —...
Page 701 Appendix A Instruction Set 8. Block transfer instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation if R4L ≠ 0 then EEPMOV. B — — — — — — — repeat @R5 → @R6 R5+1 → R5 R6+1 →...
Page 702: Operation Code Map
Appendix A Instruction Set Operation Code Map Table A.2 Operation Code Map Rev. 3.00 Mar 21, 2006 page 674 of 814 REJ09B0302-0300...
Page 703 Appendix A Instruction Set Rev. 3.00 Mar 21, 2006 page 675 of 814 REJ09B0302-0300...
Page 704 Appendix A Instruction Set Rev. 3.00 Mar 21, 2006 page 676 of 814 REJ09B0302-0300...
Page 705: Number Of States Required For Execution
Appendix A Instruction Set Number of States Required for Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8/300H CPU. Table A.4 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction.
Page 706 Appendix A Instruction Set Table A.3 Number of States per Cycle Access Conditions On-Chip External Device Supporting Module 8-Bit Bus 16-Bit Bus On-Chip 8-Bit 16-Bit 2-State 3-State 2-State 3-State Cycle Memory Access Access Access Access Instruction fetch 6 + 2 m 3 + m Branch address read Stack operation...
Page 707 Appendix A Instruction Set Table A.4 Number of Cycles per Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS...
Page 708 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16...
Page 709 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8 BLD #xx:3, Rd BLD #xx:3, @ERd BLD #xx:3, @aa:8 BNOT BNOT #xx:3, Rd BNOT #xx:3, @ERd...
Page 710 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BXOR BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd...
Page 711 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic Normal * JSR @ERn Advanced Normal * JSR @aa:24 Advanced JSR @@aa:8 Normal * Advanced LDC #xx:8, CCR LDC Rs, CCR LDC @ERs, CCR LDC @(d:16, ERs), CCR LDC @(d:24, ERs), CCR...
Page 712 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.W @(d:24, ERs), Rd 4 MOV.W @ERs+, Rd MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd MOV.W Rs, @(d:16, ERd) 2 MOV.W Rs, @(d:24, ERd) 4 MOV.W Rs, @–ERd MOV.W Rs, @aa:16...
Page 713 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd ORC #xx:8, CCR POP.W Rn...
Page 714 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR SHLR.B Rd SHLR.W Rd SHLR.L ERd SLEEP SLEEP STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16, ERd) STC CCR, @(d:24, ERd)
Page 715: Appendix B Internal I/O Register
Appendix B Internal I/O Register Appendix B Internal I/O Register Addresses Data Bit Names Address Register Module (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'1C Reserved area (access prohibited) H'1D H'1E H'1F...
Page 716 Appendix B Internal I/O Register Data Bit Names Address Register Module (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'30 MAR1AR DMAC channel 1A H'31 MAR1AE H'32 MAR1AH H'33 MAR1AL H'34...
Page 717 Appendix B Internal I/O Register Data Bit Names Address Register Module (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'4C Reserved area (access prohibited) H'4D H'4E H'4F H'50 H'51 H'52 H'53...
Page 718 Appendix B Internal I/O Register Data Bit Names Address Register Module (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'70 TIER1 — — — — — OVIE IMIEB IMIEA ITU channel 1 H'71...
Page 719 Appendix B Internal I/O Register Data Bit Names Address Register Module (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'94 TIER4 — — — — — OVIE IMIEB IMIEA ITU channel 4 H'95...
Page 720 Appendix B Internal I/O Register Data Bit Names Address Register Module (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'B0 C/A/GM CHR STOP CKS1 CKS0 SCI channel 0 H'B1 H'B2 MPIE...
Page 721 Appendix B Internal I/O Register Data Bit Names Address Register Module (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'D4 PBDDR DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB...
Page 722 Appendix B Internal I/O Register Bit Names Data Address Register Module (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'FA Reserved area (access prohibited) H'FB H'FC H'FD H'FE H'FF Legend: DMAC: DMA controller...
Page 723: Function
Appendix B Internal I/O Register Function Register Register Address to which Name of on-chip acronym name the register is mapped supporting module TSTR Timer Start Register H'60 ITU (all channels) numbers Initial bit — — — STR4 STR3 STR2 STR1 STR0 values Initial value...
Page 724 Appendix B Internal I/O Register MAR0A R/E/H/L—Memory Address Register 0A R/E/H/L H'20, H'21, DMAC0 H'22, H'23 Initial value Undetermined Undetermined Read/Write — — — — — — — — MAR0AR MAR0AE Initial value Undetermined Undetermined Read/Write MAR0AH MAR0AL Source or destination address Rev.
Page 725 Appendix B Internal I/O Register ETCR0A H/L—Execute Transfer Count Register 0A H/L H'24, H'25 DMAC0 • Short address mode  I/O mode and idle mode Initial value Undetermined Read/Write Transfer counter  Repeat mode Initial value Undetermined Read/Write ETCR0AH Transfer counter Initial value Undetermined Read/Write...
Page 726 Appendix B Internal I/O Register ETCR0A H/L—Execute Transfer Count Register 0A H/L H'24, H'25 DMAC0 (cont) • Full address mode  Normal mode Initial value Undetermined Read/Write Transfer counter  Block transfer mode Initial value Undetermined Read/Write ETCR0AH Block size counter Initial value Undetermined Read/Write...
Page 727 Appendix B Internal I/O Register IOAR0A—I/O Address Register 0A H'26 DMAC0 Initial value Undetermined Read/Write Short address mode: source or destination address Full address mode: not used Rev. 3.00 Mar 21, 2006 page 699 of 814 REJ09B0302-0300...
Page 728 Appendix B Internal I/O Register DTCR0A—Data Transfer Control Register 0A H'27 DMAC0 • Short address mode DTSZ DTID DTIE DTS2 DTS1 DTS0 Initial value Read/Write Data transfer select Bit 2 Bit 1 Bit 0 DTS2 DTS1 DTS0 Data Transfer Activation Source Compare match/input capture A interrupt from ITU channel 0 Compare match/input capture A interrupt from ITU channel 1 Compare match/input capture A interrupt from ITU channel 2...
Page 729 Appendix B Internal I/O Register DTCR0A—Data Transfer Control Register 0A (cont) H'27 DMAC0 • Full address mode DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A Initial value Read/Write Data transfer select 0A 0 Normal mode 1 Block transfer mode Data transfer select 2A and 1A Set both bits to 1 Data transfer interrupt enable 0 Interrupt request by DTE bit is disabled...
Page 730 Appendix B Internal I/O Register MAR0B R/E/H/L—Memory Address Register 0B R/E/H/L H'28, H'29, DMAC0 H'2A, H'2B Initial value Undetermined Undetermined Read/Write — — — — — — — — MAR0BR MAR0BE Initial value Undetermined Undetermined Read/Write MAR0BH MAR0BL Source or destination address Rev.
Page 731 Appendix B Internal I/O Register ETCR0B H/L—Execute Transfer Count Register 0B H/L H'2C, H'2D DMAC0 • Short address mode  I/O mode and idle mode Initial value Undetermined Read/Write Transfer counter  Repeat mode Initial value Undetermined Read/Write ETCR0BH Transfer counter Initial value Undetermined Read/Write...
Page 732 Appendix B Internal I/O Register ETCR0B H/L—Execute Transfer Count Register 0B H/L H'2C, H'2D DMAC0 (cont) • Full address mode  Normal mode Initial value Undetermined Read/Write Not used  Block transfer mode Initial value Undetermined Read/Write Block transfer counter IOAR0B—I/O Address Register 0B H'2E DMAC0...
Page 733 Appendix B Internal I/O Register DTCR0B—Data Transfer Control Register 0B H'2F DMAC0 • Short address mode DTSZ DTID DTIE DTS2 DTS1 DTS0 Initial value Read/Write Data transfer select Bit 2 Bit 1 Bit 0 DTS2 DTS1 DTS0 Data Transfer Activation Source Compare match/input capture A interrupt from ITU channel 0 Compare match/input capture A interrupt from ITU channel 1 Compare match/input capture A interrupt from ITU channel 2...
Page 734 Appendix B Internal I/O Register DTCR0B—Data Transfer Control Register 0B (cont) H'2F DMAC0 • Full address mode DTME — DAID DAIDE DTS2B DTS1B DTS0B Initial value Read/Write Data transfer select 2B to 0B Bit 2 Bit 1 Bit 0 Data Transfer Activation Source DTS2B DTS1B DTS0B...
Page 735 Appendix B Internal I/O Register MAR1A R/E/H/L—Memory Address Register 1A R/E/H/L H'30, H'31, DMAC1 H'32, H'33 Undetermined Undetermined Initial value Read/Write — — — — — — — — MAR1AR MAR1AE Undetermined Undetermined Initial value Read/Write MAR1AH MAR1AL Note: Bit functions are the same as for DMAC0. Rev.
Page 736 Appendix B Internal I/O Register ETCR1A H/L—Execute Transfer Count Register 1A H/L H'34, H'35 DMAC1 Initial value Undetermined Read/Write Initial value Undetermined Read/Write ETCR1AH Initial value Undetermined Read/Write ETCR1AL Note: Bit functions are the same as for DMAC0. IOAR1A—I/O Address Register 1A H'36 DMAC1 Initial value...
Page 737 Appendix B Internal I/O Register DTCR1A—Data Transfer Control Register 1A H'37 DMAC1 • Short address mode DTSZ DTID DTIE DTS2 DTS1 DTS0 Initial value Read/Write • Full address mode DTSZ SAID SAIDE DTIE DTS2A DTS1A DTS0A Initial value Read/Write Note: Bit functions are the same as for DMAC0. MAR1B R/E/H/L—Memory Address Register 1B R/E/H/L H'38, H'39, DMAC1...
Page 738 Appendix B Internal I/O Register ETCR1B H/L—Execute Transfer Count Register 1B H/L H'3C, H'3D DMAC1 Initial value Undetermined Read/Write Initial value Undetermined Read/Write ETCR1BH Initial value Undetermined Read/Write ETCR1BL Note: Bit functions are the same as for DMAC0. IOAR1B—I/O Address Register 1B H'3E DMAC1 Initial value...
Page 739 Appendix B Internal I/O Register DTCR1B—Data Transfer Control Register 1B H'3F DMAC1 • Short address mode DTSZ DTID DTIE DTS2 DTS1 DTS0 Initial value Read/Write • Full address mode DTME — DAID DAIDE DTS2B DTS1B DTS0B Initial value Read/Write Note: Bit functions are the same as for DMAC0. Rev.
Page 740 Appendix B Internal I/O Register FLMCR1—Flash Memory Control Register 1 H'40 Flash memory SWE1 ESU1 PSU1 Initial value * Read/Write R/W* R/W* R/W* R/W* R/W* R/W* R/W* Program mode 1 0 Program mode cleared (Initial value) 1 Transition to program mode Erase mode 1 0 Erase mode cleared (Initial value)
Page 741 Appendix B Internal I/O Register FLMCR2—Flash Memory Control Register 2 H'41 Flash memory FLER SWE2 ESU2 PSU2 Initial value * Read/Write R/W* R/W* R/W* R/W* R/W* R/W* R/W* Program mode 2 0 Program mode cleared (Initial value) 1 Transition to program mode Erase mode 2 0 Erase mode cleared (Initial value)
Page 742 Appendix B Internal I/O Register EBR1—Erase Block Register 1 H'42 Flash memory Initial value * Read/Write R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Erase block specification bits (1) 0 Erase protection state 1 Erasable state Note: * The initial value is H'00 in modes 5, 6 and 7 (on-chip ROM enabled). In modes 1, 2, 3, and 4 (on-chip ROM disabled), this register cannot be modified and is always read as H'FF.
Page 743 Appendix B Internal I/O Register RAMCR—RAM Control Register H'47 Flash memory — — — — RAMS RAM2 RAM1 RAM0 Initial value * Read/Write RAM select, RAM 2 to RAM 0 Bit 3 Bit 2 Bit 1 Bit 0 RAM Area RAMS RAM 2 RAM 1...
Page 744 Appendix B Internal I/O Register DASTCR—D/A Standby Control Register H'5C System control — — — — — — — DASTE Initial value Read/Write — — — — — — — D/A standby enable 0 D/A output is disabled in software standby mode 1 D/A output is enabled in software standby mode DIVCR—Division Control Register H'5D...
Page 745 Appendix B Internal I/O Register MSTCR—Module Standby Control Register H'5E System control PSTOP — MSTOP5 MSTOP4 MSTOP3 MSTOP2 MSTOP1 MSTOP0 Initial value Read/Write — Module standby 0 0 A/D converter operates normally (Initial value) 1 A/D converter is in standby state Module standby 1 0 Refresh controller operates normally (Initial value)
Page 746 Appendix B Internal I/O Register CSCR—Chip Select Control Register H'5F System control CS7E CS6E CS5E CS4E — — — — Initial value Read/Write — — — — Chip select 7 to 4 enable Bit n CSnE Description Output of chip select signal CSn is disabled (Initial value) Output of chip select signal CSn is enabled (n = 7 to 4)
Page 747 Appendix B Internal I/O Register TSTR—Timer Start Register H'60 ITU (all channels) — — — STR4 STR3 STR2 STR1 STR0 Initial value Read/Write — — — Counter start 0 0 TCNT0 is halted 1 TCNT0 is counting Counter start 1 0 TCNT1 is halted 1 TCNT1 is counting Counter start 2...
Page 748 Appendix B Internal I/O Register TSNC—Timer Synchro Register H'61 ITU (all channels) — — — SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value Read/Write — — — Timer sync 0 0 TCNT0 operates independently 1 TCNT0 is synchronized Timer sync 1 0 TCNT1 operates independently 1 TCNT1 is synchronized Timer sync 2...
Page 749 Appendix B Internal I/O Register TMDR—Timer Mode Register H'62 ITU (all channels) — FDIR PWM4 PWM3 PWM2 PWM1 PWM0 Initial value Read/Write — PWM mode 0 0 Channel 0 operates normally 1 Channel 0 operates in PWM mode PWM mode 1 0 Channel 1 operates normally 1 Channel 1 operates in PWM mode PWM mode 2...
Page 750 Appendix B Internal I/O Register TFCR—Timer Function Control Register H'63 ITU (all channels) — — CMD1 CMD0 BFB4 BFA4 BFB3 BFA3 Initial value Read/Write — — Buffer mode A3 0 GRA3 operates normally 1 GRA3 is buffered by BRA3 Buffer mode B3 0 GRB3 operates normally 1 GRB3 is buffered by BRB3 Buffer mode A4...
Page 751 Appendix B Internal I/O Register TCR0—Timer Control Register 0 H'64 ITU0 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Timer prescaler 2 to 0 Bit 2 Bit 1 Bit 0 TPSC2 TPSC1 TPSC0 TCNT Clock Source Internal clock: φ...
Page 752 Appendix B Internal I/O Register TIOR0—Timer I/O Control Register 0 H'65 ITU0 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — I/O control A2 to A0 Bit 2 Bit 1 Bit 0 IOA2 IOA1 IOA0 GRA Function GRA is an output No output at compare match compare register...
Page 753 Appendix B Internal I/O Register TIER0—Timer Interrupt Enable Register 0 H'66 ITU0 — — — — — OVIE IMIEB IMIEA Initial value Read/Write — — — — — Input capture/compare match interrupt enable A 0 IMIA interrupt requested by IMFA flag is disabled 1 IMIA interrupt requested by IMFA flag is enabled Input capture/compare match interrupt enable B 0 IMIB interrupt requested by IMFB flag is disabled...
Page 754 Appendix B Internal I/O Register TSR0—Timer Status Register 0 H'67 ITU0 — — — — — IMFB IMFA Initial value Read/Write — — — — — R/(W) R/(W) R/(W) Input capture/compare match flag A 0 [Clearing condition] Read IMFA when IMFA = 1, then write 0 in IMFA 1 [Setting conditions] •...
Page 755 Appendix B Internal I/O Register TCNT0 H/L—Timer Counter 0 H/L H'68, H'69 ITU0 Initial value Read/Write Up-counter GRA0 H/L—General Register A0 H/L H'6A, H'6B ITU0 Initial value Read/Write Output compare or input capture register GRB0 H/L—General Register B0 H/L H'6C, H'6D ITU0 Initial value Read/Write...
Page 756 Appendix B Internal I/O Register TIOR1—Timer I/O Control Register 1 H'6F ITU1 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — Note: Bit functions are the same as for ITU0. TIER1—Timer Interrupt Enable Register 1 H'70 ITU1 —...
Page 757 Appendix B Internal I/O Register GRA1 H/L—General Register A1 H/L H'74, H'75 ITU1 Initial value Read/Write Note: Bit functions are the same as for ITU0. GRB1 H/L—General Register B1 H/L H'76, H'77 ITU1 Initial value Read/Write Note: Bit functions are the same as for ITU0. TCR2—Timer Control Register 2 H'78 ITU2...
Page 758 Appendix B Internal I/O Register TIOR2—Timer I/O Control Register 2 H'79 ITU2 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — Note: Bit functions are the same as for ITU0. TIER2—Timer Interrupt Enable Register 2 H'7A ITU2 —...
Page 759 Appendix B Internal I/O Register TCNT2 H/L—Timer Counter 2 H/L H'7C, H'7D ITU2 Initial value Read/Write Phase counting mode: up/down counter Other modes: up-counter GRA2 H/L—General Register A2 H/L H'7E, H'7F ITU2 Initial value Read/Write Note: Bit functions are the same as for ITU0. GRB2 H/L—General Register B2 H/L H'80, H'81 ITU2...
Page 760 Appendix B Internal I/O Register TCR3—Timer Control Register 3 H'82 ITU3 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Note: Bit functions are the same as for ITU0. TIOR3—Timer I/O Control Register 3 H'83 ITU3 — IOB2 IOB1 IOB0...
Page 761 Appendix B Internal I/O Register TSR3—Timer Status Register 3 H'85 ITU3 — — — — — IMFB IMFA Initial value Read/Write — — — — — R/(W) R/(W) R/(W) Bit functions are the same as for ITU0 Overflow flag 0 [Clearing condition] Read OVF when OVF = 1, then write 1 in OVF 1 [Setting condition] TCNT overflowed from H'FFFF to H'0000 or underflowed from...
Page 762 Appendix B Internal I/O Register GRB3 H/L—General Register B3 H/L H'8A, H'8B ITU3 Initial value Read/Write Output compare or input capture register (can be buffered) BRA3 H/L—Buffer Register A3 H/L H'8C, H'8D ITU3 Initial value Read/Write Used in combination with GRA when buffer operation is selected BRB3 H/L—Buffer Register B3 H/L H'8E, H'8F ITU3...
Page 763 Appendix B Internal I/O Register TOER—Timer Output Enable Register H'90 ITU (all channels) — — EXB4 EXA4 Initial value Read/Write — — Master enable TIOCA3 0 TIOCA output is disabled regardless of TIOR3, TMDR, and TFCR settings 1 TIOCA is enabled for output according to TIOR3, TMDR, and TFCR settings Master enable TIOCA4 0 TIOCA output is disabled regardless of TIOR4, TMDR, and TFCR settings 1 TIOCA is enabled for output according to TIOR4, TMDR, and TFCR settings...
Page 764 Appendix B Internal I/O Register TOCR—Timer Output Control Register H'91 ITU (all channels) — — — XTGD — — OLS4 OLS3 Initial value Read/Write — — — — — Output level select 3 0 TIOCB , TOCXA , and TOCXB outputs are inverted 1 TIOCB , TOCXA , and TOCXB outputs are not inverted Output level select 4 0 TIOCA , TIOCA , and TIOCB outputs are inverted...
Page 765 Appendix B Internal I/O Register TCR4—Timer Control Register 4 H'92 ITU4 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Note: Bit functions are the same as for ITU0. TIOR4—Timer I/O Control Register 4 H'93 ITU4 — IOB2 IOB1 IOB0...
Page 766 Appendix B Internal I/O Register TCNT4 H/L—Timer Counter 4 H/L H'96, H'97 ITU4 Initial value Read/Write Note: Bit functions are the same as for ITU3. GRA4 H/L—General Register A4 H/L H'98, H'99 ITU4 Initial value Read/Write Note: Bit functions are the same as for ITU3. GRB4 H/L—General Register B4 H/L H'9A, H'9B ITU4...
Page 767 Appendix B Internal I/O Register BRB4 H/L—Buffer Register B4 H/L H'9E, H'9F ITU4 Initial value Read/Write Note: Bit functions are the same as for ITU3. TPMR—TPC Output Mode Register H'A0 — — — — G3NOV G2NOV G1NOV G0NOV Initial value Read/Write —...
Page 768 Appendix B Internal I/O Register TPCR—TPC Output Control Register H'A1 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 0 compare match select 1 and 0 Bit 1 Bit 0 G0CMS1 G0CMS0 ITU Channel Selected as Output Trigger TPC output group 0 (TP to TP ) is triggered by compare match in ITU channel 0 TPC output group 0 (TP to TP ) is triggered by compare match in ITU channel 1 TPC output group 0 (TP to TP ) is triggered by compare match in ITU channel 2...
Page 769 Appendix B Internal I/O Register NDERB—Next Data Enable Register B H'A2 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value Read/Write Next data enable 15 to 8 Bits 7 to 0 NDER15 to NDER8 Description TPC outputs TP to TP are disabled (NDR15 to NDR8 are not transferred to PB to PB ) TPC outputs TP to TP are enabled...
Page 770 Appendix B Internal I/O Register NDRB—Next Data Register B H'A4/H'A6 • Same trigger for TPC output groups 2 and 3  Address H'FFA4 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value Read/Write Store the next output data for Store the next output data for TPC output group 3 TPC output group 2...
Page 771 Appendix B Internal I/O Register NDRA—Next Data Register A H'A5/H'A7 • Same trigger for TPC output groups 0 and 1  Address H'FFA5 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value Read/Write Store the next output data for Store the next output data for TPC output group 1 TPC output group 0...
Page 772 Appendix B Internal I/O Register  Address H'FFA7 — — — — NDR3 NDR2 NDR1 NDR0 Initial value Read/Write — — — — Store the next output data for TPC output group 0 TCSR—Timer Control/Status Register H'A8 — — CKS2 CKS1 CKS0 Initial value...
Page 773 Appendix B Internal I/O Register TCNT—Timer Counter H'A9 (read), H'A8 (write) Initial value Read/Write Count value RSTCSR—Reset Control/Status Register H'AB (read), H'AA (write) WRST — — — — — — — Initial value Read/Write R/(W) — — — — — —...
Page 774 Appendix B Internal I/O Register RFSHCR—Refresh Control Register H'AC Refresh controller SRFMD PSRAME DRAME CAS/ RFSHE — RCYCE Initial value Read/Write — Refresh cycle enable 0 Refresh cycles are disabled 1 Refresh cycles are enabled for area 3 Refresh pin enable Refresh signal output at the RFSH pin is disabled...
Page 775 Appendix B Internal I/O Register RTMCSR—Refresh Timer Control/Status Register H'AD Refresh controller CMIE CKS2 CKS1 CKS0 — — — Initial value Read/Write R/(W) — — — Clock select 2 to 0 Bit 5 Bit 4 Bit 3 CKS2 CKS1 CKS0 Counter Clock Source Clock input is disabled φ/2...
Page 776 Appendix B Internal I/O Register RTCNT—Refresh Timer Counter H'AE Refresh controller Initial value Read/Write Count value RTCOR—Refresh Time Constant Register H'AF Refresh controller Initial value Read/Write Interval at which RTCNT and compare match are set Rev. 3.00 Mar 21, 2006 page 748 of 814 REJ09B0302-0300...
Page 777 Appendix B Internal I/O Register SMR—Serial Mode Register H'B0 SCI0 C/A/GM STOP CKS1 CKS0 Initial value Read/Write Clock select 1 and 0 Bit 1 Bit 0 CKS1 CKS0 Clock Source φ clock φ/4 clock Multiprocessor mode φ/16 clock 0 Multiprocessor function disabled φ/64 clock 1 Multiprocessor format selected Stop bit length...
Page 778 Appendix B Internal I/O Register BRR—Bit Rate Register H'B1 SCI0 Initial value Read/Write Serial communication bit rate setting Rev. 3.00 Mar 21, 2006 page 750 of 814 REJ09B0302-0300...
Page 779 Appendix B Internal I/O Register SCR—Serial Control Register H'B2 SCI0 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock enable 1 and 0 Bit 1 Bit 0 CKE1 CKE0 Clock Selection and Output Asynchronous mode Internal clock, SCK pin available for generic I/O Synchronous mode Internal clock, SCK pin used for serial clock output Asynchronous mode...
Page 780 Appendix B Internal I/O Register TDR—Transmit Data Register H'B3 SCI0 Initial value Read/Write Serial transmit data Rev. 3.00 Mar 21, 2006 page 752 of 814 REJ09B0302-0300...
Page 781 Appendix B Internal I/O Register SSR—Serial Status Register H'B4 SCI0 TDRE RDRF ORER FER/ERS TEND MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit Multiprocessor bit transfer Multiprocessor bit value in Multiprocessor bit value in receive data is 0 transmit data is 0 Multiprocessor bit value in Multiprocessor bit value in...
Page 782 Appendix B Internal I/O Register RDR—Receive Data Register H'B5 SCI0 Initial value Read/Write Serial receive data SCMR—Smart Card Mode Register H'B6 SCI0 — — — — SDIR SINV — SMIF Initial value Read/Write — — — — — Smart card interface mode select 0 Smart card interface function is disabled (Initial value) 1 Smart card interface function is enabled...
Page 783 Appendix B Internal I/O Register SMR—Serial Mode Register H'B8 SCI1 STOP CKS1 CKS0 Initial value Read/Write Note: Bit functions are the same as for SCI0. BRR—Bit Rate Register H'B9 SCI1 Initial value Read/Write Note: Bit functions are the same as for SCI0. SCR—Serial Control Register H'BA SCI1...
Page 784 Appendix B Internal I/O Register TDR—Transmit Data Register H'BB SCI1 Initial value Read/Write Note: Bit functions are the same as for SCI0. SSR—Serial Status Register H'BC SCI1 TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Notes: Bit functions are the same as for SCI0.
Page 785 Appendix B Internal I/O Register P1DDR—Port 1 Data Direction Register H'C0 Port 1 P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR Initial value Modes 1 to 4 Read/Write — — — — —...
Page 786 Appendix B Internal I/O Register P2DR—Port 2 Data Register H'C3 Port 2 Initial value Read/Write Data for port 2 pins P3DDR—Port 3 Data Direction Register H'C4 Port 3 P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR Initial value...
Page 787 Appendix B Internal I/O Register P3DR—Port 3 Data Register H'C6 Port 3 Initial value Read/Write Data for port 3 pins P4DR—Port 4 Data Register H'C7 Port 4 Initial value Read/Write Data for port 4 pins P5DDR—Port 5 Data Direction Register H'C8 Port 5 —...
Page 788 Appendix B Internal I/O Register P6DDR—Port 6 Data Direction Register H'C9 Port 6 — P6 DDR P6 DDR P6 DDR P6 DDR P6 DDR P6 DDR P6 DDR Initial value Read/Write — Port 6 input/output select 0 Generic input pin 1 Generic output pin P5DR—Port 5 Data Register H'CA...
Page 789 Appendix B Internal I/O Register P8DDR—Port 8 Data Direction Register H'CD Port 8 — — — P8 DDR P8 DDR P8 DDR P8 DDR P8 DDR Initial value Modes 1 to 4 Read/Write — — — Initial value Modes 5 to 7 Read/Write —...
Page 790 Appendix B Internal I/O Register P9DDR—Port 9 Data Direction Register H'D0 Port 9 — — P9 DDR P9 DDR P9 DDR P9 DDR P9 DDR P9 DDR Initial value Read/Write — — Port 9 input/output select 0 Generic input pin 1 Generic output pin PADDR—Port A Data Direction Register H'D1...
Page 791 Appendix B Internal I/O Register PADR—Port A Data Register H'D3 Port A Initial value Read/Write Data for port A pins PBDDR—Port B Data Direction Register H'D4 Port B PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR Initial value...
Page 792 Appendix B Internal I/O Register P2PCR—Port 2 Input Pull-Up MOS Control Register H'D8 Port 2 P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR Initial value Read/Write Port 2 input pull-up MOS control 7 to 0 0 Input pull-up transistor is off 1 Input pull-up transistor is on Note: Valid when the corresponding P2DDR bit is cleared to 0 (designating generic input).
Page 793 Appendix B Internal I/O Register P5PCR—Port 5 Input Pull-Up MOS Control Register H'DB Port 5 — — — — P5 PCR P5 PCR P5 PCR P5 PCR Initial value Read/Write — — — — Port 5 input pull-up MOS control 3 to 0 0 Input pull-up transistor is off 1 Input pull-up transistor is on Note: Valid when the corresponding P5DDR bit is cleared to 0 (designating generic input).
Page 794 Appendix B Internal I/O Register DACR—D/A Control Register H'DE DAOE1 DAOE0 — — — — — Initial value Read/Write — — — — — D/A enable Bit 7 Bit 6 Bit 5 DAOE1 DAOE0 Description — D/A conversion is disabled in channels 0 and 1 D/A conversion is enabled in channel 0 D/A conversion is disabled in channel 1 D/A conversion is enabled in channels 0 and 1...
Page 795 Appendix B Internal I/O Register ADDRB H/L—A/D Data Register B H/L H'E2, H'E3 — — — — — — Initial value Read/Write ADDRBH ADDRBL A/D conversion data 10-bit data giving an A/D conversion result ADDRC H/L—A/D Data Register C H/L H'E4, H'E5 —...
Page 796 Appendix B Internal I/O Register ADCSR—A/D Control/Status Register H'E8 ADIE ADST SCAN Initial value Read/Write R/(W) Clock select 0 Conversion time = 266 states (maximum) 1 Conversion time = 134 states (maximum) Channel select 2 to 0 Group Channel Selection Selection Description Single Mode...
Page 797 Appendix B Internal I/O Register ADCR—A/D Control Register H'E9 TRGE — — — — — — — Initial value Read/Write — — — — — — —* Trigger enable 0 A/D conversion cannot be externally triggered 1 A/D conversion starts at the fall of the external trigger signal ( ADTRG Note: * Bit 0 must not be set to 1;...
Page 798 Appendix B Internal I/O Register WCR—Wait Control Register H'EE Bus controller — — — — WMS1 WMS0 Initial value Read/Write — — — — Wait mode select 1 and 0 Wait count 1 and 0 Bit 3 Bit 2 Bit 1 Bit 0 WMS1 WMS0...
Page 799 Appendix B Internal I/O Register MDCR—Mode Control Register H'F1 System control — — — — — MDS2 MDS1 MDS0 Initial value — — — Read/Write — — — — — Mode select 2 to 0 Bit 2 Bit 1 Bit 0 Operating mode —...
Page 800 Appendix B Internal I/O Register SYSCR—System Control Register H'F2 System control SSBY STS2 STS1 STS0 NMIEG — RAME Initial value Read/Write — RAM enable 0 On-chip RAM is disabled 1 On-chip RAM is enabled NMI edge select 0 An interrupt is requested at the falling edge of NMI 1 An interrupt is requested at the rising edge of NMI User bit enable 0 CCR bit 6 (UI) is used as an interrupt mask bit...
Page 801 Appendix B Internal I/O Register BRCR—Bus Release Control Register H'F3 Bus controller A23E A22E A21E — — — — BRLE Modes Initial value 1, 2, Read/Write — — — — — — — 5, 7 Initial value Modes 3, 4, 6 Read/Write —...
Page 802 Appendix B Internal I/O Register IER—IRQ Enable Register H'F5 Interrupt controller — — IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) IRQ to IRQ enable 0 IRQ to IRQ interrupts are disabled 1 IRQ to IRQ interrupts are enabled ISR—IRQ Status Register H'F6...
Page 803 Appendix B Internal I/O Register IPRA—Interrupt Priority Register A H'F8 Interrupt controller IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 Initial value Read/Write Priority level A7 to A0 0 Priority level 0 (low priority) 1 Priority level 1 (high priority) •...
Page 804: Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams Port 1 Block Diagram Software standby Mode 7 Hardware standby External bus released Reset Mode 1 to 4 P1 DDR WP1D Reset Mode 7 P1 DR Mode 1 to 6 Legend: WP1D: Write to P1DDR...
Page 805: Port 2 Block Diagram
Appendix C I/O Port Block Diagrams Port 2 Block Diagram Reset P2 PCR Software standby Mode 7 RP2P WP2P Hardware standby Reset External bus Mode 1 to 4 released P2 DDR WP2D Reset Mode 7 P2 DR Mode 1 to 6 Legend: WP2P: Write to P2PCR...
Page 806: Port 3 Block Diagram
Appendix C I/O Port Block Diagrams Port 3 Block Diagram Reset Hardware standby External Mode 7 bus released P3 DDR Write to external address WP3D Reset Mode 7 P3 DR Mode 1 to 6 Read external address Legend: WP3D: Write to P3DDR WP3: Write to port 3 RP3:...
Page 807: Port 4 Block Diagram
Appendix C I/O Port Block Diagrams Port 4 Block Diagram 8-bit bus 16-bit bus mode mode Mode Mode 7 1 to 6 Reset P4 PCR RP4P WP4P Reset Write to external P4 DDR address WP4D Reset P4 DR Read external address Legend: WP4P:...
Page 808: Port 5 Block Diagram
Appendix C I/O Port Block Diagrams Port 5 Block Diagram Reset P5 PCR Software standby Mode 7 RP5P WP5P Hardware standby External bus Mode 1 to 4 released Reset P5 DDR WP5D Reset Mode 7 P5 DR Mode 1 to 6 Legend: WP5P: Write to P5PCR...
Page 809: Port 6 Block Diagrams
Appendix C I/O Port Block Diagrams Port 6 Block Diagrams Reset P6 DDR Bus controller WP6D WAIT Mode 7 input Reset enable P6 DR Bus controller WAIT Legend: input WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C.6 (a) Port 6 Block Diagram (Pin P6 Rev.
Page 810 Appendix C I/O Port Block Diagrams Reset controller P6 DDR Mode 7 WP6D Bus release enable Reset P6 DR BREQ input Legend: WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C.6 (b) Port 6 Block Diagram (Pin P6 Rev.
Page 811 Appendix C I/O Port Block Diagrams Reset P6 DDR WP6D Reset P6 DR Bus controller Mode 7 Bus release enable BACK output Legend: WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C.6 (c) Port 6 Block Diagram (Pin P6 Rev.
Page 812 Appendix C I/O Port Block Diagrams Software standby Mode 7 Hardware standby External bus released Reset Mode 7 P6 DDR WP6D Reset Mode 7 P6 DR Mode 1 to 6 AS output RD output HWR output LWR output Legend: WP6D: Write to P6DDR WP6: Write to port 6...
Page 813: Port 7 Block Diagrams
Appendix C I/O Port Block Diagrams Port 7 Block Diagrams A/D converter Input enable Analog input Legend: RP7: Read port 7 Note: n = 0 to 5 Figure C.7 (a) Port 7 Block Diagram (Pins P7 to P7 A/D converter Input enable Analog input D/A converter...
Page 814: Port 8 Block Diagrams
Appendix C I/O Port Block Diagrams Port 8 Block Diagrams Reset P8 DDR WP8D Reset Refresh P8 DR controller Mode 7 Output enable RFSH output Interrupt controller input Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.8 (a) Port 8 Block Diagram (Pin P8 Rev.
Page 815 Appendix C I/O Port Block Diagrams Reset Bus controller P8 DDR Reset output Mode 7 P8 DR Mode 1 to 6 Interrupt controller input Legend: WP8D Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Note: n = 1 to 3 Figure C.8 (b) Port 8 Block Diagram (Pins P8 to P8 Rev.
Page 816 Appendix C I/O Port Block Diagrams Reset Mode 1 to 4 Bus controller P8 DDR WP8D output Reset Mode 6/7 P8 DR Mode 1 to 5 Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.8 (c) Port 8 Block Diagram (Pin P8 Rev.
Page 817: Port 9 Block Diagrams
Appendix C I/O Port Block Diagrams Port 9 Block Diagrams Reset P9 DDR WP9D Reset P9 DR SCI0 Output enable Serial transmit data Guard time Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.9 (a) Port 9 Block Diagram (Pin P9 Rev.
Page 818 Appendix C I/O Port Block Diagrams Reset P9 DDR WP9D Reset P9 DR SCI1 Output enable Serial transmit data Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.9 (b) Port 9 Block Diagram (Pin P9 Rev.
Page 819 Appendix C I/O Port Block Diagrams Reset P9 DDR WP9D Input enable Reset P9 DR Serial receive data Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Note: n = 2 or 3 Figure C.9 (c) Port 9 Block Diagram (Pins P9 , P9 Rev.
Page 820 Appendix C I/O Port Block Diagrams Reset P9 DDR WP9D Clock input Reset enable P9 DR Clock output enable Clock output Clock input Legend: Interrupt WP9D: Write to P9DDR controller WP9: Write to port 9 RP9: Read port 9 input Note: n = 4 or 5 Figure C.9 (d) Port 9 Block Diagram (Pins P9 , P9...
Page 821: Port A Block Diagrams
Appendix C I/O Port Block Diagrams C.10 Port A Block Diagrams Reset PA DDR WPAD Reset output enable PA DR Next data Output trigger DMA controller Output enable Transfer end output Counter clock input Legend: WPAD: Write to PADDR WPA: Write to port A RPA: Read port A...
Page 822 Appendix C I/O Port Block Diagrams Reset PA DDR WPAD Reset output enable PA DR Next data Output trigger Output enable Compare match output Input capture Counter clock Legend: input WPAD: Write to PADDR WPA: Write to port A RPA: Read port A Note: n = 2 or 3 Figure C.10 (b) Port A Block Diagram (Pins PA...
Page 823 Appendix C I/O Port Block Diagrams Software standby External bus released Hardware standby Bus controller Chip select enable Address output Reset enable output WPAD Reset TPC output enable Next data Output trigger Output enable Compare match output Input capture Legend: WPAD: Write to PADDR WPA:...
Page 824 Appendix C I/O Port Block Diagrams Software standby External bus released Hardware standby Bus controller Address output Reset enable WPAD Reset TPC output enable Next data Output trigger Output enable Compare match output Input capture Legend: WPAD: Write to PADDR WPA: Write to port A RPA:...
Page 825: Port B Block Diagrams
Appendix C I/O Port Block Diagrams C.11 Port B Block Diagrams Reset PB DDR WPBD Reset TPC output enable PB DR Next data Output trigger Output enable Compare match output Input capture Legend: WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Note: n = 0 to 3...
Page 826 Appendix C I/O Port Block Diagrams Reset PB DDR WPBD Reset TPC output enable PB DR Next data Output trigger Output enable Compare match output Legend: WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Note: n = 4 or 5 Figure C.11 (b) Port B Block Diagram (Pins PB , PB Rev.
Page 827 Appendix C I/O Port Block Diagrams Reset PB DDR WPBD Reset output enable PB DR Next data Output trigger Bus controller output Chip select enable DMAC Legend: DREQ0 WPBD: Write to PBDDR input WPB: Write to port B RPB: Read port B Figure C.11 (c) Port B Block Diagram (Pin PB Rev.
Page 828 Appendix C I/O Port Block Diagrams Reset PB DDR WPBD Reset output enable PB DR Next data Output trigger DMAC DREQ1 input A/D converter ADTRG Legend: input WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C.11 (d) Port B Block Diagram (Pin PB Rev.
Page 829: Appendix D Pin States
Appendix D Pin States Appendix D Pin States Port States in Each Mode Table D.1 Port States Hardware Software Bus- Program Standby Standby Released Execution, Pin Name Mode Reset Mode Mode Mode Sleep Mode φ — Clock output T Clock output Clock output to P1 1 to 4 to A...
Page 830 Appendix D Pin States Hardware Software Bus- Program Standby Standby Released Execution, Pin Name Mode Reset Mode Mode Mode Sleep Mode 1 to 6 keep keep I/O port WAIT keep — I/O port 1 to 6 keep I/O port BREQ (BRLE = 0) (BRLE = 1) keep...
Page 831 Appendix D Pin States Hardware Software Bus- Program Standby Standby Released Execution, Pin Name Mode Reset Mode Mode Mode Sleep Mode keep * to PA 1 to 7 keep I/O port to CS to PA 3, 4, 6 (CS output) (CS output) (CS output) T (address...
Page 832: Pin States At Reset
Appendix D Pin States Pin States at Reset State: Figure D.1 is a timing diagram for the case in which RES goes low during the Reset in T state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state.
Page 833 Appendix D Pin States State: Figure D.2 is a timing diagram for the case in which RES goes low during the Reset in T state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state.
Page 834 Appendix D Pin States State: Figure D.3 is a timing diagram for the case in which RES goes low during the Reset in T state of an external three-state space access cycle. As soon as RES goes low, all ports are initialized to the input state.
Page 835: Appendix E Timing Of Transition To And Recovery From Hardware Standby Mode
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown below.
Page 836: Appendix F Product Code Lineup
Appendix F Product Code Lineup Appendix F Product Code Lineup Table F.1 H8/3052B F-ZTAT Product Code Lineup Package Product Type Product Code Mark Code (Package Code) H8/3052 F-ZTAT 5 V version HD64F3052BTE HD64F3052BTE 100-pin TQFP (TFP-100B) B mask version HD64F3052BF HD64F3052BF 100-pin QFP (FP-100B) Rev.
Page 837: Appendix G Package Dimensions
Appendix G Package Dimensions Appendix G Package Dimensions Figure G.1 shows the FP-100B package dimensions of the H8/3052B F-ZTAT. Figure G.2 shows the TFP-100B package dimensions. JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-QFP100-14x14-0.50 PRQP0100KA-A FP-100B/FP-100BV 1.2g NOTE) 1. DIMENSIONS"*1"AND"*2"...
Page 838 Appendix G Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-TQFP100-14x14-0.50 PTQP0100KA-A TFP-100B/TFP-100BV 0.5g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. Dimension in Millimeters Terminal cross section Reference Symbol 1.00 15.8 16.0...
Page 839: Appendix H Differences From H8/3048F-Ztat
Appendix H Differences from H8/3048F-ZTAT Appendix H Differences from H8/3048F-ZTAT Table H.1 Differences between H8/3052B F-ZTAT and H8/3048F-ZTAT Item H8/3048F-ZTAT H8/3052B F-ZTAT Pin 1 → V Pin specifications 5 V Operation Pin 1 → V Connected to V , with external connection of 0.1 µF capacitor Pin 10 →...
Page 840 Appendix H Differences from H8/3048F-ZTAT Item H8/3048F-ZTAT H8/3052B F-ZTAT FLMCR FLMCR (H'FF40) FLMCR1 (H'FF40)   FWE SWE1 ESU1 PSU1 EV1 PV1 FLMCR2 (H'FF41) FLER SWE2 ESU2 PSU2 EV2 PV2 EBR1 (H'FF42) EBR1 (H'FF42) EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 EBR2 (H'FF43) EBR2 (H'FF43) SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0...
Page 841 Appendix H Differences from H8/3048F-ZTAT Item H8/3048F-ZTAT H8/3052B F-ZTAT RAM emulation block On-chip RAM Flash memory On-chip RAM Flash memory configuration H'EF10 H'00000 H'00000 H'DF10 H'01000 H'F000 H'F000 H'02000 H'F1FF H'03000 H'04000 H'1FFFF H'05000 H'1F000 H'06000 H'EFFF H'1F200 H'07000 H'1F400 H'08000 H'1F600 H'1F800...
Page 842 Appendix H Differences from H8/3048F-ZTAT Rev. 3.00 Mar 21, 2006 page 814 of 814 REJ09B0302-0300...
Page 843 Publication Date: 1st Edition, January 2000 Rev.3.00, March 21, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. ©2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 844 Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Page 845 H8/3052B F-ZTAT™ Hardware Manual...

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F-ztat h8/300h series F-ztat h8/3052b series F-ztat hd64f3052bte F-ztat hd64f3052bf