Page 1 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
Page 3 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8/3857 Group, H8/3857 F-ZTAT™, H8/3854 Group, H8/3854 F-ZTAT™ Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Series H8/3857 HD6433857, HCD6433857 H8/3856...
Page 4 Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures.
Page 5 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
Page 6 Rev.3.00 Jul. 19, 2007 page iv of xxiv REJ09B0397-0300...
Page 7 H8/3857 and H8/3854 are also available in an F-ZTAT™* version which allows programs to be written after the chip is mounted on a board. Note: * F-ZTAT (Flexible Zero Turn-Around Time) is a trademark of Renesas Technology Corp.
Page 8 List of Functions Group H8/3857 Group H8/3854 Group F-ZTAT F-ZTAT Version Mask ROM Version Version Mask ROM Version Part No. H8/3857F H8/3857 H8/3856 H8/3855 H8/3854F H8/3854 H8/3853 H8/3852 ROM size (kbytes) RAM size (kbytes) I/O ports Input/output ports Input ports Interrupts External interrupts...
Page 9 Revision (See Manual for Details) ⎯ • Company name and brand names amended (Before) Hitachi, Ltd. → (After) Renesas Technology Corp. • Designation for categories amended (Before) H8/3857 Series → (After) H8/3857 Group (Before) H8/3854 Series → (After) H8/3854 Group 2.2.1 General...
Page 10 Item Page Revision (See Manual for Details) 8.3 Port 2 Description amended The UD function multiplexed with the P2 pin is provided only in the H8/3857 Group, and not in the H8/3854 Group. 11.3 Operation Figure amended Figure 11.2 PWM T = t ..
Page 11 Item Page Revision (See Manual for Details) 15.2.3 AC Table note amended Characteristics Notes: 3. The guaranteed temperature as an electrical Table15.4 Control characteristic for die type products is 75°C. Signal Timing of H8/3855, H8/3856, and H8/3857 Table15.5 Serial Table note amended Interface (SCI1) Timing Note: * The guaranteed temperature as an electrical of H8/3855, H8/3856,...
Page 12 Item Page Revision (See Manual for Details) 16.2.1 Power Supply Figure amended Voltage and Operating 10.0 32.768 Range (1) Power Supply Voltage vs. Oscillator Frequency Range 2.7* 2.7* • Active mode (high speed) • Active mode (medium speed) • Sleep mode Note added Note: * The minimum V level of the H8/3854F is 3.0 V.
Page 13 Item Page Revision (See Manual for Details) 16.2.2 DC Table condition amended Characteristics = 2.7 V to 5.5 V of the mask ROM version of H8/3852, Table 16.2 DC H8/3853, and H8/3854, V = 3.0 V to 5.5 V of H8/3854F, Characteristics of = 0.0 V, T = –20°C to +75°C*...
Page 14 Item Page Revision (See Manual for Details) 16.2.3 AC Description amended Characteristics Table 16.4 shows the control signal timing, and table 16.5 shows the serial interface timing, of the H8/3852, H8/3853, and H8/3854. Table 16.4 Control Table condition amended Signal Timing of = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3852, H8/3853, and H8/3853, and H8/3854, V...
Page 15 Item Page Revision (See Manual for Details) B.2 Register Bit table amended Descriptions P4 /IRQ pin function switch PMR2—Port mode 0 Functions as P4 input pin register 2 1 Functions as IRQ input pin Rev.3.00 Jul. 19, 2007 Page xiii of xxiv REJ09B0397-0300...
Page 16 All trademarks and registered trademarks are the property of their respective owners. Rev.3.00 Jul. 19, 2007 Page xiv of xxiv REJ09B0397-0300...
Page 17: Table Of Contents
Contents Section 1 Overview ......................Overview........................... Internal Block Diagram..................... Pin Arrangement and Functions..................1.3.1 Pin Arrangement ....................1.3.2 Pin Functions ....................... 20 Section 2 CPU ........................27 Overview........................... 27 2.1.1 Features........................ 27 2.1.2 Address Space...................... 28 2.1.3 Register Configuration..................28 Register Descriptions ......................
Page 18 2.7.3 Program Halt State....................59 2.7.4 Exception-Handling State ..................59 Memory Map ........................60 2.8.1 Memory Map ....................... 60 Application Notes ......................62 2.9.1 Notes on Data Access ..................62 2.9.2 Notes on Bit Manipulation................... 64 2.9.3 Notes on Use of the EEPMOV Instruction ............70 Section 3 Exception Handling ..................
Page 19 5.2.2 Clearing Sleep Mode.................... 107 Standby Mode ........................108 5.3.1 Transition to Standby Mode................. 108 5.3.2 Clearing Standby Mode ..................108 5.3.3 Oscillator Settling Time after Standby Mode Is Cleared ........108 5.3.4 Transition to Standby Mode and Port Pin States..........109 5.3.5 Notes on External Input Signal Changes before/after Standby Mode....
Page 20 6.3.3 Erase Block Register (EBR) ................130 6.3.4 Mode Control Register (MDCR) ................. 131 6.3.5 System Control Register 3 (SYSCR3) ..............131 On-Board Programming Modes..................132 6.4.1 Boot Mode ......................133 6.4.2 User Program Mode..................... 138 Flash Memory Programming/Erasing ................140 6.5.1 Program Mode .....................
Page 21 8.2.4 Pin States......................181 8.2.5 MOS Input Pull-Up....................182 Port 2..........................182 8.3.1 Overview......................182 8.3.2 Register Configuration and Description............... 183 8.3.3 Pin Functions ....................... 187 8.3.4 Pin States......................188 Port 3 (H8/3857 Group Only) ................... 189 8.4.1 Overview......................189 8.4.2 Register Configuration and Description...............
Page 22 Timer A..........................210 9.2.1 Overview......................210 9.2.2 Register Descriptions ................... 212 9.2.3 Timer Operation....................214 9.2.4 Timer A Operation States ..................215 Timer B ..........................215 9.3.1 Overview......................215 9.3.2 Register Descriptions ................... 217 9.3.3 Timer Operation....................219 9.3.4 Timer B Operation States..................220 Timer C (H8/3857 Group Only) ..................
Page 23 10.3.5 Operation in Synchronous Mode ................. 292 10.3.6 Multiprocessor Communication Function............299 10.3.7 Interrupts......................305 10.3.8 Application Notes ....................306 Section 11 14-Bit PWM (H8/3857 Group Only) ............311 11.1 Overview........................... 311 11.1.1 Features........................ 311 11.1.2 Block Diagram ..................... 311 11.1.3 Pin Configuration....................
Page 24 13.2.1 Index Register (IR) ....................330 13.2.2 Control Register 1 (LR0) ..................331 13.2.3 Control Register 2 (LR1) ..................333 13.2.4 Address Register (LR2) ..................335 13.2.5 Frame Frequency Setting Register (LR3) ............336 13.2.6 Display Data Register (LR4)................338 13.2.7 Display Start Line Register (LR5) ...............
Page 25 14.2.6 Display Data Register (LR4)................383 14.3 Operation........................... 384 14.3.1 System Overview ....................384 14.3.2 CPU Interface....................... 385 14.3.3 LCD Drive Pin Functions ..................388 14.3.4 Display Memory Configuration and Display ............389 14.3.5 Display Data Output .................... 390 14.3.6 Register and Display Memory Access ..............391 14.3.7 Module Standby Mode..................
Page 26 16.4 Output Load Circuit ......................438 16.5 Usage Note........................439 Appendix A CPU Instruction Set ..................441 Instructions........................441 Operation Code Map......................450 Number of Execution States ..................... 452 Appendix B Internal I/O Registers ................. 459 Register Addresses......................459 B.1.1 H8/3857 Group Addresses...................
Page 27: Section 1 Overview
1. Overview Section 1 Overview Overview The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip. Within the H8/300L Series, the H8/3857 Group and H8/3854 Group feature on-chip liquid crystal display (LCD) controllers.
Page 28 1. Overview Table 1.1 Features Item Description High-speed H8/300L CPU • General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) • Operating speed ⎯ Max. operating speed: 5 MHz ⎯ Add/subtract: 0.4 μs (operating at 5 MHz) ⎯...
Page 29 1. Overview Item Description Memory H8/3857 Group • H8/3855: 40-kbyte ROM, 2-kbyte RAM • H8/3856: 48-kbyte ROM, 2-kbyte RAM • H8/3857: 60-kbyte ROM, 2-kbyte RAM • H8/3857F: 60-kbyte ROM, 2-kbyte RAM H8/3854 Group • H8/3852: 16-kbyte ROM, 1-kbyte RAM • H8/3853: 24-kbyte ROM, 1-kbyte RAM •...
Page 30 1. Overview Item Description Serial communication H8/3857 Group: Two channels on chip interface • SCI1: synchronous serial interface Choice of 8-bit or 16-bit data transfer • SCI3: 8-bit synchronous or asynchronous serial interface Built-in function for multiprocessor communication H8/3854 Group: One channel on chip •...
Page 31 1. Overview Item Description Product lineup H8/3857 Group Part No. Mask ROM F-ZTAT ROM/RAM Version Version Package Size ⎯ HD6433855FQ 144-pin QFP (FP-144H) ROM: 40 kbytes ⎯ HD6433855TG 144-pin TQFP (TFP-144) RAM: 2 kbytes ⎯ HCD6433855 ⎯ HD6433856FQ 144-pin QFP (FP-144H) ROM: 48 kbytes ⎯...
Page 32: Internal Block Diagram
1. Overview Internal Block Diagram Figures 1.1 and 1.2 show internal block diagrams of the H8/3857 Group and H8/3854 Group. (8-bit) Data bus (lower) /TMOW /TMOFL /TMOFH FLASH/ /PWM MASK /IRQ /TMIB /IRQ /TMIC /IRQ /TMIF /WKP /IRQ /ADTRG /WKP Timer A SCI1 /WKP...
Page 33 1. Overview (8-bit) Data bus (lower) /TMOW /TMOFL FLASH/ /TMOFH MASK /IRQ /TMIB /IRQ /TMIF /WKP /IRQ /ADTRG /WKP Timer A /WKP /WKP /WKP /WKP /WKP Timer B SCI3 /WKP Timer F /SCK /RXD /TXD /IRQ Internal Port 9 Port A I/O port V1OUT V2OUT...
Page 34: Pin Arrangement And Functions
1. Overview Pin Arrangement and Functions 1.3.1 Pin Arrangement The pin arrangements of the H8/3857 Group and H8/3854 Group are shown in figures 1.3 and 1.4. The HCD64F3857 pad layout is shown in figure 1.5, and the pad coordinates in table 1.2; the HCD6433855, HCD6433856, and HCD6433857 pad layout is shown in figure 1.6, and the pad coordinates in table 1.3;...
Page 35 1. Overview SEG31 SEG5 SEG32 SEG4 SEG33 SEG3 SEG34 SEG2 SEG35 SEG1 SEG36 COM16 SEG37 COM15 SEG38 COM14 SEG39 COM13 H8/3854 SEG40 COM12 V5OUT COM11 V4OUT COM10 (Top view) V3OUT COM9 V2OUT COM8 FP-100B V1OUT COM7 TFP-100G /IRQ /TMIF COM6 /IRQ /TMIB COM5...
Page 36 1. Overview 128 126 127 125 Model (0, 0) Model: HD64F3857 Chip size: 7.08 mm × 7.31 mm Figure 1.5 Pad Layout of HCD64F3857 (F-ZTAT Version) (Top View) Rev.3.00 Jul. 19, 2007 page 10 of 532 REJ09B0397-0300...
Page 37 1. Overview Table 1.2 HCD64F3857 Pad Coordinates Coordinates* Coordinates* Coordinates* No. Pad Name X (μm) Y (μm) No. Pad Name X (μm) Y (μm) No. Pad Name X (μm) Y (μm) −3348 −3348 −2264 −3463 /WKP 2928 TEST SEG15 2032 −3348 −3348 −2404...
Page 38 1. Overview Coordinates* Coordinates* Coordinates* No. Pad Name X (μm) Y (μm) No. Pad Name X (μm) Y (μm) No. Pad Name X (μm) Y (μm) −982 102 COM23/SEG50 3348 1731 117 V 1471 3463 132 P3 /SCK 3463 −1116 103 COM22/SEG51 3348 2063...
Page 39 1. Overview 128 126 127 125 Model (0, 0) Model: HD643385rccc r: Number denoting to ROM size 7: 60-kbyte version 6: 48-kbyte version 5: 40-kbyte version ccc: ROM code Chip size: 6.21 mm × 6.21 mm Figure 1.6 Pad Layout of HCD6433855, HCD6433856, and HCD6433857 (Mask ROM Version) (Top View) Rev.3.00 Jul.
Page 40 1. Overview Table 1.3 HCD6433855, HCD6433856, and HCD6433857 Pad Coordinates Coordinates* Coordinates* Coordinates* No. Pad Name X (μm) Y (μm) No. Pad Name X (μm) Y (μm) No. Pad Name X (μm) Y (μm) −2913 −2913 −2534 −2913 /WKP 2515 FWE* SEG19 2305...
Page 41 1. Overview Coordinates* Coordinates* Coordinates* No. Pad Name X (μm) Y (μm) No. Pad Name X (μm) Y (μm) No. Pad Name X (μm) Y (μm) −715 106 COM19/SEG54 2913 2125 119 C 2913 132 P3 /SCK 2913 −845 107 COM18/SEG55 2913 2305 120 C...
Page 42 1. Overview 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 Model (0, 0) 19-1 19-2 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Model: HD64F3854 Chip size: 6.34 mm ×...
Page 43 1. Overview Table 1.4 HCD64F3854 Pad Coordinates Coordinates* Coordinates* Coordinates* No. Pad Name X (μm) Y (μm) No. Pad Name X (μm) Y (μm) No. Pad Name X (μm) Y (μm) −2985 −1413 −2985 /WKP 2494 COM2 SEG21 2985 −2985 −1210 −2985 /WKP...
Page 44 1. Overview 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 Model (0, 0) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Model: HD643385rccc r: Number denoting to ROM size 4: 32-kbyte version...
Page 45 1. Overview Table 1.5 HCD6433852, HCD6433853, and HCD6433854 Pad Coordinates Coordinates* Coordinates* Coordinates* No. Pad Name X (μm) Y (μm) No. Pad Name X (μm) Y (μm) No. Pad Name X (μm) Y (μm) −2161 −390 −2161 /WKP 1738 COM6 SEG23 2161 −2161...
Page 46: Pin Functions
1. Overview 1.3.2 Pin Functions Table 1.6 outlines the pin functions of the H8/3857 Group. Table 1.6 Pin Functions H8/3857 Group H8/3854 Group Pin No. Pin No. FP-144H FP-100B Type Symbol TFP-144 Pad No. TFP-100G Pad No. Name and Functions Power Input Power supply: All V...
Page 47 1. Overview H8/3857 Group H8/3854 Group Pin No. Pin No. FP-144H FP-100B Type Symbol TFP-144 Pad No. TFP-100G Pad No. Name and Functions System Input Reset: When this pin is control driven low, the chip is reset Input Flash write enable: This pin enables or disables flash memory programming.
Page 48 1. Overview H8/3857 Group H8/3854 Group Pin No. Pin No. FP-144H FP-100B Type Symbol TFP-144 Pad No. TFP-100G Pad No. Name and Functions ⎯ ⎯ Timer Input Timer C up/down select pins (H8/3857 Group only): This pin selects whether the timer C counter is used for up- or down-counting.
Page 49 1. Overview H8/3857 Group H8/3854 Group Pin No. Pin No. FP-144H FP-100B Type Symbol TFP-144 Pad No. TFP-100G Pad No. Name and Functions I/O ports P2 to P2 9 to 16 9 to 16 8 to 15 8 to 15 Port 2: This is an 8-bit I/O port.
Page 50 1. Overview H8/3857 Group H8/3854 Group Pin No. Pin No. FP-144H FP-100B Type Symbol TFP-144 Pad No. TFP-100G Pad No. Name and Functions Serial Output SCI3 send data output: commu- This is the SCI3 data output nication interface SCI3 clock I/O : This is the (SCI) SCI3 clock I/O pin to AN...
Page 51 1. Overview H8/3857 Group H8/3854 Group Pin No. Pin No. FP-144H FP-100B Type Symbol TFP-144 Pad No. TFP-100G Pad No. Name and Functions ⎯ ⎯ ⎯ C1+, C1–, 121 to 118 121 to 118 LCD step-up circuit controller C2+, C2– capacitance connection pins (H8/3857 Group only): These pins connect...
Page 52 1. Overview H8/3857 Group H8/3854 Group Pin No. Pin No. FP-144H FP-100B Type Symbol TFP-144 Pad No. TFP-100G Pad No. Name and Functions ⎯ ⎯ H8/3854 V1OUT to 90 to 86 90 to 86 LCD drive power supply Group V5OUT level (H8/3854 Group): When the LPS1 and LPS0 power...
Page 53: Section 2 Cpu
2. CPU Section 2 CPU Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise, optimized instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below. •...
Page 54: Address Space
2. CPU 2.1.2 Address Space The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and data. See section 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration Figure 2.1 shows the register structure of the H8/300L CPU. There are two groups of registers: the general registers and control registers.
Page 55: Register Descriptions
2. CPU Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers.
Page 56 2. CPU ORC, and XORC instructions). The N, Z, V, and C flags are used as branching conditions for conditional branching (Bcc) instructions. Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1 automatically at the start of exception handling.
Page 57: Initial Register Values
2. CPU 2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not initialized.
Page 58: Data Formats In General Registers
2. CPU 2.3.1 Data Formats in General Registers The general register data formats are shown in figure 2.3. Data Type Register No. Data Format 1-bit data don't care 1-bit data don't care Byte data don't care Byte data don't care Word data 4-bit BCD data Upper digit...
Page 59: Memory Data Formats
2. CPU 2.3.2 Memory Data Formats Figure 2.4 indicates the data formats in memory. For access by the H8/300L CPU, word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as 0.
Page 60: Addressing Modes
2. CPU Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a subset of these addressing modes. Table 2.1 Addressing Modes Address Modes Symbol Register direct Register indirect Register indirect with displacement @(d:16, Rn) Register indirect with post-increment @Rn+...
Page 61 2. CPU 4. Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn: • Register indirect with post-increment—@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of the operand.
Page 62: Effective Address Calculation
2. CPU 8. Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. The word located at this address contains the branch destination address. The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from H'0000 to H'00FF (0 to 255).
Page 63 2. CPU Table 2.2 Effective Address Calculation Addressing Mode and Effective Address Instruction Format Calculation Method Effective Address (EA) Register direct, Rn Operand is contents of registers indicated by rm/rn Register indirect, @Rn Contents (16 bits) of register indicated by rm Register indirect with displacement, @(d:16, Rn) Contents (16 bits) of...
Page 64 2. CPU Addressing Mode and Effective Address Instruction Format Calculation Method Effective Address (EA) Absolute address @aa:8 H'FF @aa:16 Immediate #xx:8 #xx:16 Operand is 1- or 2-byte immediate data Program-counter relative PC contents @(d:8, PC) Sign disp extension disp Rev.3.00 Jul. 19, 2007 page 38 of 532 REJ09B0397-0300...
Page 65 2. CPU Addressing Mode and Effective Address Instruction Format Calculation Method Effective Address (EA) Memory indirect, @@aa:8 H'00 Memory contents (16 bits) Legend: rm, rn: Register field Operation field disp: Displacement IMM: Immediate data abs: Absolute address Rev.3.00 Jul. 19, 2007 page 39 of 532 REJ09B0397-0300...
Page 66: Instruction Set
2. CPU Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3. Table 2.3 Instruction Set Function Instructions Number Data transfer MOV, PUSH* , POP* Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG Logic operations AND, OR, XOR, NOT...
Page 67 2. CPU Operation Notation General register (destination) General register (source) General register (EAd), <EAd> Destination operand (EAs), <EAs> Source operand Condition code register N (negative) flag of CCR Z (zero) flag of CCR V (overflow) flag of CCR C (carry) flag of CCR Program counter Stack pointer #IMM...
Page 68: Data Transfer Instructions
2. CPU 2.5.1 Data Transfer Instructions Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register.
Page 69 2. CPU Rm→Rn @Rm←→Rn @(d:16, Rm)←→Rn disp @Rm+→Rn, or Rn →@–Rm @aa:8←→Rn @aa:16←→Rn #xx:8→Rn #xx:16→Rn PUSH, POP → @SP+ Rn, or → @–SP Legend: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2.5 Data Transfer Instruction Codes Rev.3.00 Jul.
Page 70: Arithmetic Operations
2. CPU 2.5.2 Arithmetic Operations Table 2.5 describes the arithmetic instructions. Table 2.5 Arithmetic Instructions Instruction Size* Function Rd ± Rs → Rd, Rd + #IMM → Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register.
Page 71: Logic Operations
2. CPU 2.5.3 Logic Operations Table 2.6 describes the four instructions that perform logic operations. Table 2.6 Logic Operation Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data Rd ∨...
Page 72 2. CPU Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions. ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT MULXU, DIVXU ADD, ADDX, SUBX, CMP (#XX:8) AND, OR, XOR (Rm) AND, OR, XOR (#xx:8) SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR...
Page 73: Bit Manipulations
2. CPU 2.5.5 Bit Manipulations Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8 Bit-Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit to 1 in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 74 2. CPU Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR XORs the C flag with a specified bit in a general register or memory operand, and stores the result in the C flag. C ⊕ [~(<bit-No.> of <EAd>)] → C BIXOR XORs the C flag with the inverse of a specified bit in a general register or memory operand, and stores the result in the C flag.
Page 75 2. CPU BSET, BCLR, BNOT, BTST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: register direct (Rm) Operand: absolute (@aa:8) Bit No.:...
Page 76 2. CPU BIAND, BIOR, BIXOR, BILD, BIST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: absolute (@aa:8) Bit No.: immediate (#xx:3) Legend: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Codes (2)
Page 77: Branching Instructions
2. CPU 2.5.6 Branching Instructions Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9 Branching Instructions Instruction Size Function ⎯ Branches to the designated address if the specified condition is true. The branching conditions are given below. Mnemonic Description Condition...
Page 78 2. CPU disp JMP (@Rm) JMP (@aa:16) JMP (@@aa:8) disp JSR (@Rm) JSR (@aa:16) JSR (@@aa:8) Legend: Operation field Condition field Register field disp: Displacement abs: Absolute address Figure 2.8 Branching Instruction Codes Rev.3.00 Jul. 19, 2007 page 52 of 532 REJ09B0397-0300...
Page 79: System Control Instructions
2. CPU 2.5.7 System Control Instructions Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 System Control Instructions Instruction Size* Function ⎯ Returns from an exception-handling routine ⎯ SLEEP Causes a transition from active mode to a power-down mode. See section 5, Power-Down Modes, for details Rs →...
Page 80: Block Data Transfer Instruction
2. CPU RTE, SLEEP, NOP LDC, STC (Rn) ANDC, ORC, XORC, LDC (#xx:8) Legend: Operation field Register field IMM: Immediate data Figure 2.9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format. Table 2.11 Block Data Transfer Instruction Instruction Size...
Page 81: Basic Operational Timing
2. CPU Legend: Operation field Figure 2.10 Block Data Transfer Instruction Code Basic Operational Timing CPU operation is synchronized by a system clock (φ) or a subclock (φ ). For details on these clock signals see section 4, Clock Pulse Generators. The period from a rising edge of φ or φ the next rising edge is called one state.
Page 82: Access To On-Chip Peripheral Modules
2. CPU 2.6.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used.
Page 83: Cpu States
2. CPU Three-State Access to On-Chip Peripheral Modules Bus cycle state state state φ or φ Internal Address address bus Internal read signal Internal Read data data bus (read access) Internal write signal Internal data bus Write data (write access) Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access) CPU States 2.7.1...
Page 84 2. CPU CPU state Reset state The CPU is initialized. Program Active execution state (high speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock Active (medium speed) mode The CPU executes successive program instructions at reduced speed, synchronized by the system clock Subactive mode...
Page 85: Program Execution State
2. CPU Reset cleared Reset state Exception-handling state Reset occurs Reset Interrupt occurs source Reset Interrupt Exception- occurs source handling complete Program halt state Program execution state SLEEP instruction executed Figure 2.15 State Transitions 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one subactive mode.
Page 86: Memory Map
2. CPU Memory Map 2.8.1 Memory Map The memory maps of the H8/3857 Group and H8/3854 Group are shown in figures 2.16 (a) and (b). H8/3855 H8/3856 H8/3857 H8/3857F H'0000 Interrupt vector (42 bytes) H'0029 H'002A kbytes kbytes kbytes kbytes On-chip ROM H'9FFF H'BFFF...
Page 87 2. CPU H8/3852 H8/3853 H8/3854 H8/3854F H'0000 Interrupt vector (42 bytes) H'0029 H'002A kbytes kbytes kbytes kbytes On-chip ROM H'3FFF H'5FFF H'7FFF H'EDFF Not used H'F77F H'F780 H8/3854F On-chip RAM H8/3852 2,048 bytes H'FB7F H8/3853 H'FB80 H8/3854 1,024 bytes H'FF7F H'FF80 Internal I/O registers (128 bytes)
Page 88: Application Notes
2. CPU Application Notes 2.9.1 Notes on Data Access Access to Empty Areas: The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur.
Page 89 2. CPU Access States Word Byte H'0000 Interrupt vector area (42 bytes) H'0029 H'002A 60 kbytes On-chip ROM H'EDFF Not used — — — H'F780 On-chip RAM 2048 bytes H'FF7F H'FF80 Internal I/O registers (128 bytes) H'FFA8 H'FFAD H'FFFF Notes: The above example is a description of the H8/3857, H8/3857F, and H8/3854F. 1.
Page 90: Notes On Bit Manipulation
2. CPU 2.9.2 Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include write- only bits, and when the instruction accesses an I/O.
Page 91 2. CPU Example 2: When a BSET instruction is executed on port 3 and P3 are designated as input pins, with a low-level signal input at P3 and a high-level signal at P3 . The remaining pins, P3 to P3 , are output pins and output low-level signals.
Page 92 2. CPU As a result of this operation, bit 0 in PDR3 becomes 1, and P3 outputs a high-level signal. However, bits 7 and 6 of PDR3 end up with different values. To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR3.
Page 93 2. CPU Bit Manipulation in a Register Containing a Write-Only Bit Example 3: When a BCLR instruction is executed on PCR3 of port 3 As in the examples above, P3 and P3 are input pins, with a low-level signal input at P3 and a high-level signal at P3 .
Page 94 2. CPU As a result of this operation, bit 0 in PCR3 becomes 0, making P3 an input port. However, bits 7 and 6 in PCR3 change to 1, so that P3 and P3 change from input pins to output pins. To avoid this problem, store a copy of the PCR3 data in a work area in memory.
Page 95 2. CPU Table 2.12 lists registers that share the same address, and table 2.13 lists registers that contain write-only bits. Table 2.12 Registers with shared addresses Register Name Abbreviation Address Timer counter B and timer load register B TCB/TLB H'FFB3 Timer counter C and timer load register C* TCC/TLC H'FFB5...
Page 96: Notes On Use Of The Eepmov Instruction
2. CPU 2.9.3 Notes on Use of the EEPMOV Instruction • The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 + R4L R6 + R4L •...
Page 97: Section 3 Exception Handling
3. Exception Handling Section 3 Exception Handling Overview Exception handling is performed in the H8/3857 Group when a reset or interrupt occurs. Table 3.1 shows the priorities of these two types of exception handling. Table 3.1 Exception Handling Types and Priorities Priority Exception Source Time of Start of Exception Handling...
Page 98: Interrupt Immediately After Reset
3. Exception Handling Figure 3.1 shows the reset sequence. Reset cleared Program initial instruction prefetch Vector fetch Internal processing φ Internal address bus Internal read signal Internal write signal Internal data bus (16-bit) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) First instruction of program Figure 3.1 Reset Sequence...
Page 99: Interrupts
3. Exception Handling Interrupts 3.3.1 Overview In the H8/3857 Group, sources that initiate interrupt exception handling include 13 external interrupts (WKP to WKP , and IRQ to IRQ ), and 16 internal interrupts from on-chip peripheral modules. In the H8/3854 Group, sources that initiate interrupt exception handling include 12 external interrupts (WKP to WKP , IRQ...
Page 100 3. Exception Handling Table 3.2 Interrupt Sources and Priorities Vector Priority Interrupt Source Interrupt Number Vector Address* High Reset H'0000 to H'0001 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 SCI1* SCI1 transfer complete H'0014 to H'0015...
Page 101: Interrupt Control Registers
3. Exception Handling 3.3.2 Interrupt Control Registers Table 3.3 lists the registers that control interrupts. Table 3.3 Interrupt Control Registers Register Name Abbreviation Initial Value Address IRQ edge select register* IEGR H'E0 H'FFF2 Interrupt enable register 1* IENR1 H'00 H'FFF3 Interrupt enable register 2* IENR2 H'00...
Page 102 3. Exception Handling Edge Select (IEG3): Bit 3 selects the input sensing of pin IRQ Bit 3—IRQ /TMIF. Bit 3: IEG3 Description Falling edge of IRQ /TMIF pin input is detected (initial value) Rising edge of IRQ /TMIF pin input is detected Bit 2—IRQ Edge Select (IEG2): Bit 2 is used in the H8/3857 Group to select the input sensing of pin IRQ...
Page 103 3. Exception Handling Bit 7—Timer A Interrupt Enable (IENTA): Bit 7 enables or disables timer A overflow interrupt requests. Bit 7: IENTA Description Disables timer A interrupts (initial value) Enables timer A interrupts Bit 6—SCI1 Interrupt Enable (IENS1): Bit 6 is used in the H8/3857 Group to enable or disable SCI1 transfer complete interrupt requests.
Page 104 3. Exception Handling Interrupt Enable Register 2 (IENR2) ⎯ ⎯ IENDT IENAD IENTFH IENTFL IENTC* IENTB Initial value Read/Write Note: Applies to the H8/3857 Group. In the H8/3854 Group, this bit must always be cleared to IENR2 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7—Direct Transfer Interrupt Enable (IENDT): Bit 7 enables or disables direct transfer interrupt requests.
Page 105 3. Exception Handling Bit 2—Timer FL Interrupt Enable (IENTFL): Bit 2 enables or disables timer FL compare match and overflow interrupt requests. Bit 2: IENTFL Description Disables timer FL interrupts (initial value) Enables timer FL interrupts Bit 1—Timer C Interrupt Enable (IENTC): Bit 1 is used in the H8/3857 Group to enable or disable timer C overflow or underflow interrupt requests.
Page 106 3. Exception Handling Bit 7—Timer A Interrupt Request Flag (IRRTA) Bit 7: IRRTA Description Clearing condition: When IRRTA = 1, it is cleared by writing 0 (initial value) Setting condition: When the timer A counter value overflows (goes from H'FF to H'00) Bit 6—SCI1 Interrupt Request Flag (IRRS1): Bit 6 is used in the H8/3857 Group.
Page 107 3. Exception Handling Interrupt Request Register 2 (IRR2) ⎯ ⎯ IRRDT IRRAD IRRTFH IRRTFL IRRTC* IRRTB Initial value ⎯ ⎯ Read/Write R/W* R/W* R/W* R/W* R/W* R/W* Notes: 1. Only a write of 0 for flag clearing is possible. 2. Applies to the H8/3857 Group. In the H8/3854 Group, this bit must always be cleared to IRR2 is an 8-bit read/write register, in which the corresponding bit is set to 1 when a direct transfer, A/D converter, timer FH, timer FL, timer C, or timer B interrupt is requested.
Page 108 3. Exception Handling Bit 3—Timer FH Interrupt Request Flag (IRRTFH) Bit 3: IRRTFH Description Clearing condition: When IRRTFH = 1, it is cleared by writing 0 (initial value) Setting condition: When counter FH matches output compare register FH in 8-bit timer mode, or when 16-bit counter F (TCFL, TCFH) matches output compare register F (OCRFL, OCRFH) in 16-bit timer mode Bit 2—Timer FL Interrupt Request Flag (IRRTFL)
Page 109: External Interrupts
3. Exception Handling Wakeup Interrupt Request Register (IWPR) IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Initial value Read/Write R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Note: Only a write of 0 for flag clearing is possible. IWPR is an 8-bit read/write register, in which the corresponding bit is set to 1 when pins WKP are set to wakeup input and a pin receives a falling edge input.
Page 110: Internal Interrupts
3. Exception Handling are requested by into pins inputs to IRQ Interrupts IRQ to IRQ : Interrupts IRQ to IRQ . These interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG0 to IEG4 in the edge select register (IEGR). The IRQ interrupt is a function of the H8/3857 Group only, and is not provided in the H8/3854 Group.
Page 111 3. Exception Handling • If the interrupt is accepted, after processing of the current instruction is completed, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.4. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling.
Page 112 3. Exception Handling Program execution state IRRI0 = 1 IEN0 = 1 IRRI1 = 1 IEN1 = 1 IRRI2 = 1* IEN2 = 1* IRRDT = 1 IENDT = 1 I = 0 PC contents saved CCR contents saved I ← 1 Branch to interrupt handling routine Legend:...
Page 113 3. Exception Handling SP – 4 SP (R7) SP – 3 SP + 1 CCR* SP – 2 SP + 2 SP – 1 SP + 3 SP (R7) SP + 4 Even address Stack area Prior to start of interrupt After completion of interrupt PC and CCR exception handling...
Page 114 3. Exception Handling Figure 3.5 Interrupt Sequence Rev.3.00 Jul. 19, 2007 page 88 of 532 REJ09B0397-0300...
Page 115: Interrupt Response Time
3. Exception Handling 3.3.6 Interrupt Response Time Table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3.4 Interrupt Wait States Item States Waiting time for completion of executing instruction* 1 to 13 Saving of PC and CCR to stack Vector fetch...
Page 116: Notes On Rewriting Port Mode Registers
3. Exception Handling → H'FEFC → H'FEFD → H'FEFF MOV. B R1L, @–R7 BSR instruction SP set to H'FEFF Stack accessed beyond SP Contents of PC are lost Legend: Upper byte of program counter Lower byte of program counter R1L: General register R1L Stack pointer Figure 3.6 Operation when Odd Address Is Set in SP...
Page 117 3. Exception Handling Table 3.5 Conditions under which Interrupt Request Flag Is Set to 1 Interrupt Request Flags Set to 1 Conditions When PMR2 bit IRQ4 is changed from 0 to 1 while pin IRQ • IRR1 IRRI4 is low and IEGR bit IEG4 = 0.
Page 118 3. Exception Handling Figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0.
Page 119: Section 4 Clock Pulse Generators
4. Clock Pulse Generators Section 4 Clock Pulse Generators Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider.
Page 120: System Clock Generator
4. Clock Pulse Generators The clock signals available for use by peripheral modules are φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, φ/8192, φ , φ /2, φ /4, φ /8, φ /16, φ /32, φ /64, and φ...
Page 121 4. Clock Pulse Generators Connecting a Ceramic Oscillator: Figure 4.4 shows a typical method of connecting a ceramic oscillator. R = 1 MΩ ±20% C = 30 pF ±10% C = 30 pF ±10% Ceramic oscillator: Murata Figure 4.4 Typical Connection to Ceramic Oscillator Notes on Board Design: When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points.
Page 122: Subclock Generator
4. Clock Pulse Generators Inputting an External Clock: When inputting an external clock, connect it to the OSC pin via a resistance R, and leave the OSC pin open. An example of the connection in this case is shown in figure 4.6. External clock input Open R = 500 Ω...
Page 123 4. Clock Pulse Generators Figure 4.8 shows the equivalent circuit of the 32.768-kHz crystal oscillator. C = 1.5 pF typ R = 14 kΩ typ = 32.768 kHz Crystal oscillator: MX38T (Nihon Denpa Kogyo) Figure 4.8 Equivalent Circuit of 32.768-kHz Crystal Oscillator Inputting an External Clock •...
Page 124 4. Clock Pulse Generators Figure 4.10 External Subclock Timing The DC characteristics and timing of an external clock input to the X pin are shown in table 4.2. Table 4.2 DC Characteristics and Timing = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3853, and H8/3854, = 3.0 V to 5.5 V of H8/3854F and H8/3857 Group, AV = 3.0 V to 5.5 V, = AV...
Page 125: Prescalers
4. Clock Pulse Generators Prescalers The H8/3857 Group and H8/3854 Group are equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules.
Page 126: Note On Oscillators
4. Clock Pulse Generators Note on Oscillators Oscillator characteristics of both the mask ROM and F-ZTAT versions are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors.
Page 127: Section 5 Power-Down Modes
5. Power-Down Modes Section 5 Power-Down Modes Overview The H8/3857 Group and H8/3854 Group have seven modes of operation after a reset. These include six power-down modes, in which power dissipation is significantly reduced. Table 5.1 gives a summary of the seven operation modes. Table 5.1 Operation Modes Operating Mode...
Page 128 5. Power-Down Modes Program execution state Program halt state Reset state LSON = 0, MSON = 0 Program halt state Active (high-speed) mode SSBY = 1, TMA3 = 0, SSBY = 0, LSON = 0 LSON = 0 Standby mode Sleep mode LSON = 0, MSON = 1...
Page 129 5. Power-Down Modes Table 5.2 Internal State in Each Operation Mode Active Mode High Medium Sleep Watch Subactive Subsleep Standby Function Speed Speed Mode Mode Mode Mode Mode System clock oscillator Functions Functions Functions Halted Halted Halted Halted Subclock oscillator Functions Functions Functions...
Page 130: System Control Registers
5. Power-Down Modes 5.1.1 System Control Registers The operation mode is selected using the system control registers described in table 5.3. Table 5.3 System Control Register Name Abbreviation Initial Value Address System control register 1 SYSCR1 H'07 H'FFF0 System control register 2 SYSCR2 H'E0 H'FFF1...
Page 131 5. Power-Down Modes Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. The designation should be made according to the clock frequency so that the waiting time is at least 10 ms.
Page 132 5. Power-Down Modes Bit 4—Noise Elimination Sampling Frequency Select (NESEL): This bit selects the frequency at which the watch clock signal (φ ) generated by the subclock pulse generator is sampled, in ) generated by the system clock pulse generator. When φ relation to the oscillator clock (φ...
Page 133: Sleep Mode
5. Power-Down Modes Bits 1 and 0—Subactive Mode Clock Select (SA1, SA0): These bits select the CPU clock rate /2, φ /4, or φ (φ /8) in subactive mode. SA1 and SA0 cannot be modified in subactive mode. Bit 1: SA1 Bit 0: SA0 Description φ...
Page 134: Standby Mode
5. Power-Down Modes Standby Mode 5.3.1 Transition to Standby Mode The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit is cleared to 0, and bit TMA3 in timer register A (TMA) is cleared to 0.
Page 135: Transition To Standby Mode And Port Pin States
5. Power-Down Modes Table 5.4 Clock Frequency and Settling Time (Times are in ms) STS2 STS1 STS0 Waiting Time 5 MHz 4 MHz 2 MHz 1 MHz 0.5 MHz 8,192 states 16.4 16,384 states 16.4 32.8 32,768 states 16.4 32.8 65.5 65,536 states 13.1...
Page 136: Notes On External Input Signal Changes Before/After Standby Mode
5. Power-Down Modes 5.3.5 Notes on External Input Signal Changes before/after Standby Mode 1. When external input signal changes before/after standby mode or watch mode When an external input signal such as IRQ or WKP is input, both the high- and low-level widths of the signal must be at least two cycles of system clock φ...
Page 137: Watch Mode
5. Power-Down Modes Active (high-speed, Wait for Active (high-speed, Operating medium-speed) mode Standby mode oscillation medium-speed) mode mode or subactive mode or watch mode to settle or subactive mode subcyc subcyc subcyc subcyc φ or φ External input signal Capture possible: case 1 Capture possible: case 2...
Page 138: Clearing Watch Mode
5. Power-Down Modes 5.4.2 Clearing Watch Mode ) or by a input at the RES Watch mode is cleared by an interrupt (timer A, IRQ , WKP to WKP pin. Clearing by Interrupt: Watch mode is cleared when an interrupt is requested. The mode to which a transition is made depends on the settings of LSON in SYSCR1 and MSON in SYSCR2.
Page 139: Clearing Subsleep Mode
5. Power-Down Modes 5.5.2 Clearing Subsleep Mode Subsleep mode is cleared by an interrupt (timer A, timer C*, IRQ , IRQ , IRQ *, IRQ , IRQ ) or by a low input at the RES pin. to WKP Note: * The timer C and IRQ interrupts are functions of the H8/3857 Group only, and are not provided in the H8/3854 Group.
Page 140: Operating Frequency In Subactive Mode
5. Power-Down Modes 5.6.3 Operating Frequency in Subactive Mode The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices are φ /2, φ /4, and φ Active (medium-speed) Mode 5.7.1 Transition to Active (medium-speed) Mode If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed) mode results from IRQ , IRQ...
Page 141: Direct Transfer
5. Power-Down Modes Direct Transfer 5.8.1 Direct Transfer Overview The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program execution. A direct transfer can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1.
Page 142: Calculation Of Direct Transfer Time Before Transition
5. Power-Down Modes Direct Transfer from Subactive Mode to Active (Medium-Speed) Mode: When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the DTON bit in SYSCR2 is set to 1, and TMA3 bit in TMA is set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0 has elapsed.
Page 143 5. Power-Down Modes Example: Direct transfer time for the H8/3857 Group and H8/3854 Group = (2 + 1) × 16tosc + 14 × 2tosc = 76 tosc Legend: tosc: OSC clock cycle time tcyc: System clock (φ) cycle time Time Required before Direct Transfer from Subactive Mode to Active (High-Speed) Mode: A direct transfer is made from subactive mode to active (high-speed) mode when a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, the DTON bit in SYSCR2 is...
Page 144: Notes On External Input Signal Changes Before/After Direct Transition
5. Power-Down Modes Example: Direct transfer time for the H8/3857 Group and H8/3854 Group (when CPU clock frequency is φw/8 and wait time is 8192 states) = (2 + 1) × 8tw + (8192 + 14) × 16tosc = 24tw + 131296tosc Legend: tosc: OSC clock cycle time...
Page 145: Section 6 Rom
6. ROM Section 6 ROM Overview The H8/3857 has 60 kbytes of on-chip flash memory or mask ROM, while the H8/3856 has 48 kbytes, and the H8/3855 40 kbytes, of on-chip mask ROM. The H8/3854 has 60 kbytes of on-chip flash memory or 32 kbytes of on-chip mask ROM, while the H8/3853 has 24 kbytes, and the H8/3852 16 kbytes, of on-chip mask ROM.
Page 146: Overview Of Flash Memory
6. ROM Overview of Flash Memory 6.2.1 Features Features of the flash memory are summarized below. • Four flash memory operating modes ⎯ Program mode ⎯ Erase mode ⎯ Program-verify mode ⎯ Erase-verify mode • Programming/erase methods The flash memory is programmed 32 bytes at a time. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
Page 147: Block Diagram
6. ROM 6.2.2 Block Diagram Internal data bus (lower 8 bits) Internal data bus (upper 8 bits) SYSCR3 FLMCR1 Operating Bus interface/controller FWE pin mode FLMCR2 TEST2 pin MDCR TEST pin H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 On-chip flash memory (60 kbytes) H'EDFC H'EDFD H'EDFE...
Page 148: Flash Memory Operating Modes
6. ROM 6.2.3 Flash Memory Operating Modes Mode Transition Diagram: When the TEST , TEST, and FWE pins are set in the reset state and a reset start is effected, the chip enters one of the operating modes shown in figure 6.3. In user mode, the flash memory can be read but cannot be programmed or erased.
Page 149 6. ROM On-Board Programming Modes • Boot Mode Initial state 2. Programming control program transfer The flash memory is in the erased state when shipped. When boot mode is entered, the boot program in the The procedure for rewriting an old version of an chip (already incorporated in the chip) is started, an application program or data is described here.
Page 150 6. ROM • User Program Mode 1. Initial state 2. Programming/erase control program transfer The FWE assessment program that confirms that a high When a high level is applied to the FWE pin, user level has been applied to the FWE pin, and the program software confirms this fact, executes the transfer program that will transfer the programming/erase control program in the flash memory, and transfers the programming/erase...
Page 151: Pin Configuration
6. ROM Differences between Boot Mode and User Program Mode Table 6.1 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Total erase Possible Possible Block erase Not possible Possible Programming control program* Program/program-verify Erase/erase-verify Program/program-verify Note: To be provided by the user, in accordance with the recommended algorithm.
Page 152: Register Configuration
6. ROM 6.2.5 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 6.3. In order to access these registers, the FLSHE bit in SYSCR3 must be set to 1. Table 6.3 Flash Memory Registers Register Name Abbr.
Page 153 6. ROM when FWE = 1, then setting the ESU bit in FLMCR2, and finally setting the E bit. FLMCR1 is initialized by a reset and in standby mode. Its initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low level is input.
Page 154 6. ROM Bit 2—Program-Verify (PV)* : Bit 2 selects program-verify mode transition or clearing. (Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time.) Bit 2: PV Description Program-verify mode cleared (initial value) Transition to program-verify mode [Setting condition] When FWE = 1 and SWE = 1 Bit 1—Erase (E)*...
Page 155: Flash Memory Control Register 2 (Flmcr2)
6. ROM 6.3.2 Flash Memory Control Register 2 (FLMCR2) ⎯ ⎯ ⎯ ⎯ ⎯ FLER Initial value ⎯ ⎯ ⎯ ⎯ ⎯ Read/Write FLMCR2 is an 8-bit register used for monitoring of flash memory program/erase protection (error protection) and for flash memory program/erase mode setup. FLMCR2 is initialized to H'00 by a reset.
Page 156: Erase Block Register (Ebr)
6. ROM Bit 0—Program Setup (PSU)*: Bit 0 prepares for a transition to program mode. Set this bit to 1 before setting the P bit in FLMCR1. (Do not set the SWE, ESU, EV, PV, E, or P bit at the same time.) Bit 0: PSU Description...
Page 157: Mode Control Register (Mdcr)
6. ROM Table 6.4 Flash Memory Erase Blocks Block (Size) Addresses EB0 (1 kbyte) H'0000 to H'03FF EB1 (1 kbyte) H'0400 to H'07FF EB2 (1 kbyte) H'0800 to H'0BFF EB3 (1 kbyte) H'0C00 to H'0FFF EB4 (28 kbytes) H'1000 to H'7FFF EB5 (16 kbytes) H'8000 to H'BFFF EB6 (12 kbytes)
Page 158: On-Board Programming Modes
6. ROM SYSCR3 is initialized to H'00 by a reset. Bits 7 to 4—Reserved Bits: Bits 7 to 4 are reserved; they are always read as 0 and cannot be modified. Bit 3—Flash Memory Control Register Enable (FLSHE): Bit 3 controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, and EBR).
Page 159: Boot Mode
6. ROM 6.4.1 Boot Mode To use boot mode, a user program for programming and erasing the flash memory must be provided in advance in the host. SCI3 is used in asynchronous mode. When a reset start is executed after the chip's pins have been set to boot mode, the built-in boot program is activated, and the programming control program provided in the host is transferred sequentially to the chip using SCI3.
Page 160 6. ROM Start Set pins to boot mode and execute reset start Host transmits data (H'00) continuously at prescribed bit rate Chip measures low period of H'00 data transmitted by host Chip calculates bit rate and sets value in bit rate register After bit rate adjustment, chip transmits one H'00 data byte to host to indicate end of adjustment...
Page 161 6. ROM Automatic SCI Bit Rate Adjustment Start Stop Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 6.9 RXD Input Signal in Automatic SCI Bit Rate Adjustment When boot mode is initiated, the chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host .
Page 162 6. ROM Table 6.6 System Clock Oscillation Frequencies for which Automatic Adjustment of Chip's Bit Rate is Possible System Clock Oscillation Frequencies (f ) for which Automatic Adjustment Host Bit Rate of Chip's Bit Rate is Possible 9600bps 1.2288 MHz, 2.4576 MHz, 4.9152 MHz, 6 MHz to 10 MHz 4800bps 1.2288 MHz, 2.4576 MHz, 4 MHz to 10 MHz 2400bps...
Page 163 6. ROM Notes on Use of Boot Mode 1. When the chip comes out of reset in boot mode, it measures the low period of the input at the SCI3's RXD pin. The reset should end with RXD high. After the reset ends, it takes about 100 states for the chip to get ready to measure the low period of the RXD input.
Page 164: User Program Mode
6. ROM 3. For further information on FWE application and disconnection, see section 6.9, Flash Memory Programming and Erasing Precautions. 6.4.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user programming/erase control program.
Page 165 6. ROM Figure 6.11 shows the execution procedure when the programming/erase control program is transferred to on-chip RAM. Write FWE assessment program and transfer program (and programming/erase control program if necessary) beforehand TEST2 = 1, TEST = 0 Reset start Transfer programming/erase control program to RAM Branch to programming/erase...
Page 166: Flash Memory Programming/Erasing
6. ROM Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the on- board programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes are made by setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1.
Page 167: Program-Verify Mode
6. ROM performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a value greater than (y + z + α + β) μs as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU bit in FLMCR2, and after the elapse of (y) μs or more, the operating mode is switched to program mode by setting the P bit in FLMCR1.
Page 168 6. ROM START Set SWE bit in FLMCR1 Wait (x) μs Store 32-byte programming data in programming data area and reprogramming data area n = 1 m = 0 Consecutively write 32-byte data in repro- gramming data area in RAM to flash memory Enable WDT Set PSU bit in FLMCR2 Wait (y) μs...
Page 169: Erase Mode
6. ROM 6.5.3 Erase Mode To erase an individual flash memory block, follow the erase/erase-verify flowchart (single-block erase) shown in figure 6.13. The wait times (x, y, z, α, β, γ, ε, η) after bits are set or cleared in flash memory control register 1 (FLMCR1) and flash memory control register 2 (FLMCR2), and the maximum number of erase operations (N), are shown in table 15.10 in section 15.2.6, Flash Memory Characteristics.
Page 170 6. ROM START Set SWE bit in FLMCR1 Wait (x) μs n = 1 Set EBR Enable WDT Set ESU bit in FLMCR2 Wait (y) μs Set E bit in FLMCR1 Start of erase Wait (z) ms Clear E bit in FLMCR1 Erase halted Wait (α) μs Clear ESU bit in FLMCR2...
Page 171: Flash Memory Protection
6. ROM Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware, software, and error protection. 6.6.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. In this state, the settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and the erase block register (EBR) are reset.
Page 172: Software Protection
6. ROM 6.6.2 Software Protection Software protection can be implemented by setting the SWE bit in flash memory control register 1 (FLMCR1), and the erase block register (EBR). With software protection, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode. (See table 6.8.) Table 6.8 Software Protection Functions...
Page 173 6. ROM 3. When a SLEEP instruction (including software standby) is executed during programming/erasing Error protection is released only by a reset. Figure 6.14 shows the flash memory state transition diagram. Notes: 1. This is the state in which the P bit or E bit is set to 1 in FLMCR1. 2.
Page 174: Interrupt Handling During Flash Memory Programming And Erasing
6. ROM To prevent such abnormal operations, therefore, it is necessary to ensure correct operation in accordance with the program/erase algorithm, with the flash write enable (FWE) voltage applied, and to conduct constant monitoring for MCU errors, internally and externally, using the watchdog timer or other means.
Page 175: Flash Memory Writer Mode
In Writer mode, the on-chip ROM can be freely programmed using a PROM programmer that supports the Renesas Technology microcomputer device type with 64-kbyte on- chip flash memory. Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type.
Page 176 6. ROM HD64F3857 MCU mode Writer mode HD64F3854 H'0000 H'0000 On-chip ROM area H'EDFF H'EDFF Undefined values output H'1FFFF Figure 6.15 Memory Map in Writer Mode Rev.3.00 Jul. 19, 2007 page 150 of 532 REJ09B0397-0300...
Page 177 6. ROM Socket Adapter HD64F3857 (32-Pin Conversion) HN28F101P (32 Pins) FP-144H, TFP-144 Pin Name Pin Name Pin No. SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 FA10 SEG12 FA11 SEG13 FA12 SEG14 FA13 SEG15 FA14 SEG16 FA15 SEG23 SEG22 SEG21...
Page 178 6. ROM Socket Adapter (32-Pin Conversion) HD64F3854 HN28F101P (32 Pins) FP-100B, TFP-100G Pin Name Pin No. Pin Name SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 FA10 SEG11 FA11 SEG12 SEG13 FA12 FA13 SEG14 FA14 SEG15 SEG16 FA15 SEG23 SEG22 SEG21...
Page 179: Writer Mode Operation
6. ROM 6.8.3 Writer Mode Operation Table 6.10 shows how the different operating modes are set when using Writer mode, and table 6.11 lists the commands used in Writer mode. Details of each mode are given below. Memory Read Mode: Memory read mode supports byte reads. Auto-Program Mode: Auto-program mode supports programming of 128 bytes at a time.
Page 180: Memory Read Mode
6. ROM Table 6.11 Writer Mode Commands 1st Cycle 2nd Cycle Number of Command Name Cycles Mode Address Data Mode Address Data Memory read mode 1 + n write H'00 read Dout Auto-program mode write H'40 write Auto-erase mode write H'20 write H'20...
Page 181 6. ROM Table 6.12 AC Characteristics in Memory Read Mode (1) = 5.0 V ±10%, V = 25°C ±5°C) (Conditions: V = 0 V, T Item Symbol Unit Notes ⎯ μs Command write cycle nxtc CE hold time ⎯ CE setup time ⎯...
Page 182 6. ROM Table 6.13 AC Characteristics in Transition from Memory Read Mode to Another Mode = 5.0 V ±10%, V = 25°C ±5°C) (Conditions: V = 0 V, T Item Symbol Unit Notes ⎯ μs Command write cycle nxtc CE hold time ⎯...
Page 183 6. ROM Table 6.14 AC Characteristics in Memory Read Mode (2) = 5.0 V ±10%, V = 25°C ±5°C) (Conditions: V = 0 V, T Item Symbol Unit Notes ⎯ μs Access time CE output delay time ⎯ OE output delay time ⎯...
Page 184: Auto-Program Mode
6. ROM 6.8.5 Auto-Program Mode AC Characteristics Table 6.15 AC Characteristics in Auto-Program Mode = 5.0 V ±10%, V = 25°C ±5°C) (Conditions: V = 0 V, T Item Symbol Unit Notes ⎯ μs Command write cycle nxtc CE hold time ⎯...
Page 185 6. ROM ADDRESS ADDRESS STABLE nxtc nxtc Data transfer wsts 1 byte ... 128 bytes (1 to 3000ms) write Programming operation end identification signal Programming normal end identification signal Programming wait H'40 DATA DATA FO0 to 5= 0 DATA Figure 6.21 Auto-Program Mode Timing Waveforms Notes on Use of Auto-Program Mode 1.
Page 186: Auto-Erase Mode
6. ROM 6.8.6 Auto-Erase Mode AC Characteristics Table 6.16 AC Characteristics in Auto-Erase Mode = 5.0 V ±10%, V = 25°C ±5°C) (Conditions: V = 0 V, T Item Symbol Unit Notes ⎯ μs Command write cycle nxtc CE hold time ⎯...
Page 187: Status Read Mode
6. ROM Notes on Use of Auto-Erase Mode 1. Auto-erase mode supports only total memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking FO . Alternatively, status read mode can also be used for this purpose (the FO status polling pin is used to identify the end of an auto-erase operation).
Page 188: Status Polling
6. ROM ADDRESS nxtc nxtc nxtc H'71 H'71 DATA DATA Note: FO2 and FO3 are undefined. Figure 6.23 Status Read Mode Timing Waveforms Table 6.18 Status Read Mode Return Codes Pin Name ⎯ ⎯ Attribute Normal end Command Programming Erase error Programming Valid address identification...
Page 189: Writer Mode Transition Time
Notes: 1. The memory is initially in the erased state when the device is shipped by Renesas. For other chips for which the erasure history is unknown, it is recommended that auto- erasing be executed to check and supplement the initialization (erase) level.
Page 190: Flash Memory Programming And Erasing Precautions
1. Use the specified voltages and timing for programming and erasing. Applying a voltage in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas Technology microcomputer device type with 64-kbyte on-chip flash memory.
Page 191 6. ROM 4. Do not apply a constant high level to the FWE pin To prevent erroneous programming or erasing due to program runaway, etc., apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE pin should be avoided.
Page 192: Notes When Converting The F-Ztat Application Software To The Mask-Rom Versions
6. ROM 6.10 Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions Please note the following when converting the F-ZTAT application software to the mask-ROM versions. The values read from the internal registers for the flash ROM or the mask-ROM version and F-ZTAT version differ as follows.
Page 193: Section 7 Ram
7. RAM Section 7 RAM Overview The H8/3857 Group and the H8/3854 flash memory version have 2 kbytes of high-speed on-chip static RAM, and the H8/3854 Group mask ROM version has 1 kbyte. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. Note that the H8/3854 flash memory and mask ROM versions have different ROM and RAM sizes.
Page 194 7. RAM Rev.3.00 Jul. 19, 2007 page 168 of 532 REJ09B0397-0300...
Page 195: Section 8 I/O Ports
8. I/O Ports Section 8 I/O Ports Overview The H8/3857 Group is provided with four 8-bit I/O ports, one 3-bit I/O port, one 8-bit input-only port, and one 1-bit input-only port. The H8/3854 Group is provided with two 8-bit I/O ports, one 3-bit I/O port, one 5-bit I/O port, one 4-bit input-only port, and one 1-bit input-only port.
Page 196 8. I/O Ports Table 8.1 (a) H8/3857 Group Port Functions Function Switching Port Description Pins Other Functions Register • 8-bit I/O port Port 1 to P1 External interrupts 3 to 1 PMR1 to IRQ • Input pull-up MOS Timer event input TMIF, TMIC, TCRF, TMIF, TMIC, TMIB...
Page 197 8. I/O Ports Table 8.1 (b) H8/3854 Group Port Functions Function Switching Port Description Pins Other Functions Register • 5-bit I/O port Port 1 , P1 External interrupts 3, 1 PMR1 , IRQ • Input pull-up MOS Timer event input TMIF, TMIB TCRF, TMIF, TMIB option...
Page 198: Port 1
8. I/O Ports Port 1 Some port 1 functions differ between the H8/3857 Group and the H8/3854 Group. The P1 /IRQ /TMIC, P1 /PWM, and P1 pins are provided only in the H8/3857 Group, and not in the H8/3854 Group. 8.2.1 Overview Port 1 is an 8-bit I/O port.
Page 199: Register Configuration And Description
8. I/O Ports 8.2.2 Register Configuration and Description Table 8.2 shows the port 1 register configuration. Table 8.2 Port 1 Registers Name Abbr. Initial Value Address Port data register 1 PDR1 H'00 H'FFD4 Port control register 1 PCR1 H'00 H'FFE4 Port pull-up control register 1 PUCR1 H'00...
Page 200 8. I/O Ports Port Control Register 1 (PCR1) PCR1 is an 8-bit register for controlling whether each of the port 1 pins P1 to P1 functions as an input pin or output pin. Setting a PCR1 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin.
Page 201 8. I/O Ports Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls whether the MOS pull-up of each port 1 pin is on or off. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Page 202 8. I/O Ports Port Mode Register 1 (PMR1) PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. Upon reset, PMR1 is initialized to H'00. H8/3857 Group ⎯ IRQ3 IRQ2 IRQ1 TMOFH TMOFL TMOW Initial value ⎯...
Page 203 8. I/O Ports In the H8/3854 Group, bit 6 is reserved, and must always be cleared to 0. Bit 5—P1 /IRQ /TMIB Pin Function Switch (IRQ1): This bit selects whether pin or as IRQ /IRQ /TMIB is used as P1 /TMIB.
Page 204: Pin Functions
8. I/O Ports Bit 0—P1 /TMOW Pin Function Switch (TMOW): This bit selects whether pin P1 /TMOW is used as P1 or as TMOW. Bit 0: TMOW Description Functions as P1 I/O pin (initial value) Functions as TMOW output pin 8.2.3 Pin Functions H8/3857 Group port 1 pin functions are shown in figure 8.3 (a), and H8/3854 Group port 1 pin...
Page 205 8. I/O Ports Pin Functions and Selection Method /IRQ /TMIB The pin function depends on bit IRQ1 in PMR1, bits TMB2 to TMB0 in TMB, and bit PCR1 in PCR1. IRQ1 PCR1 TMB2 to TMB0 Not 111 output pin IRQ Pin function input pin input pin...
Page 206 8. I/O Ports Table 8.3 (b) H8/3854 Group Port 1 Pin Functions Pin Functions and Selection Method /IRQ /TMIF The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF, and bit PCR1 in PCR1. IRQ3 PCR1 CKSL2 to CKSL0 Not 0**...
Page 207: Pin States
8. I/O Ports 8.2.4 Pin States H8/3857 Group port 1 pin states in each operating mode are shown in table 8.4 (a), and H8/3854 Group port 1 pin states in each operating mode in table 8.4 (b). Table 8.4 (a) H8/3857 Group Port 1 Pin States Pins Reset...
Page 208: Mos Input Pull-Up
8. I/O Ports 8.2.5 MOS Input Pull-Up Port 1 has a built-in MOS input pull-up function that can be controlled by software. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS input pull-up for that pin.
Page 209: Register Configuration And Description
8. I/O Ports Port 2 P2 /IRQ /ADTRG Figure 8.2 (b) H8/3854 Group Port 2 Pin Configuration 8.3.2 Register Configuration and Description Table 8.5 shows the port 2 register configuration. Table 8.5 Port 2 Registers Name Abbr. Initial Value Address Port data register 2 PDR2 H'00...
Page 210 8. I/O Ports Port Control Register 2 (PCR2) PCR2 PCR2 PCR2 PCR2 PCR2 PCR2 PCR2 PCR2 Initial value Read/Write PCR2 is an 8-bit register for controlling whether each of the port 2 pins P2 to P2 functions as an input pin or output pin. Setting a PCR2 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin.
Page 211 8. I/O Ports Bits 7 and 6—Reserved Bits: Bits 7 and 6 are reserved; they are always read as 1, and cannot be modified. Bits 5 and 4—Reserved Bits: Bits 5 and 4 are reserved; they should always be cleared to 0. Bit 3—P4 /IRQ Pin Function Switch (IRQ0): This bit selects whether pin P4...
Page 212 8. I/O Ports Port Mode Register 4 (PMR4) NMOD7 NMOD6 NMOD5 NMOD4 NMOD3 NMOD2 NMOD1 NMOD0 Initial value Read/Write PMR4 is an 8-bit read/write register, used to select CMOS output or NMOS open drain output for each port 2 pin. Upon reset, PMR4 is initialized to H'00.
Page 213: Pin Functions
8. I/O Ports 8.3.3 Pin Functions H8/3857 Group port 2 pin functions are shown in figure 8.6 (a), and H8/3854 Group port 2 pin functions in figure 8.6 (b). Table 8.6 (a) H8/3857 Group Port 2 Pin Functions Pin Functions and Selection Method to P2 Input or output is selected as follows by the bit settings in PCR2.
Page 214: Pin States
8. I/O Ports Table 8.6 (b) H8/3854 Group Port 2 Pin Functions Pin Functions and Selection Method to P2 Input or output is selected as follows by the bit settings in PCR2. PCR2n Pin function input pin output pin Note: n = 7 to 1 /IRQ /ADTRG The pin function depends on bit IRQ4 in PMR2, bit TRGE in AMR, and bit...
Page 215: Port 3 (H8/3857 Group Only)
8. I/O Ports Port 3 (H8/3857 Group Only) Port 3 is a function of the H8/3857 Group only, and is not provided in the H8/3854 Group. 8.4.1 Overview Port 3 is an 8-bit I/O port, configured as shown in figure 8.3. Port 3 P3 /SO P3 /SI...
Page 216 8. I/O Ports Port Data Register 3 (PDR3) Initial value Read/Write PDR3 is an 8-bit register that stores data for port 3 pins P3 to P3 . If port 3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are cleared to 0, the pin states are read.
Page 217 8. I/O Ports Upon reset, PUCR3 is initialized to H'00. Port Mode Register 3 (PMR3) ⎯ ⎯ ⎯ ⎯ ⎯ SCK1 Initial value ⎯ ⎯ ⎯ ⎯ ⎯ Read/Write PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. Upon reset, PMR3 is initialized to H'00.
Page 218: Pin Functions
8. I/O Ports 8.4.3 Pin Functions Table 8.9 shows the port 3 pin functions. Table 8.9 Port 3 Pin Functions Pin Functions and Selection Method to P3 The pin function depends on the corresponding bit in PCR3. PCR3 Pin function input pin output pin Note:...
Page 219: Pin States
8. I/O Ports 8.4.4 Pin States Table 8.10 shows the port 3 pin states in each operating mode. Table 8.10 Port 3 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active to P3 High- Retains Retains High- Retains Functional Functional impedance previous previous...
Page 220: Port 4
8. I/O Ports Port 4 Port 4 functions are common to the H8/3857 Group and H8/3854 Group. 8.5.1 Overview Port 4 consists of a 3-bit I/O port and a 1-bit input port, and is configured as shown in figure 8.4. P4 /IRQ P4 /TXD Port 4...
Page 221 8. I/O Ports Port Data Register 4 (PDR4) ⎯ ⎯ ⎯ ⎯ Initial value Undefined ⎯ ⎯ ⎯ ⎯ Read/Write PDR4 is an 8-bit register that stores data for port 4 pins P4 to P4 . If port 4 is read while PCR4 bits are set to 1, the values stored in PDR4 are read, regardless of the actual pin states.
Page 222: Pin Functions
8. I/O Ports 8.5.3 Pin Functions Table 8.12 shows the port 4 pin functions. Table 8.12 Port 4 Pin Functions Pin Functions and Selection Method /IRQ The pin function depends on the IRQ0 bit setting in PMR2. IRQ0 Pin function input pin input pin /TXD...
Page 223: Pin States
8. I/O Ports 8.5.4 Pin States Table 8.13 shows the port 4 pin states in each operating mode. Table 8.13 Port 4 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /IRQ High- Retains Retains High- Retains Functional Functional impedance previous previous...
Page 224: Register Configuration And Description
8. I/O Ports 8.6.2 Register Configuration and Description Table 8.14 shows the port 5 register configuration. Table 8.14 Port 5 Registers Name Abbr. Initial Value Address Port data register 5 PDR5 H'00 H'FFD8 Port control register 5 PCR5 H'00 H'FFE8 Port pull-up control register 5 PUCR5 H'00...
Page 225 8. I/O Ports Port Pull-up Control Register 5 (PUCR5) PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 Initial value Read/Write PUCR5 bits control the on/off state of pin P5 –P5 MOS pull-ups. When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Page 226: Pin Functions
8. I/O Ports 8.6.3 Pin Functions Table 8.15 shows the port 5 pin functions. Table 8.15 Port 5 Pin Functions Pin Functions and Selection Method /WKP The pin function depends on bit WKPn in PMR5 and bit PCR5 in PCR5. /WKP WKPn PCR5...
Page 227: Port 9 [Chip-Internal I/O Port]
8. I/O Ports Port 9 [Chip-Internal I/O port] Port 9 functions are common to the H8/3857 Group and H8/3854 Group. 8.7.1 Overview Port 9 is an 8-bit I/O port that interfaces to the on-chip LCD controller. The port 9 pin configuration is shown in figure 8.6.
Page 228: Pin Functions
8. I/O Ports Port Data Register 9 (PDR9) Initial value Read/Write PDR9 is an 8-bit register that stores data for port 9 pins P9 to P9 . If port 9 is read while PCR9 bits are set to 1, the values stored in PDR9 are read. If port 9 is read while PCR9 bits are cleared to 0, the pin states are read.
Page 229: Pin States
8. I/O Ports 8.7.4 Pin States Table 8.19 shows the port 9 pin states in each operating mode. Table 8.19 Port 9 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active to P9 High- Retains Retains High- Retains Functional Functional impedance previous previous...
Page 230: Register Configuration And Description
8. I/O Ports 8.8.2 Register Configuration and Description Table 8.20 shows the port A register configuration. Table 8.20 Port A Registers Name Abbr. Initial Value Address Port data register A PDRA H'F0 H'FFDD Port control register A PCRA H'F0 H'FFED Port Data Register A (PDRA) ⎯...
Page 231: Pin Functions
8. I/O Ports 8.8.3 Pin Functions Table 8.21 gives the port A pin functions. Table 8.21 Port A Pin Functions Pin Functions and Selection Method to PA The pin function depends on the corresponding bit in PCRA. PCRA Pin function input pin output pin Note: n = 3 to 0...
Page 232: Port B
8. I/O Ports Port B Some port B functions differ between the H8/3857 Group and the H8/3854 Group. Pins PB to PB to AN are provided only in the H8/3857 Group, and not in the H8/3854 Group. 8.9.1 Overview Port B is an 8-bit input-only port. The H8/3857 Group port B pin configuration is shown in figure 8.8 (a), and the H8/3854 Group port B pin configuration in figure 8.8 (b).
Page 233: Register Configuration And Description
8. I/O Ports 8.9.2 Register Configuration and Description Table 8.23 shows the port B register configuration. Table 8.23 Port B Register Name Abbr. Address Port data register B PDRB H'FFDE Port Data Register B (PDRB) Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input voltage.
Page 234 8. I/O Ports Rev.3.00 Jul. 19, 2007 page 208 of 532 REJ09B0397-0300...
Page 235: Section 9 Timers
9. Timers Section 9 Timers Overview The H8/3857 Group is provided with four timers (timers A, B, C, and F), and the H8/3854 Group with three (timers A, B, and F). The H8/3857F and H8/3854F also have an on-chip watchdog timer for flash memory programming control.
Page 236: Timer A
9. Timers Timer A 9.2.1 Overview Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768-kHz crystal oscillator is connected. A clock signal divided from 32.768 kHz or from the system clock can be output at the TMOW pin. Features Features of timer A are given below.
Page 237 9. Timers Block Diagram Figure 9.1 shows a block diagram of timer A. φ φ /4 φ /32 φ /16 φ /8 φ /4 φ /128 TMOW φ /32 φ/8192, φ/4096, φ/2048, φ /16 φ/512, φ/256, φ/128, φ /8 φ/32, φ/8 φ...
Page 238: Register Descriptions
9. Timers Register Configuration Table 9.3 shows the register configuration of timer A. Table 9.3 Timer A Registers Name Abbr. Initial Value Address Timer mode register A H'10 H'FFB0 Timer counter A H'00 H'FFB1 9.2.2 Register Descriptions Timer Mode Register A (TMA) ⎯...
Page 239 9. Timers Bit 4—Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified. Bits 3 to 0—Internal Clock Select (TMA3 to TMA0): Bits 3 to 0 select the clock input to TCA. Description Bit 3: Bit 2: Bit 1: Bit 0:...
Page 240: Timer Operation
9. Timers Upon reset, TCA is initialized to H'00. 9.2.3 Timer Operation Interval Timer Operation: When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval timing resume immediately.
Page 241: Timer A Operation States
9. Timers 9.2.4 Timer A Operation States Table 9.4 summarizes the timer A operation states. Table 9.4 Timer A Operation States Sub- Sub- Operation Mode Reset Active Sleep Watch active sleep Standby TCA Interval Reset Functions Functions Halted Halted Halted Halted Clock time base Reset...
Page 242 9. Timers φ TMIB IRRTB Legend: TMB: Timer mode register B TCB: Timer counter B TLB: Timer load register B IRRTB: Timer B overflow interrupt request flag PSS: Prescaler S Figure 9.2 Block Diagram of Timer B Pin Configuration Table 9.5 shows the timer B pin configuration. Table 9.5 Pin Configuration Name...
Page 243: Register Descriptions
9. Timers 9.3.2 Register Descriptions Timer Mode Register B (TMB) ⎯ ⎯ ⎯ ⎯ TMB7 TMB2 TMB1 TMB0 Initial value ⎯ ⎯ ⎯ ⎯ Read/Write TMB is an 8-bit read/write register for selecting the auto-reload function and input clock. Upon reset, TMB is initialized to H'78. Bit 7—Auto-Reload Function Select (TMB7): Bit 7 selects whether timer B is used as an interval timer or auto-reload timer.
Page 244 9. Timers Timer Counter B (TCB) TCB7 TCB6 TCB5 TCB4 TCB3 TCB2 TCB1 TCB0 Initial value Read/Write TCB is an 8-bit read-only up-counter, which is incremented by internal clock or external event input. The clock source for input to this counter is selected by bits TMB2 to TMB0 in timer mode register B (TMB).
Page 245: Timer Operation
9. Timers 9.3.3 Timer Operation Interval timer Operation: When bit TMB7 in timer mode register B (TMB) is cleared to 0, timer B functions as an 8-bit interval timer. Upon reset, TCB is cleared to H'00 and bit TMB7 is cleared to 0, so up-counting and interval timing resume immediately.
Page 246: Timer B Operation States
9. Timers 9.3.4 Timer B Operation States Table 9.7 summarizes the timer B operation states. Table 9.7 Timer B Operation States Sub- Sub- Operation Mode Reset Active Sleep Watch active sleep Standby TCB Interval Reset Functions Functions Halted Halted Halted Halted Auto reload Reset...
Page 247 9. Timers Block Diagram Figure 9.3 shows a block diagram of timer C. φ TMIC φ IRRTC Legend: TMC: Timer mode register C TCC: Timer counter C TLC: Timer load register C IRRTC: Timer C overflow interrupt request flag PSS: Prescaler S Figure 9.3 Block Diagram of Timer C Pin Configuration...
Page 248: Register Descriptions
9. Timers Table 9.9 Timer C Registers Name Abbr. Initial Value Address Timer mode register C H'18 H'FFB4 Timer counter C H'00 H'FFB5 Timer load register C H'00 H'FFB5 9.4.2 Register Descriptions Timer Mode Register C (TMC) ⎯ ⎯ TMC7 TMC6 TMC5 TMC2...
Page 249 9. Timers Bits 4 and 3—Reserved Bits: Bits 4 and 3 are reserved; they are always read as 1, and cannot be modified. Bits 2 to 0—Clock Select (TMC2 to TMC0): Bits 2 to 0 select the clock input to TCC. For external clock counting, either the rising or falling edge can be selected.
Page 250: Timer Operation
9. Timers Timer Load Register C (TLC) TLC7 TLC6 TLC5 TLC4 TLC3 TLC2 TLC1 TLC0 Initial value Read/Write TLC is an 8-bit write-only register for setting the reload value of TCC. When a reload value is set in TLC, the same value is loaded into timer counter C (TCC) as well, and TCC starts counting up or down from that value.
Page 251 9. Timers Auto-Reload Timer Operation: Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a reload value is set in TLC, the same value is loaded into TCC, becoming the value from which TCC starts its count. After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to overflow (underflow).
Page 252: Timer C Operation States
9. Timers 9.4.4 Timer C Operation States Table 9.10 summarizes the timer C operation states. Table 9.10 Timer C Operation States Sub- Sub- Operation Mode Reset Active Sleep Watch active sleep Standby Interval Reset Functions Functions Halted Functions/ Functions/ Halted Halted* Halted* Auto...
Page 253 9. Timers Timer FH • 8-bit timer (clocked by timer FL overflow signals when timer F operates as a 16-bit timer). • Choice of four internal clocks (φ/32, φ/16, φ/4, φ/2). • Output from pin TMOFH is toggled by one compare match signal (the initial value of the toggle output can be set).
Page 254 9. Timers Block Diagram Figure 9.4 shows a block diagram of timer F. φ IRRTFL TCRF TCFL TMIF Toggle TMOFL Compare circuit circuit OCRFL TCFH Toggle Match TMOFH Compare circuit circuit OCRFH TCSRF Legend: IRRTFH TCRF: Timer control register F TCSRF: Timer control status register F TCFH:...
Page 255: Register Descriptions
9. Timers Pin Configuration Table 9.11 shows the timer F pin configuration. Table 9.11 Pin Configuration Name Abbr. Function Timer F event input TMIF Input Event input to TCFL Timer FH output TMOFH Output Timer FH toggle output Timer FL output TMOFL Output Timer FL toggle output...
Page 256 9. Timers TCF is a 16-bit read/write up-counter consisting of two cascaded 8-bit timer counters, TCFH and TCFL. TCF can be used as a 16-bit counter, with TCFH as the upper 8 bits and TCFL as the lower 8 bits of the counter, or TCFH and TCFL can be used as independent 8-bit counters. TCFH and TCFL can be read and written by the CPU, but in 16-bit mode, data transfer with the CPU takes place via a temporary register (TEMP).
Page 257 9. Timers 16-Bit Output Compare Register (OCRF) 8-Bit Output Compare Register (OCRFH) 8-Bit Output Compare Register (OCRFL) OCRF Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ← →← → OCRFH OCRFL OCRF is a 16-bit read/write output compare register consisting of two 8-bit read/write registers...
Page 258 9. Timers Timer Control Register F (TCRF) TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 Initial value Read/Write TCRF is an 8-bit write-only register. It is used to switch between 16-bit mode and 8-bit mode, to select among four internal clocks and an external clock, and to select the output level at pins TMOFH and TMOFL.
Page 259 9. Timers Bits 2 to 0—Clock Select L (CKSL2 to CKSL0): Bits 2 to 0 select the input to TCFL from four internal clock signals or external event input. Bit 2: CKSL2 Bit 1: CKSL1 Bit 0: CKSL0 Description External event (TMIF). Rising or falling edge is counted* (initial value) Internal clock: φ/32...
Page 260 9. Timers Bit 6—Compare Match Flag H (CMFH): Bit 6 is a status flag indicating a compare match between TCFH and OCRFH. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 6: CMFH Description Clearing condition: After reading CMFH = 1, cleared by writing 0 to CMFH...
Page 261: Interface With The Cpu
9. Timers Bit 2—Compare Match Flag L (CMFL): Bit 2 is a status flag indicating a compare match between TCFL and OCRFL. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 2: CMFL Description Clearing condition: After reading CMFL = 1, cleared by writing 0 to CMFL...
Page 262 9. Timers Upper byte write Internal data bus (H'AA) TEMP (H'AA) TCFH TCFL Lower byte write Internal data bus (H'55) TEMP (H'AA) TCFH TCFL (H'AA) (H'55) Figure 9.5 TCF Write Operation (CPU → TCF) Read Access: When the upper byte of TCF is read, the upper-byte data is sent directly to the CPU, and the lower byte is loaded into TEMP.
Page 263 9. Timers When the upper byte of OCRF is read, the upper-byte data is sent directly to the CPU. Next when the lower byte is read, the lower-byte data is sent directly to the CPU. Figure 9.6 shows a TCF read operation when H'AAFF is read from TCF. Upper byte read Internal data bus (H'AA)
Page 264: Timer Operation
9. Timers 9.5.4 Timer Operation Timer F is a 16-bit timer/counter that increments with each input clock. The value set in output compare register F is constantly compared with the value of timer counter F, and when they match the counter can be cleared, an interrupt can be requested, and the port output can be toggled. Timer F can also be used as two independent 8-bit timers.
Page 265 9. Timers TCF Count Timing: TCF is incremented by each pulse of the input clock (internal or external clock). • Internal clock The settings of bits CKSH2 to CKSH0 or bits CKSL2 to CKSL0 in TCRF select one of four internal clock signals divided from the system clock (φ), namely, φ/32, φ/16, φ/4, or φ/2.
Page 266: Application Notes
9. Timers Timer Overflow Flag (OVF) Set Timing: OVF is set to 1 when TCF overflows (goes from H'FFFF to H'0000). Compare Match Flag Set Timing: The compare match flags (CMFH or CMFL) are set to 1 when a compare match occurs between TCF and OCRF. A compare match signal is generated in the final state in which the values match (when TCF changes from the matching count value to the next value).
Page 267: Watchdog Timer [H8/3857F And H8/3854F Only]
9. Timers • 8-bit timer mode ⎯ TCFH and OCRFH The output at pin TMOFH toggles when there is a compare match. If the compare match signal occurs at the same time as new data is written in TCRF by a MOV instruction, however, the new value written in bit TOLH will be output at pin TMOFH.
Page 268 9. Timers An overflow period of 1 to 256 times the selected clock can be set. Block Diagram Figure 9.8 shows a block diagram of the watchdog timer. TCSRW φ Internal reset signal Legend: TCSRW : Timer control/status register W : Timer counter W : Prescaler S : Timer mode register W...
Page 269: Register Descriptions
9. Timers 9.6.2 Register Descriptions Timer Control/Status Register W (TCSRW) B6WI TCWE B4WI TCSRWE B2WI WDON BOWI WRST Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* Note: * Can be written to only when the write condition is satisfied. For the write conditions, see the individual bit descriptions.
Page 270 9. Timers Bit 4—Timer Control/Status Register W Write Enable (TCSRWE): Bit 4 controls writing of data to bits 2 and 0 of TCSRW. Bit 4: TCSRWE Description Writing to bits 2 and 0 is disabled (initial valu Writing to bits 2 and 0 is enabled Bit 3—Bit 2 Write Inhibit (B2WI): Bit 3 controls writing of data to bit 2 of TCSRW.
Page 271 9. Timers Bit 0—Watchdog Timer Reset (WRST): Bit 0 indicates that TCW has overflowed and an internal reset signal has been generated. The internal reset signal generated by the overflow resets the entire chip. WRST is cleared by a reset via the RES pin or by a 0 write by software. Bit 0: WRST Description [Clearing conditions] (initial value)
Page 272: Operation
9. Timers Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): Bits 2 to 0 select the clock to be input to TCW. Bit 2: Bit 1: Bit 0: CKS2 CKS1 CKS0 Description Internal clock: φ/64 Internal clock: φ/128 Internal clock: φ/256 Internal clock: φ/512 Internal clock: φ/1024...
Page 273: Watchdog Timer Operating Modes
9. Timers Example: With 30 ms overflow period when φ = 4 MHz (φ/8192 selected) 4 × 10 × 30 × 10 –3 = 14.6 8192 Therefore, 256 – 15 = 241 (H'F1) is set in TCW. TCW overflow H'FF H'F1 count value H'00...
Page 274 9. Timers Rev.3.00 Jul. 19, 2007 page 248 of 532 REJ09B0397-0300...
Page 275: Section 10 Serial Communication Interface
10. Serial Communication Interface Section 10 Serial Communication Interface 10.1 Overview The H8/3857 Group is provided with a two-channel serial communication interface (SCI), and the H8/3854 Group with a single-channel SCI. Table 10.1 summarizes the functions and features of the SCI channels. Table 10.1 Serial Communication Interface Functions Channel Functions...
Page 276: Sci1 (H8/3857 Group Only)
10. Serial Communication Interface 10.2 SCI1 (H8/3857 Group Only) 10.2.1 Overview Serial communication interface 1 (SCI1) performs synchronous serial transfer of 8-bit or 16-bit data. SCI1 is a function of the H8/3857 Group only, and is not provided in the H8/3854 Group. Features Features of SCI1 are as follows.
Page 277 10. Serial Communication Interface Block Diagram Figure 10.1 shows a block diagram of SCI1. φ SCR1 Transmit/receive SCSR1 control circuit Transfer bit counter SDRU SDRL IRRS1 Legend: SCR1: Serial control register 1 SCSR1: Serial control/status register 1 SDRU: Serial data register U SDRL: Serial data register L IRRS1:...
Page 278: Register Descriptions
10. Serial Communication Interface Pin Configuration Table 10.2 shows the SCI1 pin configuration. Table 10.2 Pin Configuration Name Abbr. Function SCI1 clock pin SCI1 clock input or output SCI1 data input pin Input SCI1 receive data input SCI1 data output pin Output SCI1 transmit data output Register Configuration...
Page 279 10. Serial Communication Interface Bits 7 and 6—Operation Mode Select 1, 0 (SNC1, SNC0): Bits 7 and 6 select the operation mode. Bit 7: SNC1 Bit 6: SNC0 Description 8-bit synchronous transfer mode (initial value) 16-bit synchronous transfer mode Continuous clock output mode Reserved Notes: 1.
Page 280 10. Serial Communication Interface Serial Control/Status Register 1 (SCSR1) ⎯ ⎯ ⎯ ⎯ ⎯ ORER Initial value ⎯ ⎯ ⎯ ⎯ Read/Write R/(W)* Note: Only a write of 0 for flag clearing is possible. SCSR1 is an 8-bit read/write register indicating operation status and error status. Upon reset, SCSR1 is initialized to H'80.
Page 281 10. Serial Communication Interface Bit 5—Overrun Error Flag (ORER): When an external clock is used, bit 5 indicates the occurrence of an overrun error. If a clock pulse is input after transfer completion, this bit is set to 1 indicating an overrun. If noise occurs during a transfer, causing an extraneous pulse to be superimposed on the normal serial clock, incorrect data may be transferred.
Page 282: Operation
10. Serial Communication Interface Data written to SDRU is output to SDRL starting from the least significant bit (LSB). This data is then replaced by LSB-first data input at pin SI , which is shifted in the direction from the most significant bit (MSB) toward the LSB.
Page 283 10. Serial Communication Interface to φ/2) selected in bits CKS2 to CKS0 is output continuously from pin SCK . When an external clock is used, pin SCK is the clock input pin. Data Transfer Format Figure 10.2 shows the data transfer format. Data is sent and received starting from the least significant bit, in LSB-first format.
Page 284 10. Serial Communication Interface Receiving: A receive operation is carried out as follows. • Set bits SI1 and SCK1 in PMR3 to 1 so that the respective pins function as SI and SCK • Clear bit SNC1 in SCR1 to 0, and set bit SNC0 to 1 or 0, designating 8- or 16-bit synchronous transfer mode.
Page 285: Interrupts
10. Serial Communication Interface When an external clock is used, data is transmitted and received in synchronization with the serial clock input at pin SCK . After data transmission and reception are complete, an overrun occurs if the serial clock continues to be input; no data is transmitted or received and the SCSR1 overrun error flag (bit ORER) is set to 1.
Page 286: Sci3
10. Serial Communication Interface 10.3 SCI3 10.3.1 Overview Serial communication interface 3 (SCI3) has both synchronous and asynchronous serial data communication capabilities. It also has a multiprocessor communication function for serial data communication among two or more processors. Features SCI3 features are listed below. •...
Page 287 10. Serial Communication Interface • There are six interrupt sources: transmit end, transmit data empty, receive data full, overrun error, framing error, and parity error. Block Diagram Figure 10.3 shows a block diagram of SCI3. External clock Internal clock (φ/64, φ/16, φ/4, φ) Baud rate generator Clock...
Page 288: Register Descriptions
10. Serial Communication Interface Pin Configuration Table 10.4 shows the SCI3 pin configuration. Table 10.4 Pin Configuration Name Abbr. Function SCI3 clock SCI3 clock input/output SCI3 receive data input Input SCI3 receive data input SCI3 transmit data output Output SCI3 transmit data output Register Configuration Table 10.5 shows the SCI3 internal register configuration.
Page 289 10. Serial Communication Interface The receive shift register (RSR) is for receiving serial data. Serial data is input in LSB (bit 0) order into RSR from pin RXD, converting it to parallel data. After each byte of data has been received, the byte is automatically transferred to the receive data register (RDR).
Page 290 10. Serial Communication Interface TSR cannot be read or written directly by the CPU. Transmit Data Register (TDR) TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 Initial value Read/Write The transmit data register (TDR) is an 8-bit register for holding transmit data. When SCI3 detects that the transmit shift register (TSR) is empty, it shifts transmit data written in TDR to TSR and starts serial data transmission.
Page 291 10. Serial Communication Interface Bit 6—Character Length (CHR): Bit 6 selects either 7 bits or 8 bits as the data length in asynchronous mode. In synchronous mode the data length is always 8 bits regardless of the setting here. Bit 6: CHR Description 8-bit data (initial value)
Page 292 10. Serial Communication Interface Bit 3—Stop Bit Length (STOP): Bit 3 selects 1 bit or 2 bits as the stop bit length in asynchronous mode. This setting is valid only in asynchronous mode. In synchronous mode a stop bit is not added, so this bit is ignored. Bit 3: STOP Description 1 stop bit...
Page 293 10. Serial Communication Interface Serial Control Register 3 (SCR3) MPIE TEIE CKE1 CKE0 Initial value Read/Write Serial control register 3 (SCR3) is an 8-bit register that controls SCI3 transmit and receive operations, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the serial clock source.
Page 294 10. Serial Communication Interface Bit 5—Transmit Enable (TE): Bit 5 enables or disables the start of a transmit operation. Bit 5: TE Description Transmit operation disabled (TXD is a general I/O port) (initial value) Transmit operation enabled (TXD is the transmit data pin) Notes: 1.
Page 295 10. Serial Communication Interface value of 1 is received, the receive data full interrupt (RXI) and receive error interrupt (ERI) are disabled and serial status register (SSR) flags RDRF, FER, and OER are not set. When the multiprocessor bit receives a 1, the MPBR bit of SSR is set to 1, MPIE is automatically cleared to 0, RXI and ERI interrupts are enabled (provided bits TIE and RIE in SCR3 are set to 1), and setting of the RDRF, FER, and OER flags is enabled.
Page 296 10. Serial Communication Interface Serial Status Register (SSR) TDRE RDRF TEND MPBR MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: Only 0 can be written for flag clearing. The serial status register (SSR) is an 8-bit register containing status flags for indicating SCI3 states, and containing the multiprocessor bits.
Page 297 10. Serial Communication Interface Bit 6—Receive Data Register Full (RDRF): Bit 6 is a status flag indicating whether there is receive data in RDR. Bit 6: RDRF Description Indicates there is no receive data in RDR (initial value) Clearing conditions: After reading RDRF = 1, cleared by writing 0 to RDRF.
Page 298 10. Serial Communication Interface Bit 4—Framing Error (FER): Bit 4 is a status flag indicating that a framing error has occurred during asynchronous receiving. Bit 4: FER Description Indicates that data receiving is in progress or has been completed (initial value) Clearing condition: After reading FER = 1, cleared by writing 0 to FER Indicates that a framing error occurred in data receiving...
Page 299 10. Serial Communication Interface Bit 2—Transmit End (TEND): Bit 2 is a status flag indicating that TDRE was set to 1 when the last bit of a transmitted character was sent. TEND is a read-only bit and cannot be modified directly.
Page 300 10. Serial Communication Interface Bit Rate Register (BRR) BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 Initial value Read/Write The bit rate register (BRR) is an 8-bit register which, together with the baud rate generator clock selected by bits CKS1 and CKS0 in the serial mode register (SMR), sets the transmit/receive bit rate.
Page 301 10. Serial Communication Interface OSC (MHz) 4.9152 7.3728 Bit Rate Error Error Error Error (bits/s) −0.26 +0.03 +0.70 +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 1200 +0.16 +0.16 2400 +0.16 +0.16 −2.34 4800 +0.16 −2.34 9600 +0.16 −2.34 ⎯ ⎯ ⎯...
Page 302 10. Serial Communication Interface OSC (MHz) 9.8304 Bit Rate Error Error (bits/s) −0.25 +0.31 +0.16 +0.16 +0.16 1200 +0.16 2400 +0.16 −1.36 4800 9600 +1.73 19200 +1.73 −1.70 31250 38400 +1.73 Notes: 1. Settings should be made so that error is within 1%. 2.
Page 303 10. Serial Communication Interface The meaning of n is shown in table 10.7. Table 10.7 Relation between n and Clock SMR Setting Clock CKS1 CKS0 φ φ/4 φ/16 φ/64 Table 10.8 shows the maximum bit rate for selected frequencies in asynchronous mode. Values in table 10.8 are for active (high-speed) mode.
Page 304 10. Serial Communication Interface Table 10.9 shows typical BRR settings in synchronous mode. Values in table 10.9 are for active (high-speed) mode. Table 10.9 Typical BRR Settings and Bit Rates (Synchronous Mode) OSC (MHz) Bit Rate (bits/s) ⎯ ⎯ ⎯ ⎯...
Page 305: Operation
10. Serial Communication Interface The meaning of n is shown in table 10.10. Table 10.10 Relation between n and Clock SMR Setting Clock CKS1 CKS0 φ φ/4 φ/16 φ/64 10.3.3 Operation SCI3 supports serial data communication in both asynchronous mode, where each character transferred is synchronized separately, and synchronous mode, where transfer is synchronized by clock pulses.
Page 306 10. Serial Communication Interface Synchronous Mode: • Transfer format: 8 bits • Overrun error can be detected when data is received. • Clock source: Choice of internal clocks or an external clock When an internal clock is selected: Operates on baud rate generator clock, and outputs a serial clock.
Page 307 10. Serial Communication Interface Table 10.12 SMR and SCR3 Settings and Clock Source Selection SCR3 Transmit/Receive Clock Bit 7: Bit 1: Bit 0: Clock CKE1 CKE0 Mode Source Pin SCK Function Asynchronous Internal I/O port (SCK function not used) mode Outputs clock with same frequency as bit rate External...
Page 308 10. Serial Communication Interface Continuous Transmit/Receive Operation Using Interrupts: Continuous transmit and receive operations are possible with SCI3, using the RXI or TXI interrupts. Table 10.13 explains this use of these interrupts. Table 10.13 Transmit/Receive Interrupts Interrupt Flag Interrupt Conditions Remarks RDRF When serial data is received normally...
Page 309: Operation In Asynchronous Mode
10. Serial Communication Interface TDR (next transmit data) ↓ (transmission complete, TSR (transmitting) next data transferred) ← TDRE = 0 TDRE (TXI requested if TIE = 1) Figure 10.5 TDRE Setting and TXI Interrupt TSR (transmitting) TSR (transmission end) ← TEND = 0 TEND (TEI requested if TEIE = 1)
Page 310 10. Serial Communication Interface Transmit/Receive Formats Figure 10.7 shows the general format for asynchronous serial communication. (LSB) (MSB) Start Parity Stop bit Mark Serial Transmit or receive data state data 1 bit 1 or 2 none 1 bit 7 or 8 bits bits One unit of data (character or frame) Figure 10.7 Data Format in Asynchronous Serial Communication Mode...
Page 311 10. Serial Communication Interface Table 10.14 Serial Communication Formats in Asynchronous Mode SMR Settings Serial Transfer Format and Frame Length STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data STOP 8-bit data STOP STOP 7-bit data STOP 7-bit data STOP STOP 7-bit data STOP...
Page 312 10. Serial Communication Interface Clock The clock source is determined by bit COM in SMR and bits CKE1 and CKE0 in serial control register 3 (SCR3). See table 10.12 for the settings. Either an internal clock source can be used to run the built-in baud rate generator, or an external clock source can be input at pin SCK When an external clock is input at pin SCK , it should have a frequency 16 times the desired bit...
Page 313 10. Serial Communication Interface Figure 10.9 shows a typical flow chart for SCI3 initialization. Start Clear TE and RE to 0 in SCR3 Select the clock in serial control register 3 Set bits CKE1 and CKE0 (SCR3). Other bits must be cleared to 0. If clock output is selected in asynchronous mode, a clock signal will be output as soon as CKE1 and CKE0 have been set.
Page 314 10. Serial Communication Interface Transmitting: Figure 10.10 shows a typical flow chart for data transmission. After SCI3 initialization, follow the procedure below. Start Read bit TDRE in SSR Read the serial status register (SRR), and after confirming that bit TDRE = 1, write transmit data in the transmit data register (TDR).
Page 315 10. Serial Communication Interface SCI3 operates as follows during data transmission. SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR). Then TDRE is set to 1 and transmission starts.
Page 316 10. Serial Communication Interface Start 1. Read bits OER, PER, and FER in the serial status Read bits OER, PER, and register (SSR) to FER in SSR determine if a receive error has occurred. OER + PER + If a receive error has FER = 1 occurred, receive error processing is executed.
Page 317 10. Serial Communication Interface SCI3 operates as follows when receiving serial data in asynchronous mode. SCI3 monitors the communication line, and when a start bit (0) is detected it performs internal synchronization and starts receiving. The communication format for data receiving is as outlined in table 10.14.
Page 318: Operation In Synchronous Mode
10. Serial Communication Interface Figure 10.13 shows a typical SCI3 data receive operation in asynchronous mode. Start Receive Parity Stop Start Receive Parity Stop Mark data data (idle state) Serial data 1 frame 1 frame RDRF LSI operation RXI request RDRF cleared Detects stop bit = 0 to 0...
Page 319 10. Serial Communication Interface Transmit/Receive Format Figure 10.14 shows the general communication data format for synchronous communication. Serial clock Don't Don't Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 care care 8 bits One unit of communication data (character or frame)
Page 320 10. Serial Communication Interface Data Transmit/Receive Operations SCI3 Initialization: Before transmitting or receiving data, follow the SCI3 initialization procedure explained under 10.3.4, SCI3 Initialization, and illustrated in figure 10.9. Transmitting: Figure 10.15 shows a typical flow chart for data transmission. After SCI3 initialization, follow the procedure below.
Page 321 10. Serial Communication Interface SCI3 operates as follows during data transmission in synchronous mode. SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR). Then TDRE is set to 1 and transmission starts.
Page 322 10. Serial Communication Interface Receiving: Figure 10.17 shows a typical flow chart for receiving data. After SCI3 initialization, follow the procedure below. Start 1. Read bit OER in the serial status register (SSR) Read bit OER in SSR to determine if an error has occurred. If an overrun error has occurred, overrun error processing is executed.
Page 323 10. Serial Communication Interface SCI3 operates as follows when receiving serial data in synchronous mode. SCI3 synchronizes internally with the input or output of the serial clock and starts receiving. Received data is set in RSR from LSB to MSB. After data has been received, SCI3 checks to confirm that the value of bit RDRF is 0 indicating that received data can be transferred from RSR to RDR.
Page 324 10. Serial Communication Interface Simultaneous Transmit/Receive: Figure 10.19 shows a typical flow chart for transmitting and receiving simultaneously. After SCI3 synchronization, follow the procedure below. Read the serial status register (SSR), Start and after confirming that bit TDRE = 1, write transmit data in the transmit data register (TDR).
Page 325: Multiprocessor Communication Function
10. Serial Communication Interface Notes: 1. To switch from transmitting to simultaneous transmitting and receiving, use the following procedure. • First confirm that TDRE and TEND are both set to 1 and that SCI3 has finished transmitting. Next clear TE to 0. Then set both TE and RE to 1. 2.
Page 326 10. Serial Communication Interface Transmitting processor Communication line Receiving Receiving Receiving Receiving processor A processor B processor C processor D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) (MPB = 0) ID-sending cycle Data-sending cycle (receiving processor...
Page 327 10. Serial Communication Interface Transmitting Multiprocessor Data: Figure 10.21 shows a typical flow chart for multiprocessor serial data transmission. After SCI3 initialization, follow the procedure below. Start Read bit TDRE in SSR Read the serial status register (SSR), and after confirming that bit TDRE = 1, set bit MPBT (multiprocessor bit transmit) in SSR to 0 or 1, then write transmit data in the TDRE = 1?
Page 328 10. Serial Communication Interface SCI3 operates as follows during data transmission using a multiprocessor format. SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR). Then TDRE is set to 1 and transmission starts.
Page 329 10. Serial Communication Interface Receiving Multiprocessor Data: Figure 10.23 shows a typical flow chart for receiving data using a multiprocessor format. After SCI3 initialization, follow the procedure below. Start Set bit MPIE in SCR3 to 1 Set bit MPIE in serial control register 3 (SCR3) to 1. Read bits OER and FER in SSR Read bits OER and FER in the serial status register (SSR) to determine if an error has occurred.
Page 330 10. Serial Communication Interface Figure 10.24 gives an example of data reception using a multiprocessor format. Start Receive Stop Start Receive Stop Mark data (ID1) data (data 1) (idle state) Serial data 1 frame 1 frame MPIE RDRF value LSI operation RXI request RDRF cleared to 0 No RXI request...
Page 331: Interrupts
10. Serial Communication Interface 10.3.7 Interrupts SCI3 has six interrupt sources: transmit end, transmit data empty, receive data full, and the three receive error interrupts (overrun error, framing error, and parity error). All share a common interrupt vector. Table 10.16 describes each interrupt. Table 10.16 SCI3 Interrupts Interrupt Description...
Page 332: Application Notes
10. Serial Communication Interface 10.3.8 Application Notes When using SCI3, attention should be paid to the following matters. Relation between Bit TDRE and Writing Data to TDR: Bit TDRE in the serial status register (SSR) is a status flag indicating that TDR does not contain new transmit data. TDRE is automatically cleared to 0 when data is written to TDR.
Page 333 10. Serial Communication Interface Sending a Mark or Break Signal: When TE is cleared to 0 the TXD pin becomes an I/O port, the level and direction (input or output) of which are determined by the PDR and PCR bits. This feature can be used to place the TXD pin in the mark state or send a break signal.
Page 334 10. Serial Communication Interface The receive margin in asynchronous mode can therefore be derived from the following equation. M = {(0.5 – 1/2N) – (D – 0.5) / N – (L – 0.5) F} × 100% ......Equation (1) M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 16) D: Clock duty cycle (D = 0.5 to 1) L: Frame length (L = 9 to 12)
Page 335 10. Serial Communication Interface Frame 1 Frame 2 Frame 3 Communica- Data 1 Data 2 Data 3 tion line RDRF Data 1 Data 2 RDR read RDR read At A , data 1 is read. At B , data 2 is read. Figure 10.26 Relationship between Data and RDR Read Timing To avoid the situation described above, after RDRF is confirmed to be 1, RDR should only be read once and should not be read twice or more.
Page 336 10. Serial Communication Interface 2. When an SCK function is switched from clock output to general input/output When stopping data transfer, a. Issue one instruction to clear bits TE and RE in SCR3 to 0 and to set bits CKE1 and CKE0 to 1 and 0, respectively.
Page 337: Section 11 14-Bit Pwm (H8/3857 Group Only)
11. 14-Bit PWM (H8/3857 Group Only) Section 11 14-Bit PWM (H8/3857 Group Only) 11.1 Overview The H8/3857 Group is provided with a 14-bit PWM (pulse width modulator), which can be used as a D/A converter by connecting a low-pass filter. The H8/3854 Group does not have this module.
Page 338: Pin Configuration
11. 14-Bit PWM (H8/3857 Group Only) 11.1.3 Pin Configuration Table 11.1 shows the output pin assigned to the 14-bit PWM. Table 11.1 Pin Configuration Name Abbr. Function PWM output pin Output Pulse-division PWM waveform output 11.1.4 Register Configuration Table 11.2 shows the register configuration of the 14-bit PWM. Table 11.2 Register Configuration Name Abbr.
Page 339: Pwm Data Registers U And L (Pwdru, Pwdrl)
11. 14-Bit PWM (H8/3857 Group Only) Bit 0—Clock Select 0 (PWCR0): Bit 0 selects the clock supplied to the 14-bit PWM. This bit is a write-only bit; it is always read as 1. Bit 0: PWCR0 Description ∗ = 2/φ). The conversion period is 16,384/φ, with a The input clock is φ/2 (t φ...
Page 340: Operation
11. 14-Bit PWM (H8/3857 Group Only) 11.3 Operation When using the 14-bit PWM, set the registers in the following sequence. 1. Set bit PWM in port mode register 1 (PMR1) to 1 so that pin P1 /PWM is designated for PWM output.
Page 341: Section 12 A/D Converter
12. A/D Converter Section 12 A/D Converter 12.1 Overview The H8/3857 Group and H8/3854 Group include a resistance-ladder-based successive- approximation analog-to-digital converter. The maximum number of analog input channels is eight in the H8/3857 Group and four in the H8/3854 Group. 12.1.1 Features The A/D converter has the following features.
Page 342: Block Diagram
12. A/D Converter 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the A/D converter. ADTRG A/D mode register A/D start Multiplexer register Com- Control logic parator – Reference voltage A/D result register IRRAD Notes: 1. AN to AN are functions of the H8/3857 Group only, and are not provided in the H8/3854 Group.
Page 343: Pin Configuration
12. A/D Converter 12.1.3 Pin Configuration Table 12.1 shows the A/D converter pin configuration. Table 12.1 Pin Configuration Name Abbr. Function Analog power supply pin* AV Input Power supply and reference voltage of analog part Analog ground pin* Input Ground and reference voltage of analog part Analog input pin 0* Input Analog input channel 0...
Page 344: Register Descriptions
12. A/D Converter 12.2 Register Descriptions 12.2.1 A/D Result Register (ADRR) ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write The A/D result register (ADRR) is an 8-bit read-only register for holding the results of analog-to- digital conversion.
Page 345 12. A/D Converter Bit 6—External Trigger Select (TRGE): Bit 6 enables or disables the start of A/D conversion by external trigger input. Bit 6: TRGE Description Disables start of A/D conversion by external trigger (initial value) Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG* Note: The external trigger (ADTRG) edge is selected by bit INTEG4 of the IRQ edge select...
Page 346: A/D Start Register (Adsr)
12. A/D Converter 12.2.3 A/D Start Register (ADSR) ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ADSF Initial value ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Read/Write The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D conversion.
Page 347: Operation
12. A/D Converter 12.3 Operation 12.3.1 A/D Conversion Operation The A/D converter operates by successive approximations, and yields its conversion result as 8-bit data. A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete.
Page 348: Interrupts
12. A/D Converter 12.4 Interrupts When A/D conversion ends (ADSF changes from 1 to 0), bit IRRAD in interrupt request register 2 (IRR2) is set to 1. A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt enable register 2 (IENR2).
Page 349 12. A/D Converter Figure 12.3 Typical A/D Converter Operation Timing Rev.3.00 Jul. 19, 2007 page 323 of 532 REJ09B0397-0300...
Page 350 12. A/D Converter Start Set A/D conversion speed and input channel Disable A/D conversion end interrupt Start A/D conversion Read ADSR ADSF = 0? Read ADRR data Perform A/D conversion? Figure 12.4 Flow Chart of Procedure for Using A/D Converter (1) (Polling by Software) Rev.3.00 Jul.
Page 351: Application Notes
12. A/D Converter Start Set A/D conversion speed and input channels Enable A/D conversion end interrupt Start A/D conversion A/D conversion end interrupt? Clear bit IRRAD to 0 in IRR2 Read ADRR data Perform A/D conversion? Figure 12.5 Flow Chart of Procedure for Using A/D Converter (2) (Interrupts Used) 12.6 Application Notes •...
Page 352 12. A/D Converter Rev.3.00 Jul. 19, 2007 page 326 of 532 REJ09B0397-0300...
Page 353: Section 13 Dot Matrix Lcd Controller (H8/3857 Group)
13. Dot Matrix LCD Controller (H8/3857 Group) Section 13 Dot Matrix LCD Controller (H8/3857 Group) 13.1 Overview The LCD controller has built-in display RAM, and performs dot matrix LCD display. One bit of display RAM data corresponds to illumination or non-illumination of one dot on the LCD panel, making possible displays with an extremely high degree of freedom.
Page 354: Block Diagram
13. Dot Matrix LCD Controller (H8/3857 Group) 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the LCD controller. COM17/ COM32/ COM16/ COM9/ SEG40 SEG1 SEG64 COM8 COM1 SEG56 SEG41 SEG57 Common/segment Common/segment Segment driver Common driver driver driver Level shifter Common counter Decoder...
Page 355: Pin Configuration
13. Dot Matrix LCD Controller (H8/3857 Group) 13.1.3 Pin Configuration Table 13.1 shows the pins assigned to the LCD controller. Table 13.1 Pin Configuration Pin Name Abbr. Function Common output pins COM1 to COM32 Output LCD common drive pins Segment output pins SEG1 to SEG64 Output LCD segment drive pins LCD bias setting pins...
Page 356: Register Configuration
13. Dot Matrix LCD Controller (H8/3857 Group) 13.1.4 Register Configuration The LCD controller has one index register and ten control registers, all of which are accessed via an I/O port interface. Except for the display data register (LR4), these registers cannot be read. The LCD controller register configuration is shown in table 13.2.
Page 357: Control Register 1 (Lr0)
13. Dot Matrix LCD Controller (H8/3857 Group) Bits 3 to 0—Index Register (IR3 to IR0): Bits 3 to 0 are used to select one of the LCD controller's ten control registers. The correspondence between the settings of IR3 to IR0 and the selected registers is shown in table 13.2.
Page 358 13. Dot Matrix LCD Controller (H8/3857 Group) Bit 2—Display Mode Select (SOB): Bit 2 selects either character display mode or graphic display mode. Bit 2: SOB Description Character display mode Bits 4 to 0 of one display memory data byte are output to the segment pins (initial value) Graphic display mode All bits in one display memory data byte are output to the segment pins...
Page 359: Control Register 2 (Lr1)
13. Dot Matrix LCD Controller (H8/3857 Group) 13.2.3 Control Register 2 (LR1) ⎯ ⎯ ⎯ DISP OPON ⎯ ⎯ ⎯ Initial value ⎯ ⎯ ⎯ Read/Write LR1 is an 8-bit write-only register that selects operation or halting of LCD display and the op-amp circuits, performs read-modify-write mode setting, and selects the address to be incremented in the display memory.
Page 360 13. Dot Matrix LCD Controller (H8/3857 Group) Bit 3—Read-Modify-Write Setting (RMW): Bit 3 selects whether display memory X or Y address incrementing is carried out after a write/read access, or only after a write access (read- modify-write mode). Bit 3: RMW Description Address is incremented after write/read access to display memory (initial value)
Page 361: Address Register (Lr2)
13. Dot Matrix LCD Controller (H8/3857 Group) 13.2.4 Address Register (LR2) Initial value Read/Write LR2 is an 8-bit write-only register that sets the display memory X- and Y-direction addresses accessed by the CPU. Upon reset, LR2 is initialized to H'00. Bits 7 to 5—X Address Setting (XA2 to XA0): Bits 7 to 5 set the display memory X-direction address.
Page 362: Frame Frequency Setting Register (Lr3)
13. Dot Matrix LCD Controller (H8/3857 Group) 13.2.5 Frame Frequency Setting Register (LR3) ⎯ ⎯ ⎯ ⎯ Initial value ⎯ ⎯ Read/Write LR3 is an 8-bit write-only register that sets the frame frequency. Upon reset, LR3 is initialized to H'00. Bits 7 and 6—Reserved Bits: Bits 7 and 6 are reserved;...
Page 363 13. Dot Matrix LCD Controller (H8/3857 Group) Table 13.3 Register Settings and Division Ratios Division Division Division Division Ratio r Ratio r Ratio r Ratio r 5 4 3 2 1 0 5 4 3 2 1 0 5 4 3 2 1 0 5 4 3 2 1 0 0 0 0 0 0 0 2 0 1 0 0 0 0 34...
Page 364: Display Data Register (Lr4)
13. Dot Matrix LCD Controller (H8/3857 Group) 13.2.6 Display Data Register (LR4) Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write LR4 is an 8-bit read/write register used to perform read/write access to the display memory specified by XA2 to XA0 and YA4 to YA0 in LR2. In a write to display memory, the write is performed directly to the display memory via this register.
Page 365: Blink Register (Lr6)
13. Dot Matrix LCD Controller (H8/3857 Group) 13.2.8 Blink Register (LR6) Initial value Read/Write LR6 is an 8-bit write-only register that specifies blink areas. An area is made to blink by writing 1 to the corresponding bit in this register. There are no restrictions on areas that can blink simultaneously, and the entire screen can be made to blink by writing 1 to all the bits.
Page 366: Blink End Line Register (Lr9)
13. Dot Matrix LCD Controller (H8/3857 Group) The possible settings are 0 to 31 for 1/32 duty, 0 to 15 for 1/16 duty, and 0 to 7 for 1/8 duty. Normal operation is not guaranteed if these ranges are exceeded. 13.2.10 Blink End Line Register (LR9) ⎯...
Page 367 13. Dot Matrix LCD Controller (H8/3857 Group) Bits 3 to 0—Contrast Control Setting (CCR3 to CCR0): Bits 3 to 0 specify the value of the contrast control resistance between the V and V1 levels. By adjusting the contrast control resistance between the V and V1 levels, it is possible to adjust the contrast of the LCD panel.
Page 368: Operation
13. Dot Matrix LCD Controller (H8/3857 Group) 13.3 Operation 13.3.1 System Overview The LCD controller operates at 1/32, 1/16, or 1/8 duty. The display size is a maximum of 40 × 32 dots (4 rows of 8 columns with a 5 × 8-dot font). As the LCD controller operates on the subclock to perform display control, the time, etc., can be constantly displayed.
Page 369: Cpu Interface
13. Dot Matrix LCD Controller (H8/3857 Group) 13.3.2 CPU Interface The LCD controller's registers are not included in the memory map shown in figure 2.16 (a). They are controlled from the CPU by means of chip-internal LCD pins DB7 to DB0, RS, R/W, and STRB, via chip-internal I/O ports 9 and A.
Page 370 13. Dot Matrix LCD Controller (H8/3857 Group) performed in the next cycle, DB7 to DB0 are set to input mode from the point at which R/W is cleared to 0, and the output is cleared. In either case, do not change RS or R/W at the fall of STRB. STRB DB7 to Data...
Page 371 13. Dot Matrix LCD Controller (H8/3857 Group) Examples of display data register (LR4) read/write access when read-modify-write is designated are shown below. [Set index register to display data register] • Port A set to output mode, RMW set to 1 MOV.W #H'0100,R1 MOV.W...
Page 372: Lcd Drive Pin Functions
13. Dot Matrix LCD Controller (H8/3857 Group) 13.3.3 LCD Drive Pin Functions Common/Segment Output Switching Among the LCD controller's LCD drive outputs, COM9 to COM32 and SEG64 to SEG41 are switched according to the display duty and display mode. The display duty is set by control register 1 (LR0) bits DDTY1 and DDTY0, and the display mode by bit SOB.
Page 373: Display Memory Configuration And Display
13. Dot Matrix LCD Controller (H8/3857 Group) Table 13.6 Pin Functions According to Display Mode and Display Duty Function SOB = 0 (Character Display Mode) SOB = 1 (Graphic Display Mode) Pin Name 1/8 Duty 1/16 Duty 1/32 Duty 1/8 Duty 1/16 Duty 1/32 Duty COM1 to COM8 COM1 to COM8 COM1 to...
Page 374 13. Dot Matrix LCD Controller (H8/3857 Group) COM1 COM2 SEG1 SEG3 SEG5 SEG2 SEG4 SEG40 Y address H'00 H'01 Display memory (MSB) (LSB) (1) SOB = 0 COM1 COM2 SEG1 SEG3 SEG5 SEG7 SEG40, SEG56, SEG2 SEG4 SEG6 SEG8 SEG64 Y address H'00 H'01...
Page 375: Display Data Output
13. Dot Matrix LCD Controller (H8/3857 Group) 13.3.5 Display Data Output The LCD controller has a character display mode (SOB = 0) in which only 5 bits of each display data byte can be output to perform efficient 5-dot × 8-dot character output, and a graphic display mode (SOB = 1) in which all the bits of a data byte can be output to perform efficient full-dot graphic display.
Page 376 13. Dot Matrix LCD Controller (H8/3857 Group) (1) Character display mode (SOB = 0) • 1/8 duty Display dots: 320 X address H'00 H'05 H'06 H'07 H'00 H'07 H'08 H'0F H'10 H'1F • 1/16 duty Display dots: 640 X address H'00 H'05 H'06...
Page 377 13. Dot Matrix LCD Controller (H8/3857 Group) • 1/32 duty Display dots: 1280 X address H'00 H'05 H'06 H'07 H'00 H'07 H'08 H'0F H'10 H'1F (2) Graphic display mode (SOB = 1) • 1/8 duty Display dots: 512 X address H'00 H'05 H'06...
Page 378 13. Dot Matrix LCD Controller (H8/3857 Group) • 1/16 duty Display dots: 896 X address H'00 H'05 H'06 H'07 H'00 H'07 H'08 H'0F H'10 H'1F • 1/32 duty Display dots: 1280 X address H'00 H'05 H'06 H'07 H'00 H'07 H'08 H'0F H'10 H'1F...
Page 379: Register And Display Memory Access
13. Dot Matrix LCD Controller (H8/3857 Group) 13.3.6 Register and Display Memory Access Register Access To access a register, RS is first cleared to 0 and the register number of the register to be accessed is set in the index register. Then RS is set to 1, enabling the specified register to be accessed. Some internal registers have nonexistent bits;...
Page 380 13. Dot Matrix LCD Controller (H8/3857 Group) X addres H'00 H'01 H'1F (1) Priority given to Y-direction data access (INC = 0) X address H'00 H'01 H'1F (2) Priority given to X-direction data access (INC = 1) Notes: Address register (LR2) bits XA2 to XA0 show the X address, and bits YA4 to YA0 show the Y address. X address operation (1) SOB = 0: Address becomes H'0 after H'7, regardless of the display duty.
Page 381 13. Dot Matrix LCD Controller (H8/3857 Group) Reading for Display The LCD controller's display RAM is of the dual-port type, with accesses from the CPU and reads for LCD display independent of each other. This allows flexible interfacing. STRB Input data H'02 [n, m] H'04...
Page 382: Scroll Function
13. Dot Matrix LCD Controller (H8/3857 Group) Read-Modify-Write Mode In the normal state, the X or Y address is incremented after both read and write accesses to the display memory. In read-modify-write mode, the address is incremented only after a write, and remains the same after a read.
Page 383 13. Dot Matrix LCD Controller (H8/3857 Group) Display start line = 0 Y address Y address H' 00 H' 00 H' 01 H' 01 H' 02 H' 02 H' 03 H' 03 H' 04 H' 04 H' 05 H' 05 H' 06 H' 06 H' 07...
Page 384: Blink Function
13. Dot Matrix LCD Controller (H8/3857 Group) 13.3.8 Blink Function Dot Matrix Display Blinking The LCD controller can perform blinking display in any area. With an 80 Hz frame frequency, the display goes on and off in a cycle of approximately 1.6 seconds. To set a blink area, in the horizontal direction the line unit is specified by means of the blink start line register (LR8) and blink end line register (LR9), while in the vertical direction a 5-bit unit (SOB = 0) or 8-bit unit (SOB = 1) is set in the blink register (LR6).
Page 385 13. Dot Matrix LCD Controller (H8/3857 Group) Display start line = H'0 Display start line = H'4 Blink start line = H'0 Blink start line = H'4 Blink end line = H'7 Blink end line = H'7 Figure 13.11 Blinking during Display Scrolling (SOB = 0, 1/16 Duty) Rev.3.00 Jul.
Page 386: Module Standby Mode
13. Dot Matrix LCD Controller (H8/3857 Group) 13.3.9 Module Standby Mode The LCD controller has a module standby function that enables low power consumption to be achieved. In module standby mode, the built-in step-up circuit and op-amps are halted, and segment and common outputs go to the V (display-off state) level.
Page 387: 13.3.10 Power-On And Power-Off Procedures
13. Dot Matrix LCD Controller (H8/3857 Group) 13.3.10 Power-On and Power-Off Procedures As the LCD controller incorporates a complete power supply circuit, the procedures shown in figure 13.13 must be followed when powering on and off. Failure to follow these procedures may result in an abnormal display.
Page 388: 13.3.11 Power Supply Circuit
13. Dot Matrix LCD Controller (H8/3857 Group) 13.3.11 Power Supply Circuit The LCD controller has a built-in 2X or 3X step-up circuit for LCD drive. In standby mode, the power supply circuit is automatically turned off after a maximum of two subclock cycles, and the power consumption of the step-up circuit falls to zero.
Page 389: 13.3.12 Lcd Drive Power Supply Voltages
13. Dot Matrix LCD Controller (H8/3857 Group) • By changing step-up circuit reference voltage V The step-up circuit voltage level can be varied by changing step-up circuit reference voltage External Power Supply • When an external power supply is input to V V1 to V5 can be generated by inputting an external power supply to V , and using the built-in op-amps by setting the OPON bit in control register 2 (LR1) to 1.
Page 390 13. Dot Matrix LCD Controller (H8/3857 Group) 1 frame Line selection period COM1 COM2 COM32 SEG1 SEG40 Not selected Selected Figure 13.14 LCD Drive Power Supply Waveforms (1/32 Duty) Rev.3.00 Jul. 19, 2007 page 364 of 532 REJ09B0397-0300...
Page 391: 13.3.13 Lcd Voltage Generation Circuit
13. Dot Matrix LCD Controller (H8/3857 Group) 13.3.13 LCD Voltage Generation Circuit When Using External Power Supply and Built-In Op-Amps When the built-in step-up circuit is not used, and the LCD drive voltages are supplied directly from an external power supply, connections should be made as shown in figure 13.15. The V input level must be between V and 7.0 V.
Page 392 13. Dot Matrix LCD Controller (H8/3857 Group) OPON = 1 V1OUT V2OUT SEG1 to SEG40 V3OUT Control COM32/SEG41 circuit to COM9/SEG64 V4OUT COM1 to COM8 V5OUT 0.1 to 0.5 μF PWR = 0 C1 + – Step-up C2 + circuit –...
Page 393 13. Dot Matrix LCD Controller (H8/3857 Group) When Using External Power Supply but Not Using Built-In Op-Amps When the built-in step-up circuit and op-amps are not used, and the LCD drive voltages are supplied directly from an external power supply, connections should be made as shown in figure 13.16.
Page 394 13. Dot Matrix LCD Controller (H8/3857 Group) When Using Built-In Step-Up Circuit and Op-Amps When the built-in step-up circuit is used, connections should be made as shown in figure 13.17 (1) (3X step-up) or figure 13.17 (2) (2X step-up). The LCD controller includes bleeder resistances that generate levels V1 to V5, and voltage follower op-amp circuits.
Page 395 13. Dot Matrix LCD Controller (H8/3857 Group) OPON = 1 V1OUT V2OUT SEG1 to SEG40 V3OUT Control COM32/SEG41 circuit to COM9/SEG64 V4OUT COM1 to COM8 V5OUT 0.1 to 0.5 μF PWR = 1 C1 + 0.47 to 1 μF – Step-up C2 + circuit...
Page 396 13. Dot Matrix LCD Controller (H8/3857 Group) OPON = 1 V1OUT V2OUT SEG1 to SEG40 V3OUT Control COM32/SEG41 circuit to COM9/SEG64 V4OUT COM1 to COM8 V5OUT 0.1 to 0.5 μF PWR = 1 C1 + – Step-up 0.47 to 1 μF C2 + circuit –...
Page 397 13. Dot Matrix LCD Controller (H8/3857 Group) When Using Built-In Step-Up Circuit and Bleeder Resistances If the drive capability of the built-in op-amps is insufficient for the size of the LCD panel, the V1 to V5 levels can be supplied from external bleeder resistances. In this case, clear the OPON bit in control register 2 (LR1) to 0 to turn the op-amps off.
Page 398 13. Dot Matrix LCD Controller (H8/3857 Group) OPON = 0 V1OUT V2OUT SEG1 to SEG40 V3OUT Control COM32/SEG41 circuit to COM9/SEG64 V4OUT COM1 to COM8 V5OUT PWR = 1 C1 + 0.47 to 1 μF – Step-up C2 + circuit 0.47 to 1 μF –...
Page 399: 13.3.14 Contrast Control Circuit
13. Dot Matrix LCD Controller (H8/3857 Group) 13.3.14 Contrast Control Circuit Contrast control can be performed by software (electronic control function) by controlling the LCD drive voltage (the potential difference between V and V1) by means of the contrast control register (LRA).
Page 400: 13.3.15 Lcd Drive Bias Selection Circuit
13. Dot Matrix LCD Controller (H8/3857 Group) Table 13.8 Contrast Control Ranges Bias LCD Drive Voltage: V Contrast Control Range • LCD drive voltage 0.758 × (V ) ≤ V ≤ 0.980 × (V – V – V adjustment range: 5 ×...
Page 401: Section 14 Dot Matrix Lcd Controller (H8/3854 Group)
14. Dot Matrix LCD Controller (H8/3854 Group) Section 14 Dot Matrix LCD Controller (H8/3854 Group) 14.1 Overview The LCD controller has built-in display RAM, and performs dot matrix LCD display. One bit of display RAM data corresponds to illumination or non-illumination of one dot on the LCD panel, making possible displays with an extremely high degree of freedom.
Page 402: Block Diagram
14. Dot Matrix LCD Controller (H8/3854 Group) 14.1.2 Block Diagram Figure 14.1 shows a block diagram of the LCD controller. COM9 COM1 SEG40 SEG1 COM16 COM8 Segment driver Common driver Common Decoder counter Latch 2 Latch 1 Display line counter 40 ×...
Page 403: Pin Configuration
14. Dot Matrix LCD Controller (H8/3854 Group) 14.1.3 Pin Configuration Table 14.1 shows the pins assigned to the LCD controller. Table 14.1 Pin Configuration Pin Name Abbr. Function Common output pins COM1 to COM16 Output LCD common drive pins Segment output pins SEG1 to SEG40 Output LCD segment drive pins LCD drive power supply...
Page 404: Register Descriptions
14. Dot Matrix LCD Controller (H8/3854 Group) 14.2 Register Descriptions 14.2.1 Index Register (IR) ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initial value ⎯ ⎯ ⎯ ⎯ ⎯ Read/Write IR is an 8-bit write-only register that selects one of the LCD controller's five control registers. IR is selected when RS is 0.
Page 405: Control Register 2 (Lr1)
14. Dot Matrix LCD Controller (H8/3854 Group) Bit 5—Module Standby (LSBY): Bit 5 is the module standby setting bit. When LSBY is set to 1, the LCD controller enters standby mode. At this time, bits DISP, LPS1, and LPS0 in LR1 are reset.
Page 406 14. Dot Matrix LCD Controller (H8/3854 Group) Bit 6—LCD Operation Setting (DISP): Bit 6 selects operation or halting of the LCD display. When the LSBY bit in LR0 is set to 1, DISP is cleared. Bit 6: DISP Description LCD is turned off. All LCD outputs go to the V level (initial value) LCD is turned on...
Page 407: Address Register (Lr2)
14. Dot Matrix LCD Controller (H8/3854 Group) Bit 1—Increment Address Select (INC): Bit 1 selects either the X address or the Y address as the address to be incremented after the display memory access specified by the RMW bit. The selected address is cleared after a display memory access with the maximum value for the valid display data area;...
Page 408: Frame Frequency Setting Register (Lr3)
14. Dot Matrix LCD Controller (H8/3854 Group) valid display data area. When INC is 1 and the value in XA2 to XA0 is H'4, the address is incremented after the access specified by RMW. 14.2.5 Frame Frequency Setting Register (LR3) ⎯...
Page 409: Display Data Register (Lr4)
14. Dot Matrix LCD Controller (H8/3854 Group) Table 14.3 Register Settings, Division Ratios, and Frame Frequencies at Each Display Duty Display Duty 1/N 1/16 Subclock Frequency f (kHz) 32.768 38.4 32.768 38.4 Division ratio r Frame Frequency f (Hz) 2048.0 2400.0 1024.0 1200.0...
Page 410: Operation
14. Dot Matrix LCD Controller (H8/3854 Group) 14.3 Operation 14.3.1 System Overview The LCD controller operates at 1/16 or 1/8 duty. The display size is a maximum of 40 × 16 dots. As the LCD controller operates on the subclock to perform display control, the time, etc., can be constantly displayed.
Page 411: Cpu Interface
14. Dot Matrix LCD Controller (H8/3854 Group) 14.3.2 CPU Interface The LCD controller's registers are not included in the memory map shown in figure 2.16 (b). They are controlled from the CPU by means of chip-internal LCD pins DB7 to DB0, RS, R/W, and STRB, via chip-internal I/O ports 9 and A.
Page 412 14. Dot Matrix LCD Controller (H8/3854 Group) performed in the next cycle, DB7 to DB0 are set to input mode from the point at which R/W is cleared to 0, and the output is cleared. In either case, do not change RS or R/W at the fall of STRB. STRB DB7 to Data...
Page 413 14. Dot Matrix LCD Controller (H8/3854 Group) Examples of display data register (LR4) read/write access when read-modify-write is designated are shown below. [Set index register to display data register] • Port A set to output mode, RMW set to 1 MOV.W #H'0100,R1 MOV.W...
Page 414: Lcd Drive Pin Functions
14. Dot Matrix LCD Controller (H8/3854 Group) 14.3.3 LCD Drive Pin Functions Common/Segment Output The display duty is set by control register 1 (LR0) bits DDTY1. • 1/8 duty (DDTY1 = 1) Common outputs: COM1 to COM8 Segment outputs: SEG1 to SEG40 Note: COM9 to COM16 output common signal non-selection waveforms •...
Page 415: Display Memory Configuration And Display
14. Dot Matrix LCD Controller (H8/3854 Group) 14.3.4 Display Memory Configuration and Display The LCD controller includes 40 × 16-bit bit-mapped display memory. As the display memory configuration, an 8-bit × 5 X-direction combination can be selected, while the Y-direction configuration is 16 bits.
Page 416: Display Data Output
14. Dot Matrix LCD Controller (H8/3854 Group) 14.3.5 Display Data Output The relationship between the LCD controller display duty and output pins is shown in figure 14.5. (1) 1/8 duty Display dots: 320 X address (2) 1/16 duty Display dots: 640 X address H'00 H'07...
Page 417: Register And Display Memory Access
14. Dot Matrix LCD Controller (H8/3854 Group) 14.3.6 Register and Display Memory Access Register Access To access a register, RS is first cleared to 0 and the register number of the register to be accessed is set in the index register. Then RS is set to 1, enabling the specified register to be accessed. Some internal registers have nonexistent bits;...
Page 418 14. Dot Matrix LCD Controller (H8/3854 Group) X addres (1) Priority given to Y-direction data access (INC = 0) X address (2) Priority given to X-direction data access (INC = 1) Notes: Address register (LR2) bits XA2 to XA0 show the X address, and bits YA3 to YA0 show the Y address. X address operation Address becomes H'0 after H'4, regardless of the duty.
Page 419 14. Dot Matrix LCD Controller (H8/3854 Group) Reading for Display Reads for LCD display are performed asynchronously with respect to accesses by the CPU. However, since simultaneous accesses would corrupt data in the RAM, arbitration is carried out within the chip. Basically, accesses by the CPU have priority, and reads for display are performed in the intervals between CPU accesses.
Page 420 14. Dot Matrix LCD Controller (H8/3854 Group) Read-Modify-Write Mode In the normal state, the X or Y address is incremented after both read and write accesses to the display memory. In read-modify-write mode, the address is incremented only after a write, and remains the same after a read.
Page 421: Module Standby Mode
14. Dot Matrix LCD Controller (H8/3854 Group) 14.3.7 Module Standby Mode The LCD controller has a module standby function that enables low power consumption to be achieved. In module standby mode, the current supply to the built-in bleeder resistances is halted, and segment and common outputs go to the V (display-off state) level.
Page 422: Power-On And Power-Off Procedures
14. Dot Matrix LCD Controller (H8/3854 Group) 14.3.8 Power-On and Power-Off Procedures As the LCD controller incorporates a complete power supply circuit, the procedures shown in figure 14.10 must be followed when powering on and off. Failure to follow these procedures may result in an abnormal display.
Page 423: 14.3.10 Lcd Drive Power Supply Voltages
14. Dot Matrix LCD Controller (H8/3854 Group) External Power Supply • When external power supply is input directly to pins V1OUT through V5OUT A power supply can be applied directly to V1OUT, V2OUT, V3OUT, V4OUT, and V5OUT from an external source by clearing bits LPS0 and LPS1 to 0 in control register 2 (LR1) to halt the power supply to the built-in bleeder resistance circuit.
Page 424 14. Dot Matrix LCD Controller (H8/3854 Group) 1 frame Line selection period COM1 COM2 COM16 SEG1 SEG40 Not selected Selected Figure 14.11 LCD Drive Power Supply Waveforms (1/16 Duty) Rev.3.00 Jul. 19, 2007 page 398 of 532 REJ09B0397-0300...
Page 425: 14.3.11 Lcd Voltage Generation Circuit
14. Dot Matrix LCD Controller (H8/3854 Group) 14.3.11 LCD Voltage Generation Circuit When Using Internal Power Supply and Built-In Bleeder Resistances The LCD controller includes bleeder resistances that generate levels V1 to V5. For the LCD drive power supply, drive can be performed using the internal power supply and V , or using an external supply.
Page 426 14. Dot Matrix LCD Controller (H8/3854 Group) When Using External Power Supply and Built-In Bleeder Resistances When an external power supply is supplied from V1OUT and the built-in bleeder resistances are used, clear LPS1 to 0 and set LPS0 to 1 in control register 2 (LR1), and make the connections shown in figure 14.13.
Page 427 14. Dot Matrix LCD Controller (H8/3854 Group) When Using External Power Supply and Bleeder Resistances If the drive capability of the built-in bleeder resistance is insufficient for the size of the LCD panel, the V1 to V5 levels can be supplied from external bleeder resistances. In this case, clear the LPS1 and LPS0 bits in control register 2 (LR1) to 0, and make the connections shown in figure 14.14.
Page 428: 14.3.12 Lcd Drive Bias Selection Circuit
14. Dot Matrix LCD Controller (H8/3854 Group) 14.3.12 LCD Drive Bias Selection Circuit The ideal bias value that gives the best contrast is calculated using the equation shown below. If drive is performed at a bias value lower than the optimum, contrast will deteriorate, but the LCD drive voltage (the potential difference between V1 and V ) can be kept low.
Page 429: Section 15 Electrical Characteristics (H8/3857 Group)
15. Electrical Characteristics (H8/3857 Group) Section 15 Electrical Characteristics (H8/3857 Group) 15.1 H8/3855, H8/3856, and H8/3857 Absolute Maximum Ratings (Standard Specifications) Table 15.1 shows the absolute maximum ratings. Table 15.1 Absolute Maximum Ratings Item Symbol Value Unit Notes Power supply voltage –0.3 to +7.0 Analog power supply voltage –0.3 to +7.0...
Page 430: H8/3855, H8/3856, And H8/3857 Electrical Characteristics (Standard Specifications)
15. Electrical Characteristics (H8/3857 Group) 15.2 H8/3855, H8/3856, and H8/3857 Electrical Characteristics (Standard Specifications) 15.2.1 Power Supply Voltage and Operating Range The power supply voltage and operating range of the H8/3855, H8/3856, and H8/3857 are indicated by the shaded region in the figures below. (1) Power Supply Voltage vs.
Page 431 15. Electrical Characteristics (H8/3857 Group) (2) Power Supply Voltage vs. Operating Frequency Range 19.200 16.384 9.600 8.192 4.800 4.096 • Active mode (high speed) • Subactive mode • Sleep mode (except CPU) • Subsleep mode (except CPU) • Watch mode (except CPU) 625.0 500.0 312.5...
Page 432: Dc Characteristics
15. Electrical Characteristics (H8/3857 Group) 15.2.2 DC Characteristics Table 15.2 shows the DC characteristics of the H8/3855, H8/3856, and H8/3857. Table 15.2 DC Characteristics of H8/3855, H8/3856, and H8/3857 (1) = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C*...
Page 433 15. Electrical Characteristics (H8/3857 Group) Values Item Symbol Applicable Pins Test Conditions Unit Notes ⎯ Input low –0.3 voltage ⎯ to P1 = 4.0 V to 5.5 V –0.3 0.3 V to P2 to P3 to P4 ⎯ –0.3 0.2 V to P5 to PB ⎯...
Page 434 15. Electrical Characteristics (H8/3857 Group) Values Item Symbol Applicable Pins Test Conditions Unit Notes ⎯ Sleep mode = 5 V, mA * SLEEP current = 10 MHz dissipation ⎯ μA Subactive = 3.3 V, (with 2X mode current LCD on, step-up) dissipation 32-kHz...
Page 435 15. Electrical Characteristics (H8/3857 Group) Notes: 1. Pin states during current measurement Mode Internal State Pins LCD Power Supply Oscillator Pins Active mode (high Operates = 6.0 V System clock oscillator: Crystal and medium speed) Subclock oscillator: Pin X Sleep mode Only timer operates = 6.0 V Subactive mode...
Page 436 15. Electrical Characteristics (H8/3857 Group) Table 15.3 DC Characteristics of H8/3855, H8/3856, and H8/3857 (2) = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C* including subactive mode, unless otherwise specified. Values Item Symbol Applicable Pins...
Page 437: Ac Characteristics
15. Electrical Characteristics (H8/3857 Group) 15.2.3 AC Characteristics Table 15.4 shows the control signal timing, and tables 15.5 and 15.6 show the serial interface timing, of the H8/3855, H8/3856, and H8/3857. Table 15.4 Control Signal Timing of H8/3855, H8/3856, and H8/3857 = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV...
Page 438 15. Electrical Characteristics (H8/3857 Group) Values Applicable Reference Item Symbol Pins Test Conditions Unit Figure ⎯ ⎯ External subclock 0.4/fx Figure 15.2 high width ⎯ ⎯ External subclock 0.4/fx Figure 15.2 low width ⎯ ⎯ External subclock 100.0 Figure 15.2 rise time ⎯...
Page 439 15. Electrical Characteristics (H8/3857 Group) Table 15.5 Serial Interface (SCI1) Timing of H8/3855, H8/3856, and H8/3857 = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C*, unless otherwise specified.
Page 440 15. Electrical Characteristics (H8/3857 Group) Table 15.6 Serial Interface (SCI3) Timing of H8/3855, H8/3856, and H8/3857 = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C*, unless otherwise specified.
Page 441: A/D Converter Characteristics
15. Electrical Characteristics (H8/3857 Group) 15.2.4 A/D Converter Characteristics Table 15.7 shows the A/D converter characteristics of the H8/3855, H8/3856, and H8/3857. Table 15.7 A/D Converter Characteristics of H8/3855, H8/3856, and H8/3857 = 3.0 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C* , unless otherwise specified.
Page 442: Lcd Characteristics
15. Electrical Characteristics (H8/3857 Group) 15.2.5 LCD Characteristics Table 15.8 shows the LCD characteristics, and table 15.9 shows the step-up circuit characteristics, of the H8/3855, H8/3856, and H8/3857. Table 15.8 LCD Characteristics of H8/3855, H8/3856, and H8/3857 = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0.0 V, T...
Page 443 15. Electrical Characteristics (H8/3857 Group) Table 15.9 Step-Up Circuit Characteristics of H8/3855, H8/3856, and H8/3857 = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C* including subactive mode, unless otherwise specified. Values Applicable Item...
Page 444: Flash Memory Characteristics
15. Electrical Characteristics (H8/3857 Group) 15.2.6 Flash Memory Characteristics Table 15.10 shows the flash memory characteristics. Table 15.10 Flash Memory Characteristics Conditions: V = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, V = AV = 0.0 V, T = 0°C to +75°C (program/erase operating temperature range) Test...
Page 445: Operation Timing
15. Electrical Characteristics (H8/3857 Group) 15.3 Operation Timing Figures 15.1 to 15.8 show timing diagrams. Figure 15.1 System Clock Input Timing Figure 15.2 Subclock Input Timing Figure 15.3 RES Pin Low Width Timing to IRQ to WKP ADTRG, TMIB, TMIC, TMIF Figure 15.4 Input Timing Figure 15.5 UD Pin Minimum Transition Width Timing...
Page 446 15. Electrical Characteristics (H8/3857 Group) Scyc or V or V SCKL SCKH SCKf SCKr Note: * Output timing reference levels Output high = 2.0 V Output low = 0.8 V Load conditions are shown in figure 15.10. Figure 15.6 SCI1 Input/Output Timing SCKW Scyc Figure 15.7 SCK3 Input Clock Timing...
Page 447 15. Electrical Characteristics (H8/3857 Group) Scyc or V or V (transmit data) (receive data) Note: * Output timing reference levels Output high = 2.0 V Output low = 0.8 V Load conditions are shown in figure 15.10. Figure 15.8 SCI3 Input/Output Timing in Synchronous Mode (2X step-up) (3X step-up) 1 μF...
Page 448: Output Load Circuit
15. Electrical Characteristics (H8/3857 Group) 15.4 Output Load Circuit 2.4 kΩ LSI Chip Output pin 12 kΩ 30 pF Figure 15.10 Output Load Conditions 15.5 Usage Note Although both the F-ZTAT and mask ROM versions fully meet the electrical specifications listed in this manual, there may be differences in the actual values of the electrical characteristics, operating margins, noise margins, and so forth, due to differences in the fabrication process, the on-chip ROM, and the layout patterns.
Page 449: Section 16 Electrical Characteristics (H8/3854 Group)
16. Electrical Characteristics (H8/3854 Group) Section 16 Electrical Characteristics (H8/3854 Group) 16.1 H8/3852, H8/3853, and H8/3854 Absolute Maximum Ratings (Standard Specifications) Table 16.1 shows the absolute maximum ratings. Table 16.1 Absolute Maximum Ratings Item Symbol Value Unit Notes Power supply voltage –0.3 to +7.0 Programming voltage (FWE) –0.3 to V...
Page 450: H8/3852, H8/3853, And H8/3854 Electrical Characteristics (Standard Specifications)
16. Electrical Characteristics (H8/3854 Group) 16.2 H8/3852, H8/3853, and H8/3854 Electrical Characteristics (Standard Specifications) 16.2.1 Power Supply Voltage and Operating Range The power supply voltage and operating range of the H8/3852, H8/3853, and H8/3854 are indicated by the shaded region in the figures below. (1) Power Supply Voltage vs.
Page 451 16. Electrical Characteristics (H8/3854 Group) (2) Power Supply Voltage vs. Operating Frequency Range 19.200 16.384 9.600 8.192 4.800 4.096 2.7* 2.7* • Active mode (high speed) • Subactive mode • Sleep mode (except CPU) • Subsleep mode (except CPU) • Watch mode (except CPU) 625.0 Notes: 1.
Page 452: Dc Characteristics
16. Electrical Characteristics (H8/3854 Group) 16.2.2 DC Characteristics Table 16.2 shows the DC characteristics of the H8/3852, H8/3853, and H8/3854. Table 16.2 DC Characteristics of H8/3852, H8/3853, and H8/3854 (1) = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3853, and H8/3854, = 3.0 V to 5.5 V of H8/3854F, V = 0.0 V, T = –20°C to +75°C*...
Page 453 16. Electrical Characteristics (H8/3854 Group) Values Item Symbol Applicable Pins Test Conditions Unit Notes ⎯ Input low –0.3 voltage ⎯ to P1 = 4.0 V to 5.5 V –0.3 0.3 V , P1 to P2 to P4 ⎯ –0.3 0.2 V to P5 to PB ⎯...
Page 454 16. Electrical Characteristics (H8/3854 Group) Values Item Symbol Applicable Pins Test Conditions Unit Notes ⎯ Active mode Active mode 10.0 15.0 mA * OPE1 current (high speed) dissipation = 5 V, = 10 MHz A/D not used ⎯ ⎯ Active mode 16.5 mA * OPE3...
Page 455 16. Electrical Characteristics (H8/3854 Group) Values Item Symbol Applicable Pins Test Conditions Unit Notes ≤ ≤ ⎯ Program/ 0°C 70°C mA * FLASH erase current = 12 MHz dissipation ⎯ ⎯ RAM data retaining voltage Notes: 1. Pin states during current measurement Mode Internal State Pins...
Page 456 16. Electrical Characteristics (H8/3854 Group) Table 16.3 DC Characteristics of H8/3852, H8/3853, and H8/3854 (2) = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3853, and H8/3854, = 3.0 V to 5.5 V of H8/3854F, V = 0.0 V, T = –20°C to +75°C* , including subactive mode,...
Page 457: Ac Characteristics
16. Electrical Characteristics (H8/3854 Group) 16.2.3 AC Characteristics Table 16.4 shows the control signal timing, and table 16.5 shows the serial interface timing, of the H8/3852, H8/3853, and H8/3854. Table 16.4 Control Signal Timing of H8/3852, H8/3853, and H8/3854 = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3853, and H8/3854, = 3.0 V to 5.5 V of H8/3854F, V = 0.0 V, T = –20°C to +75°C*...
Page 458 16. Electrical Characteristics (H8/3854 Group) Values Applicable Reference Item Symbol Pins Test Conditions Unit Figure ⎯ ⎯ External subclock 0.4/fx Figure 16.2 high width ⎯ ⎯ External subclock 0.4/fx Figure 16.2 low width ⎯ ⎯ External subclock 100.0 Figure 16.2 rise time ⎯...
Page 459 16. Electrical Characteristics (H8/3854 Group) Table 16.5 Serial Interface (SCI3) Timing of H8/3852, H8/3853, and H8/3854 = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3853, and H8/3854, = 3.0 V to 5.5 V of H8/3854F, V = 0.0 V, T = –20°C to +75°C*, unless otherwise specified.
Page 460: A/D Converter Characteristics
16. Electrical Characteristics (H8/3854 Group) 16.2.4 A/D Converter Characteristics Table 16.6 shows the A/D converter characteristics of the H8/3852, H8/3853, and H8/3854. Table 16.6 A/D Converter Characteristics of H8/3852, H8/3853, and H8/3854 = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3853, and H8/3854, = 3.0 V to 5.5 V of H8/3854F, V = 0.0 V, T = –20°C to +75°C*, unless otherwise specified.
Page 461: Lcd Characteristics
16. Electrical Characteristics (H8/3854 Group) 16.2.5 LCD Characteristics Table 16.7 shows the LCD characteristics of the H8/3852, H8/3853, and H8/3854. Table 16.7 LCD Characteristics of H8/3852, H8/3853, and H8/3854 = 2.7 V to 5.5 V of the mask ROM version of H8/3852, H8/3853, and H8/3854, = 3.0 V to 5.5 V of H8/3854F, V = 0.0 V, T = –20°C to +75°C*...
Page 462: Flash Memory Characteristics
16. Electrical Characteristics (H8/3854 Group) 16.2.6 Flash Memory Characteristics Table 16.8 shows the flash memory characteristics. Table 16.8 Flash Memory Characteristics Conditions: V = 4.5 V to 5.5 V, V = 0.0 V, T = 0°C to +75°C (program/erase operating temperature range) Test Item Symbol...
Page 463: Operation Timing
16. Electrical Characteristics (H8/3854 Group) 16.3 Operation Timing Figures 16.1 to 16.6 show timing diagrams. Figure 16.1 System Clock Input Timing Figure 16.2 Subclock Input Timing Figure 16.3 RES Pin Low Width Timing , IRQ , IRQ , IRQ to WKP , ADTRG, TMIB, TMIF Figure 16.4 Input Timing...
Page 464: Output Load Circuit
16. Electrical Characteristics (H8/3854 Group) Scyc or V or V (transmit data) (receive data) Note: * Output timing reference levels Output high = 2.0 V Output low = 0.8 V Load conditions are shown in figure 16.7. Figure 16.6 SCK3 Input/Output Timing in Synchronous Mode 16.4 Output Load Circuit 2.4 kΩ...
Page 465: Usage Note
16. Electrical Characteristics (H8/3854 Group) 16.5 Usage Note Although both the F-ZTAT and mask ROM versions fully meet the electrical specifications listed in this manual, there may be differences in the actual values of the electrical characteristics, operating margins, noise margins, and so forth, due to differences in the fabrication process, the on-chip ROM, and the layout patterns.
Page 466 16. Electrical Characteristics (H8/3854 Group) Rev.3.00 Jul. 19, 2007 page 440 of 532 REJ09B0397-0300...
Page 467: Appendix A Cpu Instruction Set
Appendix A CPU Instruction Set Appendix A CPU Instruction Set Instructions Operation Notation Symbol Description Rd8/16 General register (destination) (8 or 16 bits) Rs8/16 General register (source) (8 or 16 bits) Rn8/16 General register (8 or 16 bits) Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR...
Page 468 Appendix A CPU Instruction Set Condition Code Notation Symbol Description Modified according to the instruction result Not fixed (value not guaranteed) Always cleared to 0 ⎯ Not affected by the instruction execution result Rev.3.00 Jul. 19, 2007 page 442 of 532 REJ09B0397-0300...
Page 469 Appendix A CPU Instruction Set Table A.1 Instruction Set Addressing Mode/ Instruction Length (Bytes) Condition Code Mnemonic Operation I H N Z V C B #xx:8 → Rd8 ⎯ ⎯ 0 ⎯ 2 MOV.B #xx:8, Rd B Rs8 → Rd8 ⎯...
Page 470 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (Bytes) Condition Code Mnemonic Operation I H N Z V C W SP–2 → SP ⎯ ⎯ 0 ⎯ 6 PUSH Rs Rs16 → @SP B Rd8+#xx:8 → Rd8 ⎯ ADD.B #xx:8, Rd B Rd8+Rs8 →...
Page 471 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (Bytes) Condition Code Mnemonic Operation I H N Z V C B Rd16÷Rs8 → Rd16 (RdH: ⎯ ⎯ (5) (6) ⎯ ⎯ 14 DIVXU.B Rs, Rd remainder, RdL: quotient) B Rd8∧#xx:8 → Rd8 ⎯...
Page 472 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (Bytes) Condition Code Mnemonic Operation I H N Z V C B (#xx:3 of Rd8) ← 1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2 BSET #xx:3, Rd B (#xx:3 of @Rd16) ← 1 ⎯...
Page 473 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (Bytes) Condition Code Mnemonic Operation I H N Z V C B (#xx:3 of Rd8) → C ⎯ ⎯ ⎯ ⎯ ⎯ BLD #xx:3, Rd B (#xx:3 of @Rd16) → C ⎯...
Page 474 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (Bytes) Condition Code Mnemonic Operation Branching I H N Z V C Condition B C⊕(#xx:3 of @Rd16) → C ⎯ ⎯ ⎯ ⎯ ⎯ BIXOR #xx:3, @Rd B C⊕(#xx:3 of @aa:8) → C ⎯...
Page 475 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (Bytes) Condition Code Mnemonic Operation I H N Z V C ⎯ SP–2 → SP ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8 JSR @@aa:8 PC → @SP PC ← @aa:8 ⎯ PC ← @SP 2 ⎯...
Page 476: Operation Code Map
Appendix A CPU Instruction Set Operation Code Map Table A.2 is an operation code map. It shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
Page 477 Appendix A CPU Instruction Set Table A.2 Operation Code Map Rev.3.00 Jul. 19, 2007 page 451 of 532 REJ09B0397-0300...
Page 478: Number Of Execution States
Appendix A CPU Instruction Set Number of Execution States The tables here can be used to calculate the number of states required for instruction execution. Table A.4 indicates the number of states required for each cycle (instruction fetch, data read/write, etc.) in instruction execution, and table A.3 indicates the number of cycles of each type occurring in each instruction.
Page 479 Appendix A CPU Instruction Set Table A.3 Number of Cycles in Each Instruction Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module ⎯ Instruction fetch Branch address read Stack operation Byte data access 2 or 3* ⎯ Word data access Internal operation Note: Depends on which on-chip module is accessed.
Page 480 Appendix A CPU Instruction Set Table A.4 Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDS.W #1, Rd ADDS.W #2, Rd ADDX...
Page 481 Appendix A CPU Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BCLR BCLR Rn, @Rd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 2 BILD BILD #xx:3, Rd BILD #xx:3, @Rd...
Page 482 Appendix A CPU Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BSET BSET Rn, @aa:8 BSR d:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BTST BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd...
Page 483 Appendix A CPU Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.B @Rs, Rd MOV.B @(d:16, Rs), MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, MOV.B Rs, @–Rd MOV.B Rs, @aa:8...
Page 484 Appendix A CPU Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ROTXL ROTXL.B Rd ROTXR ROTXR.B Rd SHAL SHAL.B Rd SHAR SHAR.B Rd SHLL SHLL.B Rd SHLR SHLR.B Rd SLEEP SLEEP STC CCR, Rd...
Page 485: Appendix B Internal I/O Registers
Appendix B Internal I/O Registers Appendix B Internal I/O Registers Register Addresses B.1.1 H8/3857 Group Addresses Bit Names Address Register Module (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'80 —...
Page 486 Appendix B Internal I/O Registers Bit Names Address Register Module (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'9C H'9D H'9E H'9F ⎯ ⎯ H'A0 SCR1 SNC1 SNC0 CKS3 CKS2 CKS1 CKS0...
Page 487 Appendix B Internal I/O Registers Bit Names Address Register Module (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'B9 TCFL TCFL7 TCFL6 TCFL5 TCFL4 TCFL3 TCFL2 TCFL1 TCFL0 Timer F H'BA OCRFH OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0...
Page 488 Appendix B Internal I/O Registers Bit Names Address Register Module (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'DA I/O ports H'DB H'DC PDR9 ⎯ ⎯ ⎯ ⎯ H'DD PDRA H'DE PDRB...
Page 489 Appendix B Internal I/O Registers Bit Names Address Register Module (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'FA H'FB H'FC H'FD H'FE H'FF Legend: SCI1: Serial communication interface 1 SCI3: Serial communication interface 3 Notes: 1.
Page 490: H8/3854 Group Addresses
Appendix B Internal I/O Registers B.1.2 H8/3854 Group Addresses Bit Names Address Register Module (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name ⎯ ⎯ H'80 Flash FLMCR1 memory ⎯ ⎯...
Page 491 Appendix B Internal I/O Registers Bit Names Address Register Module (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'A0 H'A1 H'A2 H'A3 H'A4 H'A5 H'A6 H'A7 H'A8 STOP CKS1 CKS0 SCI3 H'A9...
Page 492 Appendix B Internal I/O Registers Bit Names Address Register Module (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'C2 H'C3 ⎯ ⎯ H'C4 TRGE converter H'C5 ADRR ADR7 ADR6 ADR5 ADR4 ADR3...
Page 493 Appendix B Internal I/O Registers Bit Names Address Register Module (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name ⎯ ⎯ ⎯ H'E4 PCR1 PCR1 PCR1 PCR1 PCR1 PCR1 I/O ports H'E5 PCR2 PCR2...
Page 494: Register Descriptions
Appendix B Internal I/O Registers Register Descriptions Register Register Address to which the Name of acronym name register is mapped on-chip supporting module TMC—Timer mode register C H'B4 Timer C numbers Initial bit ⎯ ⎯ TMC7 TMC6 TMC5 TMC2 TMC1 TMC0 values Initial value...
Page 495 Appendix B Internal I/O Registers FLMCR1—Flash memory control register 1 H'80 Flash memory (On-chip flash memory version only) ⎯ ⎯ ⎯* Initial value ⎯ ⎯ Read/Write Program Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 Erase Erase mode cleared Transition to erase mode...
Page 496 Appendix B Internal I/O Registers FLMCR2—Flash memory control register 2 H'81 Flash memory (On-chip flash memory version only) ⎯ ⎯ ⎯ ⎯ ⎯ FLER Initial value ⎯ ⎯ ⎯ ⎯ ⎯ Read/Write Program setup Program setup cleared Program setup [Setting condition] When FWE = 1 and SWE = 1 Erase setup Erase setup cleared...
Page 497 Appendix B Internal I/O Registers EBR—Erase block register H'83 Flash memory (On-chip flash memory version only) ⎯ Initial value ⎯ Read/Write Flash memory erase blocks Block (Size) Addresses EB0 (1 kbyte) H'0000 to H'03FF EB1 (1 kbyte) H'0400 to H'07FF EB2 (1 kbyte) H'0800 to H'0BFF EB3 (1 kbyte)
Page 498 Appendix B Internal I/O Registers MDCR—Mode control register H'89 Flash memory (On-chip flash memory version only) ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ TSDS2 TSDS1 ⎯* ⎯* Initial value ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Read/Write Test pin monitor bits Note: * Determined by the TEST and TEST2 pins. SYSCR3—System control register 3 H'8F Flash memory...
Page 499 Appendix B Internal I/O Registers TCSRW—Timer control/status register W H'90 Flash memory (On-chip flash memory version only) B6WI TCWE B4WI TCSRWE B2WI WDON B0WI WRST Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* Watchdog timer reset [Clearing conditions] • Reset by RES pin •...
Page 500 Appendix B Internal I/O Registers TCW—Timer counter W H'91 Flash memory (On-chip flash memory version only) TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1 TCW0 Initial value Read/Write Count value TMW—Timer mode register W H'92 Flash memory (On-chip flash memory version only) ⎯...
Page 501 Appendix B Internal I/O Registers SCR1—Serial control register 1 H'A0 SCI1 (H8/3857 Group only) ⎯ ⎯ SNC1 SNC0 CKS3 CKS2 CKS1 CKS0 Initial value Read/Write Clock Select (CKS2 to CKS0) Serial Clock Cycle Bit 2 Bit 1 Bit 0 Synchronous Prescaler φ...
Page 502 Appendix B Internal I/O Registers SCSR1—Serial control/status register 1 H'A1 SCI1 (H8/3857 Group only) ⎯ ⎯ ⎯ ⎯ ⎯ ORER Initial value ⎯ ⎯ ⎯ ⎯ ⎯ Read/Write R/(W) Start flag Read Indicates that transfer is stopped Write Invalid Read Indicates transfer in progress Write Starts a transfer operation...
Page 503 Appendix B Internal I/O Registers SDRU—Serial data register U H'A2 SCI1 (H8/3857 Group only) SDRU7 SDRU6 SDRU5 SDRU4 SDRU3 SDRU2 SDRU1 SDRU0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write Used to set transmit data and store receive data 8-bit transfer mode: Not used 16-bit transfer mode:...
Page 504 Appendix B Internal I/O Registers SMR—Serial mode register H'A8 SCI3 STOP CKS1 CKS0 Initial value Read/Write Clock select 0, 1 φ clock φ/4 clock Multiprocessor mode φ/16 clock 0 Multiprocessor communication function disabled φ/64 clock 1 Multiprocessor communication function enabled Stop bit length 0 1 stop bit 1 2 stop bits...
Page 505 Appendix B Internal I/O Registers SCR3—Serial control register 3 H'AA SCI3 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock enable Bit 1 Bit 0 Description CKE1 CKE0 Communication Mode Clock Source SCK Pin Function Asynchronous Internal clock I/O port Synchronous Internal clock Serial clock output Asynchronous...
Page 506 Appendix B Internal I/O Registers TDR—Transmit data register H'AB SCI3 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 Initial value Read/Write Data to be transferred to TSR Rev.3.00 Jul. 19, 2007 page 480 of 532 REJ09B0397-0300...
Page 507 Appendix B Internal I/O Registers SSR—Serial status register H'AC SCI3 TDRE RDRF TEND MPBR MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit receive Multiprocessor bit transmit 0 Indicates reception of data in which the multiprocessor bit is 0 0 The multiprocessor bit in transmit data is 0 1 Indicates reception of data in which the multiprocessor bit is 1 1 The multiprocessor bit in transmit data is 1...
Page 508 Appendix B Internal I/O Registers RDR—Receive data register H'AD SCI3 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 Initial value Read/Write TMA—Timer mode register A H'B0 Timer A TMA7 TMA6 TMA5 — TMA3 TMA2 TMA1 TMA0 Initial value Read/Write — Clock output select Internal clock select φ/32...
Page 509 Appendix B Internal I/O Registers TCA—Timer counter A H'B1 Timer A TCA7 TCA6 TCA5 TCA4 TCA3 TCA0 TCA2 TCA1 Initial value Read/Write Count value TMB—Timer mode register B H'B2 Timer B TMB7 — — — — TMB2 TMB1 TMB0 Initial value Read/Write —...
Page 510 Appendix B Internal I/O Registers TCB—Timer counter B H'B3 Timer B TCB7 TCB6 TCB5 TCB4 TCB3 TCB0 TCB2 TCB1 Initial value Read/Write Count value TLB—Timer load register B H'B3 Timer B TLB7 TLB6 TLB5 TLB4 TLB3 TLB2 TLB1 TLB0 Initial value Read/Write Reload value Rev.3.00 Jul.
Page 511 Appendix B Internal I/O Registers TMC—Timer mode register C H'B4 Timer C (H8/3857 Group only) ⎯ ⎯ TMC7 TMC6 TMC5 TMC2 TMC1 TMC0 Initial value ⎯ ⎯ Read/Write Clock select φ/8192 Internal clock: φ/2048 Internal clock: φ/512 Internal clock: Auto-reload function select φ/64 Internal clock: 0 Interval timer function selected...
Page 512 Appendix B Internal I/O Registers TLC—Timer load register C H'B5 Timer C (H8/3857 Group only) TLC7 TLC6 TLC5 TLC4 TLC3 TLC2 TLC1 TLC0 Initial value Read/Write Reload value TCRF—Timer control register F H'B6 Timer F TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0...
Page 513 Appendix B Internal I/O Registers TCSRF—Timer control/status register F H'B7 Timer F OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL Initial value Read/Write R/(W) R/(W) R/(W) R/(W) Timer overflow interrupt enable L 0 TCFL overflow interrupt disabled 1 TCFL overflow interrupt enabled Compare match flag L 0 [Clearing condition] After reading CMFL = 1, cleared by writing 0 to CMFL...
Page 514 Appendix B Internal I/O Registers TCFH—8-bit timer counter FH H'B8 Timer F TCFH7 TCFH6 TCFH5 TCFH4 TCFH3 TCFH0 TCFH2 TCFH1 Initial value Read/Write Count value TCFL—8-bit timer counter FL H'B9 Timer F TCFL7 TCFL6 TCFL5 TCFL4 TCFL3 TCFL2 TCFL1 TCFL0 Initial value Read/Write Count value...
Page 515 Appendix B Internal I/O Registers AMR—A/D mode register H'C4 A/D converter ⎯ ⎯ TRGE Initial value ⎯ ⎯ Read/Write Channel select Bit 3 Bit 2 Bit 1 Bit 0 Analog input channel No channel selected Reserved External trigger select 0 Disables start of A/D conversion by external trigger 1 Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG Clock select...
Page 516 Appendix B Internal I/O Registers ADRR—A/D result register H'C5 A/D converter ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write A/D conversion result ADSR—A/D start register H'C6 A/D converter ⎯ ⎯...
Page 517 Appendix B Internal I/O Registers PMR1—Port mode register 1 H'C8 I/O ports ⎯ IRQ2 * PWM * IRQ3 IRQ1 TMOFH TMOFL TMOW Initial value ⎯ Read/Write P1 /TMOW pin function switch 0 Functions as P1 I/O pin 1 Functions as TMOW output pin P1 /TMOFL pin function switch 0 Functions as P1 I/O pin 1 Functions as TMOFL output pin...
Page 518 Appendix B Internal I/O Registers PMR2—Port mode register 2 H'C9 I/O ports ⎯ ⎯ ⎯ ⎯ POF1 * UD * IRQ0 IRQ4 Initial value ⎯ ⎯ Read/Write P2 /IRQ /ADTRG pin function switch 0 Functions as P2 I/O pin 1 Functions as IRQ /ADTRG input pin P2 /UD pin function switch 0 Functions as P2 I/O pin 1 Functions as UD input pin...
Page 519 Appendix B Internal I/O Registers PMR3—Port mode register 3 H'CA I/O ports (H8/3857 Group only) ⎯ ⎯ ⎯ ⎯ ⎯ SCK1 Initial value ⎯ ⎯ ⎯ ⎯ ⎯ Read/Write P3 /SCK pin function switch 0 Functions as P3 I/O pin 1 Functions as SCK I/O pin P3 /SI pin function switch 0 Functions as P3 I/O pin...
Page 520 Appendix B Internal I/O Registers PMR5—Port mode register 5 H'CC I/O ports Initial value Read/Write P5 /WKP pin function switch 0 Functions as P5 I/O pin 1 Functions as WKP input pin PWCR—PWM control register H'D0 14-bit PWM (H8/3857 Group only) ⎯...
Page 521 Appendix B Internal I/O Registers PWDRL—PWM data register L H'D2 14-bit PWM (H8/3857 Group only) PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 Initial value Read/Write Lower 8 bits of data for generating PWM waveform PDR1—Port data register 1 H'D4 I/O ports Initial value Read/Write...
Page 522 Appendix B Internal I/O Registers PDR4—Port data register 4 H'D7 I/O ports ⎯ ⎯ ⎯ ⎯ Initial value Undefined ⎯ ⎯ ⎯ ⎯ Read/Write PDR5—Port data register 5 H'D8 I/O ports Initial value Read/Write PDR9—Port data register 9 H'DC I/O ports Initial value Read/Write PDRA—Port data register A...
Page 523 Appendix B Internal I/O Registers PUCR1—Port pull-up control register 1 H'E0 I/O ports PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 PUCR1 Initial value Read/Write Note: * PUCR1 , PUCR1 , and PUCR1 are functions of the H8/3857 Group only. In the H8/3854 Group these bits are reserved, and must always be cleared to 0. PUCR3—Port pull-up control register 3 H'E1 I/O ports...
Page 524 Appendix B Internal I/O Registers PCR2—Port control register 2 H'E5 I/O ports PCR2 PCR2 PCR2 PCR2 PCR2 PCR2 PCR2 PCR2 Initial value Read/Write Port 2 input/output select 0 Input pin 1 Output pin PCR3—Port control register 3 H'E6 I/O ports (H8/3857 Group only) PCR3 PCR3...
Page 525 Appendix B Internal I/O Registers PCR5—Port control register 5 H'E8 I/O ports PCR5 PCR5 PCR5 PCR5 PCR5 PCR5 PCR5 PCR5 Initial value Read/Write Port 5 input/output select 0 Input pin 1 Output pin PCR9—Port control register 9 H'EC I/O ports PCR9 PCR9 PCR9...
Page 526 Appendix B Internal I/O Registers SYSCR1—System control register 1 H'F0 System control ⎯ ⎯ ⎯ SSBY STS2 STS1 STS0 LSON Initial value ⎯ ⎯ ⎯ Read/Write Low speed on flag 0 The CPU operates on the system clock (φ) 1 The CPU operates on the subclock (φ Standby timer select 2 to 0 Wait time = 8,192 states Wait time = 16,384 states...
Page 527 Appendix B Internal I/O Registers SYSCR2—System control register 2 H'F1 System control ⎯ ⎯ ⎯ NESEL DTON MSON Initial value ⎯ ⎯ ⎯ Read/Write Medium speed on flag Subactive mode clock select φ /8 0 Operates in active (high-speed) mode φ...
Page 528 Appendix B Internal I/O Registers IEGR—IRQ edge select register H'F2 System control ⎯ ⎯ ⎯ IEG2 * IEG4 IEG3 IEG1 IEG0 Initial value ⎯ ⎯ ⎯ Read/Write IRQ edge select 0 Falling edge of IRQ pin input is detected 1 Rising edge of IRQ pin input is detected IRQ edge select 0 Falling edge of IRQ /TMIB pin input is detected 1 Rising edge of IRQ /TMIB pin input is detected...
Page 529 Appendix B Internal I/O Registers IENR1—Interrupt enable register 1 H'F3 System control IENS1 * IEN2 * IENTA IENWP IEN4 IEN3 IEN1 IEN0 Initial value Read/Write IRQ to IRQ interrupt enable 0 Disables interrupt request IRQ Enables interrupt request IRQ Note: n = 4 to 0 Wakeup interrupt enable 0 Disables interrupt requests from WKP to WKP Enables interrupt requests from WKP to WKP...
Page 530 Appendix B Internal I/O Registers IENR2—Interrupt enable register 2 H'F4 System control ⎯ ⎯ IENTC * IENDT IENAD IENTFH IENTFL IENTB Initial value Read/Write Timer B interrupt enable 0 Disables timer B interrupts 1 Enables timer B interrupts Timer C interrupt enable 0 Disables timer C interrupts 1 Enables timer C interrupts Timer FL interrupt enable...
Page 531 Appendix B Internal I/O Registers IRR1—Interrupt request register 1 H'F6 System control ⎯ IRRTA IRRS1 IRRI4 IRRI3 IRRI2 IRRI1 IRRI0 Initial value ⎯ Read/Write IRQ to IRQ interrupt request flag 0 [Clearing conditions] When IRRI4 = 1, it is cleared by writing 0 When 0 is written to IRRI4 when IRRI4 = 1 The same also applies to IRRI3—IRRI0 1 [Setting conditions]...
Page 532 Appendix B Internal I/O Registers IRR2—Interrupt request register 2 H'F7 System control ⎯ ⎯ IRRDT IRRAD IRRTFH IRRTFL IRRTC IRRTB Initial value ⎯ ⎯ Read/Write Timer B interrupt request flag 0 [Clearing condition] When IRRTB = 1, it is cleared by writing 0 1 [Setting condition] When the timer B counter overflows from H'FF to H'00...
Page 533 Appendix B Internal I/O Registers IWPR—Wakeup interrupt request register H'F9 System control IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Initial value Read/Write Wakeup interrupt request flag 0 [Clearing condition] When IWPFn = 1, it is cleared by writing 0 1 [Setting condition] When pin WKP is set to interrupt input and a falling signal edge is detected Note: n = 7 to 0...
Page 534: Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams Block Diagram of Port 1 SBY (low level during reset and in standby mode) Internal data bus PUCR1 PMR1 PDR1 PCR1 n – 4 Timer B module TMIB (P1 Legend: Timer C module PDR1:...
Page 535 Appendix C I/O Port Block Diagrams PWM module Internal data bus PUCR1 PMR1 PDR1 PCR1 Legend: PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Figure C.1 (b) Port 1 Block Diagram (Pin P1 : Function of H8/3857 Group Only) Rev.3.00 Jul.
Page 536 Appendix C I/O Port Block Diagrams Internal data bus PUCR1 PDR1 PCR1 Legend: PDR1: Port data register 1 PCR1: Port control register 1 PUCR1: Port pull-up control register 1 Figure C.1 (c) Port 1 Block Diagram (Pin P1 : Function of H8/3857 Group Only) Rev.3.00 Jul.
Page 537 Appendix C I/O Port Block Diagrams Timer F module TMOFH (P1 ) TMOFL (P1 ) Internal data bus PUCR1 PMR1 PDR1 PCR1 Legend: PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Note: n = 2 or 1 Figure C.1 (d) Port 1 Block Diagram (Pins P1...
Page 538 Appendix C I/O Port Block Diagrams Timer A module TMOW Internal data bus PUCR1 PMR1 PDR1 PCR1 Legend: PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Figure C.1 (e) Port 1 Block Diagram (Pin P1 Rev.3.00 Jul.
Page 539: Block Diagram Of Port 2
Appendix C I/O Port Block Diagrams Block Diagram of Port 2 Internal data bus PMR4 PDR2 PCR2 Legend: PDR2: Port data register 2 PCR2: Port control register 2 PMR4: Port mode register 4 Notes: H8/3857 Group: n = 7 to 2 H8/3854 Group: n = 7 to 1 Figure C.2 (a) Port 2 Block Diagram (Pins P2...
Page 540 Appendix C I/O Port Block Diagrams Internal data bus PMR4 PMR2 PDR2 PCR2 Timer C module Legend: PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 PMR4: Port mode register 4 Figure C.2 (b) Port 2 Block Diagram (Pin P2 : H8/3857 Group) Rev.3.00 Jul.
Page 541 Appendix C I/O Port Block Diagrams Internal data bus PMR4 PMR2 PDR2 PCR2 A/D converter module Legend: PDR2: Port data register 2 ADTRG PCR2: Port control register 2 PMR2: Port mode register 2 PMR4: Port mode register 4 Figure C.2 (c) Port 2 Block Diagram (Pin P2 Rev.3.00 Jul.
Page 542: Block Diagram Of Port 3 (H8/3857 Group Only)
Appendix C I/O Port Block Diagrams Block Diagram of Port 3 (H8/3857 Group Only) PUCR3 PDR3 PCR3 Legend: PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3 Note: n = 7 to 3 Figure C.3 (a) Port 3 Block Diagram (Pins P3 to P3 : Functions of H8/3857 Group Only)
Page 543 Appendix C I/O Port Block Diagrams SCI1 module PMR2 Internal data bus PUCR3 PMR3 PDR3 PCR3 Legend: PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PMR2: Port mode register 2 PUCR3: Port pull-up control register 3 Figure C.3 (b) Port 3 Block Diagram (Pin P3 : Function of H8/3857 Group Only) Rev.3.00 Jul.
Page 544 Appendix C I/O Port Block Diagrams PUCR3 PMR3 PDR3 PCR3 SCI1 module Legend: PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C.3 (c) Port 3 Block Diagram (Pin P3 : Function of H8/3857 Group Only) Rev.3.00 Jul.
Page 545 Appendix C I/O Port Block Diagrams SCI1 module EXCK SCKO SCKI PUCR3 PMR3 PDR3 PCR3 Legend: PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C.3 (d) Port 3 Block Diagram (Pin P3 : Function of H8/3857 Group Only) Rev.3.00 Jul.
Page 546: Block Diagram Of Port 4
Appendix C I/O Port Block Diagrams Block Diagram of Port 4 Internal data bus PMR2 Legend: PMR2: Port mode register 2 Figure C.4 (a) Port 4 Block Diagram (Pin P4 SCI3 module PDR4 Internal data bus PCR4 Legend: PDR4: Port data register 4 PCR4: Port control register 4 Figure C.4 (b) Port 4 Block Diagram (Pin P4...
Page 547 Appendix C I/O Port Block Diagrams SCI3 module PDR4 PCR4 Legend: PDR4: Port data register 4 PCR4: Port control register 4 Figure C.4 (c) Port 4 Block Diagram (Pin P4 Rev.3.00 Jul. 19, 2007 page 521 of 532 REJ09B0397-0300...
Page 548 Appendix C I/O Port Block Diagrams SCI3 module SCKIE SCKOE SCKO SCKI PDR4 PCR4 Legend: PDR4: Port data register 4 PCR4: Port control register 4 Figure C.4 (d) Port 4 Block Diagram (Pin P4 Rev.3.00 Jul. 19, 2007 page 522 of 532 REJ09B0397-0300...
Page 549: Block Diagram Of Port 5
Appendix C I/O Port Block Diagrams Block Diagram of Port 5 Internal data bus PUCR5 PMR5 PDR5 PCR5 Legend: PDR5: Port data register 5 PCR5: Port control register 5 PMR5: Port mode register 5 PUCR5: Port pull-up control register 5 Note: n = 7 to 0 Figure C.5 Port 5 Block Diagram...
Page 550: Block Diagram Of Port 9
Appendix C I/O Port Block Diagrams Block Diagram of Port 9 Internal data bus PDR9 PCR9 Legend: PDR9: Port data register 9 PCR9: Port control register 9 Note: n = 7 to 0 Figure C.6 Port 9 Block Diagram Rev.3.00 Jul. 19, 2007 page 524 of 532 REJ09B0397-0300...
Page 551: Block Diagram Of Port A
Appendix C I/O Port Block Diagrams Block Diagram of Port A Internal data bus PDRA PCRA Legend: PDRA: Port data register A PCRA: Port control register A Note: n = 3 to 0 Figure C.7 Port A Block Diagram Rev.3.00 Jul. 19, 2007 page 525 of 532 REJ09B0397-0300...
Page 552: Block Diagram Of Port B
Appendix C I/O Port Block Diagrams Block Diagram of Port B Internal data bus A/D module AMR0 to AMR3 Notes: H8/3857 Group: n = 7 to 0 H8/3854 Group: n = 7 to 4 Figure C.8 Port B Block Diagram (Pins PB to PB : H8/3857 Group, Pins PB...
Page 553: Appendix D Port States In The Different Processing States
Appendix D Port States in the Different Processing States Appendix D Port States in the Different Processing States Table D.1 Port States Overview Port Reset Sleep Subsleep Standby Watch Subactive Active to P1 High Retained Retained High Retained Functions Functions impedance impedance* to P2...
Page 554: Appendix E List Of Product Codes
Appendix E List of Product Codes Appendix E List of Product Codes Table E.1 H8/3857 Group Product Code Lineup Product Type Part No. Mask Code Package H8/3857F F-ZTAT Standard HD64F3857FQ HD64F3857FQ 144-pin QFP (FP-144H) versions models HD64F3857TG HD64F3857TG 144-pin TQFP (TFP-144) ⎯...
Page 555: Appendix F Package Dimensions
Appendix F Package Dimensions Appendix F Package Dimensions The package dimention that is shown in the Renesas Semiconductor Package Data Book has priority. JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LQFP144-20x20-0.50 PLQP0144KC-A FP-144H/FP-144HV 1.4g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2.
Page 556 Appendix F Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-TQFP144-16x16-0.40 PTQP0144LC-A TFP-144/TFP-144V 0.6g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. Dimension in Millimeters Reference Symbol Min Nom Max Terminal cross section 1.00...
Page 557 Appendix F Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-QFP100-14x14-0.50 PRQP0100KA-A FP-100B/FP-100BV 1.2g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. Dimension in Millimeters Reference Terminal cross section Symbol 2.70 15.7 16.0...
Page 558 Appendix F Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-TQFP100-12x12-0.40 PTQP0100LC-A TFP-100G/TFP-100GV 0.4g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. Dimension in Millimeters Reference Symbol Min Nom Max Terminal cross section 1.00...
Page 559 Publication Date: 1st Edition, March 1999 Rev.3.00, July 19, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. © 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 560 Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Page 562 H8/3857 Group, H8/3857 F-ZTAT™, H8/3854 Group, H8/3854 F-ZTAT™ Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0397-0300...

Renesas F-ZTAT H8 Series Hardware Manual

Section 1 Overview

Section 2 CPU

Section 3 Exception Handling

Section 4 Clock Pulse Generators

Section 5 Power-Down Modes

Section 6 ROM

Section 7 RAM

Section 8 I/O Ports

Section 9 Timers

Section 10 Serial Communication Interface

Section 11 14-Bit PWM (H8/3857 Group Only)

Section 12 A/D Converter

Section 13 Dot Matrix LCD Controller (H8/3857 Group)

Section 14 Dot Matrix LCD Controller (H8/3854 Group)

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Summary of Contents for Renesas F-ZTAT H8 Series