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19.5.2
Division Control Register (DIVCR)
DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency
divider.
Bit
Initial value
Read/Write
DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 2—Reserved: These bits cannot be modified and are always read as 1.
Bits 1 and 0—Divide (DIV1 and DIV0): These bits select the frequency division ratio, as
follows.
Bit 1
Bit 0
DIV1
DIV0
Frequency Division Ratio
0
0
1/1
0
1
1/2
1
0
1/4
1
1
1/8
19.5.3
Usage Notes
The DIVCR setting changes the φ frequency, so note the following points.
• Select a frequency division ratio that stays within the assured operation range specified for the
clock cycle time t
cyc
that give system clock frequencies less than 1 MHz.
• All on-chip module operations are based on φ. Note that the timing of timer operations, serial
communication, and other time-dependent processing differs before and after any change in
the division ratio. The waiting time for exit from software standby mode also changes when
the division ratio is changed. For details, see section 20.4.3, Selection of Waiting Time for Exit
from Software Standby Mode.
7
6
5
1
1
1
Reserved bits
in the AC electrical characteristics. Note that φ
Section 19 Clock Pulse Generator
4
3
2
1
1
1
Divide bits 1 and 0
These bits select the
frequency division ratio
min
Rev. 4.00 Jan 26, 2006 page 673 of 938
1
0
DIV1
DIV0
0
0
R/W
R/W
(Initial value)
= 1 MHz. Avoid settings
REJ09B0276-0400
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