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• Figure 6.33 shows typical interconnections when using two 4-Mbit DRAMs, and the
corresponding address map. The DRAMs used in this example are of the 9-bit row address ×
10-bit column address type. In this example, upper address decoding allows multiple DRAMs
to be connected to a single area. The RFSH pin is used in this case, since both DRAMs must
be refreshed simultaneously. However, note that RAS down mode cannot be used in this
interconnection example.
H8/3067 Group chip
Figure 6.33 Interconnections and Address Map for 2-CAS 4-Mbit DRAMs with × × × × 16-Bit
CS
(RAS
)
2
2
PB
(UCAS)
4
PB
(LCAS)
5
RD (WE)
RFSH
A
19
A
-A
9
1
D
-D
15
0
(a) Interconnections (example)
PB
4
(UCAS)
15
H'400000
DRAM (No.1)
H'47FFFE
H'480000
DRAM (No.2)
H'4FFFFE
Area 2
H'500000
Not used
H'5FFFFE
16-Mbyte mode
(b) Address map
Organization
2-CAS 4-Mbit DRAM
9-bit row address x 9-bit column address
x16-bit organization
RAS
UCAS
LCAS
WE
A
-A
8
0
D
-D
15
0
RAS
UCAS
LCAS
WE
A
-A
8
0
D
-D
15
0
PB
5
(LCAS)
8
7
0
CS
(RAS
)
2
2
Rev. 4.00 Jan 26, 2006 page 187 of 938
Section 6 Bus Controller
No.1
OE
No.2
OE
REJ09B0276-0400
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