Table of Contents
Advertisement
Section 7 DMA Controller
Table 7.14 Address Ranges Specifiable in MAR and IOAR
1-Mbyte Mode
MAR
H'00000 to H'FFFFF
(0 to 1048575)
IOAR
H'FFF00 to H'FFFFF
(1048320 to 1048575)
MAR bits 23 to 20 are ignored in 1-Mbyte mode.
7.6.8
Bus Cycle when Transfer is Aborted
When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME
bit, if this halts a channel for which the DMAC has a transfer request pending internally, a dead
cycle may occur. This dead cycle does not update the halted channel's address register or counter
value. Figure 7.27 shows an example in which an auto-requested transfer in cycle-steal mode on
channel 0 is aborted by clearing the DTE bit in channel 0.
CPU cycle
T
1
φ
Address bus
RD
HWR, LWR
Figure 7.27 Bus Timing at Abort of DMA Transfer in Cycle-Steal Mode
Rev. 4.00 Jan 26, 2006 page 266 of 938
REJ09B0276-0400
DMAC cycle
T
T
T
T
T
2
d
1
2
16-Mbyte Mode
H'000000 to H'FFFFFF
(0 to 16777215)
H'FFFF00 to H'FFFFFF
(16776960 to 16777215)
CPU cycle
T
T
T
T
1
2
1
2
DTE bit is
cleared
DMAC
cycle
CPU cycle
T
T
T
T
3
d
d
1
2
Advertisement
Table of Contents
