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If a DRAM read/write cycle is followed by an access cycle for an external area other than DRAM
space when HWR and LWR are selected as the UCAS and LCAS output pins, an idle cycle (Ti) is
inserted unconditionally immediately after the DRAM access cycle. See section 6.9, Idle Cycle,
for details.
CSn (RAS)
PB
4
(UCAS / LCAS)
Read access
PB
4
(UCAS / LCAS)
Write access
Note: n = 2 to 5
Figure 6.18 Basic Access Timing (CSEL = 0 in DRCRB)
T
p
φ
A
to A
23
0
AS
/PB
5
RD(WE)
D
to D
15
0
/PB
5
RD(WE)
D
to D
15
0
Section 6 Bus Controller
Tr
T
c1
Row
Column
High level
High level
Rev. 4.00 Jan 26, 2006 page 169 of 938
T
c2
REJ09B0276-0400
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