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Bus cycle A
(DRAM access cycle)
Tp
φ
Address bus
HWR/LWR
(UCAS/LCAS)
CSn
(a) Idle cycle not inserted
Figure 6.45 Example of Idle Cycle Operation (3) (HWR
Figure 6.46 Example of Idle Cycle Operation (4) (Consecutive Precharge Cycles)
Usage Notes: When non-insertion of idle cycles is set, the rise (negation) of RD and the fall
(assertion) of CSn may occur simultaneously. An example of the operation is shown in figure
6.47.
If consecutive reads between different external areas occur while the ICIS1 bit is cleared to 0 in
BCR, or if a write cycle to a different external area occurs after an external read while the ICIS0
bit is cleared to 0, the RD negation in the first read cycle and the CSn assertion in the following
bus cycle will occur simultaneously. Therefore, depending on the output delay time of each signal,
it is possible that the low-level output of RD in the preceding read cycle and the low-level output
of CSn in the following bus cycle will overlap.
Bus cycle B
Tr Tc1 Tc2
T1
T2
Simultaneous change of
HWR/LWR and CSn
External read
T1
φ
Address bus
RD
UCAS/LCAS
Address bus
(DRAM access cycle) Bus cycle B
φ
Address bus
HWR/LWR
(UCAS/LCAS)
CSn
HWR/LWR
LWR Used as UCAS
HWR
HWR
LWR
LWR
DRAM space read
T2
T3
Tp
Tr
Tc1
Rev. 4.00 Jan 26, 2006 page 201 of 938
Section 6 Bus Controller
Bus cycle A
Tp
Tr Tc1 Tc2
Ti
(b) Idle cycle inserted
UCAS/LCAS
UCAS
UCAS
Tc2
REJ09B0276-0400
T1
T2
LCAS)
LCAS
LCAS
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