System Control Register (Syscr) - Renesas H8S/2158 User Manual

3.2.2

System Control Register (SYSCR)

SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode
and the detection edge for NMI, enables or disables register access to the on-chip peripheral
modules, and enables or disables on-chip RAM address space.
Bit Bit Name Initial Value
7 CS256E 0
6 IOSE 0
5 INTM1 0
4 INTM0 0
3 XRST 1
R/W Description
R/W Chip Select 256 Enable
Enables or disables P97/WAIT/CPWAIT/CS256 pin
function in extended mode.
0: P97/WAIT/CPWAIT pin
WAIT/CPWAIT pin function is selected by the
settings of WSCR and WSCR2.
1: CS256 pin
Outputs low when a specified address of addresses
H'F80000 to H'FBFFFF is accessed.
R/W IOS Enable
Enables or disables AS/IOS pin function in extended
mode.
0: AS pin
Outputs low when an external area is accessed.
1: IOS pin
Outputs low when a specified address of addresses
H'(FF)F000 to H'(FF)F7FF is accessed.
R These bits select the control mode of the interrupt
R/W controller. For details on the interrupt control modes,
see section 5.6, Interrupt Control Modes and Interrupt
Operation.
00: Interrupt control mode 0
01: Interrupt control mode 1
10: Setting prohibited
11: Setting prohibited
R External Reset
This bit indicates the reset source. A reset is caused
by an external reset input, or when the watchdog timer
overflows.
0: A reset is caused when the watchdog timer
overflows.
1: A reset is caused by an external reset.
Section 3 MCU Operating Modes
Rev. 3.00 Jan 25, 2006 page 57 of 872
REJ09B0286-0300