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Section 8 I/O Ports
Pin
Pin Functions and Selection Method
PB
/TP
/
The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and OS1/0 in TCSR3, bits
3
11
TMIO
/
CCLR1 and CCLR0 in TCR3, bit CS4E in CSCR, bit NDER11 in NDERB, and bit PB
3
DREQ
/CS
function as follows.
1
4
DRAM interface
settings
OIS3/2 and OS1/0
CS4E
PB
DDR
3
NDER11
Pin function
Notes:
1.
2.
3.
DRAM interface
settings
DRAS2
DRAS1
DRAS0
PB
/TP
/
The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and OS1/0 in TCSR2, bit
2
10
TMO
/CS
CS5E in CSCR, bit NDER10 in NDERB, and bit PB
2
5
DRAM interface
settings
OIS3/2 and OS1/0
CS5E
PB
DDR
2
NDER10
Pin function
CS
Note: *
5
DRAM interface
settings
DRAS2
DRAS1
DRAS0
Rev. 4.00 Jan 26, 2006 page 322 of 938
REJ09B0276-0400
0
—
PB
3
input
TMIO
input when CCLR1 = CCLR0 = 1.
3
When an external request is specified as a DMAC activation source, DREQ
bits OIS3 and OIS2, OS1 and OS0, CCLR1 and CCLR0, CS4E, NDER11, and PB
CS
is output as RAS
.
4
4
0
0
1
0
—
PB
2
input
is output as RAS
.
5
0
0
1
(1) in table below
All 0
0
1
1
0
1
PB
TP
3
11
output
output
input *
TMIO
3
DREQ
input *
1
(1)
0
1
0
1
DDR select the pin function as follows.
2
(1) in table below
All 0
0
1
1
0
1
PB
TP
2
10
output
output
(1)
0
1
0
1
DDR select the pin
3
(2) in table
Not all 0
1
—
—
—
—
—
CS
TMIO
output
4
3
output
1
2
input regardless of
1
DDR.
3
(2)
1
0
0
1
0
(2) in table
Not all 0
1
—
—
—
—
—
CS
TMIO
output
5
2
output
(2)
(1)
1
0
0
1
0
below
—
—
—
—
CS
4
output *
3
(1)
1
1
below
—
—
—
—
CS
5
output*
1
1
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