Renesas H8/3067 Series User Manual page 845

DTCR0A—Data Transfer Control Register 0A (cont)
•
Full address mode
7
Bit
DTE
Initial value 0
Read/Write R/W
Data transfer size
0 Byte-size transfer
1
Word-size transfer
Data transfer enable
0
Data transfer is disabled
1
Data transfer is enabled
6 5 4
DTSZ SAID SAIDE
0 0 0
R/W R/W R/W
Source address increment/decrement (bit 5)
Source address increment/decrement enable (bit 4)
Bit 5 Bit 4
SAID SAIDE
0 MARA is held fixed
0
Incremented: If DTSZ = 0, MARA is incremented by 1 after each transfer
1
0
MARA is held fixed
1
Decremented: If DTSZ = 0, MARA is decremented by 1 after each transfer
1
Appendix B Internal I/O Registers
H'FFF27
3 2
DTIE DTS2A
0 0
R/W R/W
Data transfer select 2A and 1A
Set both bits to 1
Data transfer interrupt enable
0 Interrupt requested by DTE bit is disabled
1 Interrupt requested by DTE bit is enabled
Increment/Decrement Enable
If DTSZ = 1, MARA is incremented by 2 after each transfer
If DTSZ = 1, MARA is decremented by 2 after each transfer
Rev. 4.00 Jan 26, 2006 page 821 of 938
DMAC0
1 0
DTS1A DTS0A
0 0
R/W R/W
Data transfer select 0A
0 Normal mode
1 Block transfer mode
REJ09B0276-0400