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Section 6 Bus Controller
6.5.7
Precharge State Control
In the H8/3067 Group, provision is made for the DRAM RAS precharge time by always inserting
one RAS precharge state (T
by setting the TPC bit to 1 in DRCRB. The optimum number of T
to the DRAM connected and the operating frequency of the H8/3067 Group chip. Figure 6.19
shows the timing when two T
When the TCP bit is set to 1, two T
CSn (RAS)
PB
4
(UCAS /LCAS)
Read access
RD(WE)
D
PB
4
(UCAS /LCAS)
Write access
RD(WE)
D
Note: n = 2 to 5
Figure 6.19 Timing with Two Precharge States (CSEL = 0 in DRCRB)
Rev. 4.00 Jan 26, 2006 page 170 of 938
REJ09B0276-0400
) when DRAM space is accessed. This can be changed to two T
p
states are inserted.
p
states are also used for CAS-before-RAS refresh cycles.
p
T
p1
φ
A
to A
23
0
AS
/PB
5
to D
15
0
/PB
5
D
15 to
0
cycles should be set according
p
T
Tr
p2
Row
High level
High level
states
p
T
T
c1
c2
Column
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