Renesas H8/3066 Manuals

Manuals and User Guides for Renesas H8/3066. We have 1 Renesas H8/3066 manual available for free PDF download: User Manual

Renesas H8/3066 User Manual (965 pages)

Renesas 16-Bit Single-Chip Microcomputer

Brand: Renesas | Category: Computer Hardware | Size: 5.02 MB

Table of Contents
9
Section 1 Overview
25
Overview
25
Block Diagram
31
Pin Description
32
Pin Arrangement
32
Pin Functions
34
Pin Assignments in each Mode
40
Notes on Flash Memory R Version Model
45
Pin Arrangement
45
Differences in Flash Memory R Version
45
Section 2 CPU
47
Overview
47
Features
47
Differences from H8/300 CPU
48
CPU Operating Modes
49
Address Space
50
Register Configuration
51
Overview
51
General Registers
52
Control Registers
53
Initial CPU Register Values
54
Data Formats
55
General Register Data Formats
55
Memory Data Formats
56
Instruction Set
58
Instruction Set Overview
58
Instructions and Addressing Modes
59
Tables of Instructions Classified by Function
60
Basic Instruction Formats
69
Notes on Use of Bit Manipulation Instructions
70
Addressing Modes and Effective Address Calculation
72
Addressing Modes
72
Effective Address Calculation
74
Processing States
78
Overview
78
Program Execution State
79
Exception-Handling State
79
Exception-Handling Sequences
81
Bus-Released State
82
Reset State
82
Power-Down State
83
Basic Operational Timing
84
Overview
84
On-Chip Memory Access Timing
84
On-Chip Supporting Module Access Timing
85
Access to External Address Space
86
Section 3 MCU Operating Modes
87
Overview
87
Operating Mode Selection
87
Register Configuration
88
Mode Control Register (MDCR)
89
System Control Register (SYSCR)
90
Operating Mode Descriptions
92
Mode 1
92
Mode 2
92
Mode 3
92
Mode 4
93
Mode 5
93
Mode 6
93
Mode 7
93
Pin Functions in each Operating Mode
94
Memory Map in each Operating Mode
95
Note on Reserved Areas
95
Section 4 Exception Handling
103
Overview
103
Exception Handling Types and Priority
103
Exception Handling Operation
103
Exception Vector Table
104
Reset
106
Overview
106
Reset Sequence
106
Interrupts after Reset
109
Interrupts
110
Trap Instruction
111
Stack Status after Exception Handling
112
Notes on Stack Usage
113
Section 5 Interrupt Controller
115
Overview
115
Features
115
Block Diagram
116
Pin Configuration
117
Register Configuration
117
Register Descriptions
118
System Control Register (SYSCR)
118
Interrupt Priority Registers a and B (IPRA, IPRB)
119
IRQ Status Register (ISR)
126
IRQ Enable Register (IER)
127
IRQ Sense Control Register (ISCR)
128
Interrupt Sources
129
External Interrupts
129
Internal Interrupts
130
Interrupt Vector Table
130
Interrupt Operation
134
Interrupt Handling Process
134
Interrupt Sequence
139
Interrupt Response Time
140
Usage Notes
141
Contention between Interrupt and Interrupt-Disabling Instruction
141
Instructions that Inhibit Interrupts
142
Interrupts During EEPMOV Instruction Execution
142
Section 6 Bus Controller
143
Overview
143
Features
143
Block Diagram
145
Pin Configuration
146
Register Configuration
147
Register Descriptions
148
Bus Width Control Register (ABWCR)
148
Access State Control Register (ASTCR)
149
Wait Control Registers H and L (WCRH, WCRL)
149
Bus Release Control Register (BRCR)
154
Bus Control Register (BCR)
156
Chip Select Control Register (CSCR)
158
DRAM Control Register a (DRCRA)
159
DRAM Control Register B (DRCRB)
161
Refresh Timer Control/Status Register (RTMCSR)
164
Refresh Timer Counter (RTCNT)
165
Refresh Time Constant Register (RTCOR)
166
Address Control Register (ADRCR) (Provided Only in Flash Memory R Version and Mask ROM Versions)
167
Operation
168
Area Division
168
Bus Specifications
171
Memory Interfaces
172
Chip Select Signals
172
Address Output Method
174
Basic Bus Interface
176
Overview
176
Data Size and Data Alignment
176
Valid Strobes
177
Memory Areas
178
Basic Bus Control Signal Timing
180
Wait Control
187
DRAM Interface
189
Overview
189
DRAM Space and RAS Output Pin Settings
189
Address Multiplexing
191
Data Bus
191
Pins Used for DRAM Interface
192
Basic Timing
192
Precharge State Control
194
Wait Control
195
Byte Access Control and cas Output Pin
196
Burst Operation
198
Refresh Control
204
Examples of Use
208
Usage Notes
212
Interval Timer
215
Operation
215
Interrupt Sources
221
Burst ROM Interface
221
Overview
221
Basic Timing
221
Wait Control
222
Idle Cycle
223
Operation
223
Pin States in Idle Cycle
226
Bus Arbiter
227
Operation
227
Register and Pin Input Timing
230
Register Write Timing
230
BREQ Pin Input Timing
231
Section 7 DMA Controller
233
Overview
233
Features
233
Block Diagram
234
Functional Overview
235
Input/Output Pins
236
Register Configuration
236
Register Descriptions (1) (Short Address Mode)
238
Memory Address Registers (MAR)
238
I/O Address Registers (IOAR)
239
Execute Transfer Count Registers (ETCR)
239
Data Transfer Control Registers (DTCR)
241
Register Descriptions (2) (Full Address Mode)
244
Memory Address Registers (MAR)
244
I/O Address Registers (IOAR)
244
Execute Transfer Count Registers (ETCR)
245
Data Transfer Control Registers (DTCR)
247
Operation
253
Overview
253
I/O Mode
255
Idle Mode
257
Repeat Mode
260
Normal Mode
264
Block Transfer Mode
267
DMAC Activation
272
DMAC Bus Cycle
274
Multiple-Channel Operation
280
External Bus Requests, DRAM Interface, and DMAC
281
NMI Interrupts and DMAC
282
Aborting a DMAC Transfer
283
Exiting Full Address Mode
284
DMAC States in Reset State, Standby Modes, and Sleep Mode
285
Interrupts
286
Usage Notes
287
Note on Word Data Transfer
287
DMAC Self-Access
287
Longword Access to Memory Address Registers
287
Note on Full Address Mode Setup
287
Note on Activating DMAC by Internal Interrupts
288
NMI Interrupts and Block Transfer Mode
289
Memory and I/O Address Register Values
289
Bus Cycle When Transfer Is Aborted
290
Transfer Requests by A/D Converter
291
Section 8 I/O Ports
293
Overview
293
Port 1
296
Overview
296
Register Descriptions
297
Port 2
299
Overview
299
Register Descriptions
300
Port 3
303
Overview
303
Register Descriptions
303
Port 4
305
Overview
305
Register Descriptions
306
Port 5
309
Overview
309
Register Descriptions
310
Port 6
313
Overview
313
Register Descriptions
314
Port 7
317
Overview
317
Register Description
318
Port 8
319
Overview
319
Register Descriptions
320
Port 9
325
Overview
325
Register Descriptions
326
Port a
330
Overview
330
Register Descriptions
332
Port B
341
Overview
341
Register Descriptions
343
Section 9 16-Bit Timer
351
Overview
351
Features
351
Block Diagrams
354
Input/Output Pins
357
Register Configuration
358
Register Descriptions
360
Timer Start Register (TSTR)
360
Timer Synchro Register (TSNC)
361
Timer Mode Register (TMDR)
363
Timer Interrupt Status Register a (TISRA)
366
Timer Interrupt Status Register B (TISRB)
369
Timer Interrupt Status Register C (TISRC)
372
Timer Counters (TCNT)
374
General Registers (GRA, GRB)
375
Timer Control Registers (TCR)
376
Timer I/O Control Register (TIOR)
378
Timer Output Level Setting Register C (TOLR)
380
CPU Interface
383
16-Bit Accessible Registers
383
8-Bit Accessible Registers
385
Operation
386
Overview
386
Basic Functions
387
Synchronization
395
PWM Mode
397
Phase Counting Mode
401
Setting Initial Value of 16-Bit Timer Output
403
Interrupts
404
Setting of Status Flags
404
Timing of Clearing of Status Flags
406
Interrupt Sources and DMA Controller Activation
407
Usage Notes
408
Section 10 8-Bit Timers
421
Overview
421
Features
421
Block Diagram
423
Pin Configuration
424
Register Configuration
425
Register Descriptions
426
Timer Counters (TCNT)
426
Time Constant Registers a (TCORA)
427
Time Constant Registers B (TCORB)
428
Timer Control Register (TCR)
429
Timer Control/Status Registers (TCSR)
432
CPU Interface
437
8-Bit Registers
437
Operation
439
TCNT Count Timing
439
Compare Match Timing
440
Input Capture Signal Timing
441
Timing of Status Flag Setting
442
Operation with Cascaded Connection
443
Input Capture Setting
445
Interrupts
447
Interrupt Sources
447
A/D Converter Activation
448
8-Bit Timer Application Example
448
Usage Notes
449
Contention between TCNT Write and Clear
449
Contention between TCNT Write and Increment
450
Contention between TCOR Write and Compare Match
451
Contention between TCOR Read and Input Capture
452
Contention between Counter Clearing by Input Capture and Counter Increment
453
Contention between TCOR Write and Input Capture
454
Contention between TCNT Byte Write and Increment in 16-Bit Count Mode (Cascaded Connection)
455
Contention between Compare Matches a and B
456
TCNT Operation at Internal Clock Source Switchover
456
Section 11 Programmable Timing Pattern Controller (TPC)
459
Overview
459
Features
459
Block Diagram
460
TPC Pins
461
Registers
462
Register Descriptions
463
Port a Data Direction Register (PADDR)
463
Port a Data Register (PADR)
463
Port B Data Direction Register (PBDDR)
464
Port B Data Register (PBDR)
464
Next Data Register a (NDRA)
465
Next Data Register B (NDRB)
467
Next Data Enable Register a (NDERA)
469
Next Data Enable Register B (NDERB)
470
TPC Output Control Register (TPCR)
471
TPC Output Mode Register (TPMR)
474
Operation
476
Overview
476
Output Timing
477
Normal TPC Output
478
Non-Overlapping TPC Output
480
TPC Output Triggering by Input Capture
482
Usage Notes
483
Operation of TPC Output Pins
483
Note on Non-Overlapping Output
483
Section 12 Watchdog Timer
485
Overview
485
Features
485
Block Diagram
486
Pin Configuration
486
Register Configuration
487
Register Descriptions
488
Timer Counter (TCNT)
488
Timer Control/Status Register (TCSR)
489
Reset Control/Status Register (RSTCSR)
491
Notes on Register Access
493
Operation
495
Watchdog Timer Operation
495
Interval Timer Operation
496
Timing of Setting of Overflow Flag (OVF)
497
Timing of Setting of Watchdog Timer Reset Bit (WRST)
498
Interrupts
499
Usage Notes
499
Section 13 Serial Communication Interface
501
Overview
501
Features
501
Block Diagram
503
Input/Output Pins
504
Register Configuration
505
Register Descriptions
506
Receive Shift Register (RSR)
506
Receive Data Register (RDR)
506
Transmit Shift Register (TSR)
507
Transmit Data Register (TDR)
507
Serial Mode Register (SMR)
508
Serial Control Register (SCR)
512
Serial Status Register (SSR)
517
Bit Rate Register (BRR)
523
Operation
531
Overview
531
Operation in Asynchronous Mode
533
Multiprocessor Communication
543
Synchronous Operation
550
SCI Interrupts
558
Usage Notes
559
Notes on Use of SCI
559
Section 14 Smart Card Interface
565
Overview
565
Features
565
Block Diagram
566
Pin Configuration
567
Register Configuration
568
Register Descriptions
569
Smart Card Mode Register (SCMR)
569
Serial Status Register (SSR)
571
Serial Mode Register (SMR)
573
Serial Control Register (SCR)
574
Operation
575
Overview
575
Pin Connections
575
Data Format
577
Register Settings
578
Clock
580
Transmitting and Receiving Data
582
Usage Notes
590
Section 15 A/D Converter
593
Overview
593
Features
593
Block Diagram
594
Input Pins
595
Register Configuration
596
Register Descriptions
597
A/D Data Registers a to D (ADDRA to ADDRD)
597
A/D Control/Status Register (ADCSR)
598
A/D Control Register (ADCR)
601
CPU Interface
602
Operation
604
Single Mode (SCAN = 0)
604
Scan Mode (SCAN = 1)
606
Input Sampling and A/D Conversion Time
608
External Trigger Input Timing
610
Interrupts
611
Usage Notes
611
Section 16 D/A Converter
617
Overview
617
Features
617
Block Diagram
618
Input/Output Pins
618
Register Configuration
619
Register Descriptions
620
D/A Data Registers 0 and 1 (DADR0/1)
620
D/A Control Register (DACR)
620
D/A Standby Control Register (DASTCR)
622
Operation
623
D/A Output Control
624
Section 17 RAM
625
Overview
625
Block Diagram
626
Register Configuration
627
System Control Register (SYSCR)
628
Operation
629
Section 18 ROM
631
Overview
631
Overview of Flash Memory
632
Features
632
Block Diagram
633
Pin Configuration
634
Register Configuration
634
Register Descriptions
635
Flash Memory Control Register (FLMCR)
635
Erase Block Register (EBR)
639
RAM Control Register (RAMCR)
641
Flash Memory Status Register
643
On-Board Programming Modes
645
Boot Mode
648
User Program Mode
653
Programming/Erasing Flash Memory
655
Program Mode
656
Program-Verify Mode
657
Erase Mode
659
Erase-Verify Mode
659
Flash Memory Protection
661
Hardware Protection
661
Software Protection
663
Error Protection
663
NMI Input Disable Conditions
666
Flash Memory Emulation by RAM
667
Flash Memory PROM Mode
669
PROM Mode Setting
669
Memory Map
669
PROM Mode Operation
669
Memory Read Mode
672
Auto-Program Mode
675
Auto-Erase Mode
677
Status Read Mode
679
PROM Mode Transition Time
680
Notes on Memory Programming
681
Notes on Flash Memory Programming/Erasing
682
Mask ROM Overview
687
18.10.1 Block Diagram
687
Notes on Ordering Mask ROM Version Chip
688
Section 19 Clock Pulse Generator
689
Overview
689
Block Diagram
690
Oscillator Circuit
691
Connecting a Crystal Resonator
691
External Clock Input
693
Duty Adjustment Circuit
696
Prescalers
696
Frequency Divider
696
Register Configuration
696
Division Control Register (DIVCR)
697
Usage Notes
697
Section 20 Power-Down State
699
Overview
699
Register Configuration
701
System Control Register (SYSCR)
701
Module Standby Control Register H (MSTCRH)
703
Module Standby Control Register L (MSTCRL)
704
Sleep Mode
707
Transition to Sleep Mode
707
Exit from Sleep Mode
707
Software Standby Mode
708
Transition to Software Standby Mode
708
Exit from Software Standby Mode
708
Selection of Waiting Time for Exit from Software Standby Mode
709
Sample Application of Software Standby Mode
711
Note
711
Cautions on Clearing the Software Standby Mode of F-ZTAT Version
712
Hardware Standby Mode
713
Transition to Hardware Standby Mode
713
Exit from Hardware Standby Mode
713
Timing for Hardware Standby Mode
714
Module Standby Function
715
Module Standby Timing
715
Read/Write in Module Standby
715
Usage Notes
715
System Clock Output Disabling Function
717
Section 21 Electrical Characteristics
719
Electrical Characteristics of Mask ROM Version
719
Absolute Maximum Ratings
719
DC Characteristics
720
AC Characteristics
730
A/D Conversion Characteristics
738
D/A Conversion Characteristics
740
Electrical Characteristics of Flash Memory and Flash Memory R Versions
741
Absolute Maximum Ratings
741
DC Characteristics
742
AC Characteristics
749
A/D Conversion Characteristics
756
D/A Conversion Characteristics
758
Flash Memory Characteristics
759
Operational Timing
761
Clock Timing
761
Control Signal Timing
762
Bus Timing
763
DRAM Interface Bus Timing
769
TPC and I/O Port Timing
772
Timer Input/Output Timing
773
SCI Input/Output Timing
774
DMAC Timing
775
Appendix A Instruction Set
777
Instruction List
777
Operation Code Maps
792
Number of States Required for Execution
795
Appendix B Internal I/O Registers
804
Addresses
804
Functions
815
Appendix C I/O Port Block Diagrams
903
Port 1 Block Diagram
903
Port 2 Block Diagram
904
Port 3 Block Diagram
905
Port 4 Block Diagram
906
Port 5 Block Diagram
907
Port 6 Block Diagrams
908
Port 7 Block Diagrams
915
Port 8 Block Diagrams
916
Port 9 Block Diagrams
921

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Renesas H8/3066 User Manual (965 pages)

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