Bus Release Control Register (Brcr) - Renesas H8/3067 Series User Manual

Section 6 Bus Controller
6.2.4

Bus Release Control Register (BRCR)

BRCR is an 8-bit readable/writable register that enables address output on bus lines A
enables or disables release of the bus to an external device.
Bit 7
A23E
Modes
Initial value 1
1, 2, 6,
and 7 Read/Write —
Initial value 1
Modes
3 and 4
Read/Write R/W
Initial value 1
Mode 5
Read/Write R/W
Address 23 to 20 enable
These bits enable PA
used for A
BRCR is initialized to H'FE in modes 1, 2, 5, 6, and 7, and to H'EE in modes 3 and 4, by a reset
and in hardware standby mode. It is not initialized in software standby mode.
Bit 7—Address 23 Enable (A23E): Enables PA
0 in this bit enables A
modified and PA has its ordinary port functions.
4
Bit 7
A23E Description
0 PA
1 PA
Rev. 4.00 Jan 26, 2006 page 130 of 938
REJ09B0276-0400
6 5
A22E A21E
1 1
— —
1 1
R/W R/W
1 1
R/W R/W
to PA
7
to A address output
23 20
output from PA . In modes other than 3, 4, and 5, this bit cannot be
23 4
is the A address output pin
4 23
is an input/output pin
4
4 3 2
A20E — —
1 1 1
— — —
0 1 1
— — —
1 1 1
R/W — —
Reserved bits
to be
4
to be used as the A
4
to A
23
1 0
— BRLE
1 0
— R/W
1 0
— R/W
1 0
— R/W
Bus release enable
Enables or disables release
of the bus to an external device
address output pin. Writing
23
(Initial value)
and
20