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Section 18 ROM
18.2.3
Pin Configuration
The flash memory is controlled by means of the pins shown in table 18.2.
Table 18.2 Flash Memory Pins
Pin Name
Reset
Flash write enable
Mode 2
Mode 1
Mode 0
Transmit data
Receive data
Note: The transmit data and receive data pins are used in boot mode.
* In the mask ROM versions, the FWE pin functions as the RESO pin.
18.2.4
Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 18.3.
Table 18.3 Flash Memory Registers
Register Name
Flash memory control register
Erase block register
RAM control register
Flash memory status register
Notes: 1. Lower 20 bits of address in advanced mode.
2. When a high level is input to the FWE pin, the initial value is H'80.
The registers in table 18.3 are used in the flash memory and flash memory R versions only.
Reading the corresponding addresses in a mask ROM version will always return 1s, and writes to
these addresses are disabled.
Rev. 4.00 Jan 26, 2006 page 610 of 938
REJ09B0276-0400
Abbreviation
I/O
RES
Input
FWE*
Input
MD
Input
2
MD
Input
1
MD
Input
0
TxD
Output
1
RxD
Input
1
Abbreviation
FLMCR
EBR
RAMCR
FLMSR
Function
Reset
Flash program/erase protection by hardware
Sets this LSI operating mode
Sets this LSI operating mode
Sets this LSI operating mode
Serial transmit data output
Serial receive data input
R/W
Initial Value
H'00 *
2
R/W
R/W
H'00
R/W
H'F1
R
H'7F
Address *
1
H'EE030
H'EE032
H'EE077
H'EE07D
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