Table of Contents
Advertisement
Section 5 Interrupt Controller
5.4.3
Interrupt Response Time
Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the
first instruction of the interrupt service routine is executed.
Table 5.5
Interrupt Response Time
No.
Item
1
Interrupt priority
decision
2
Maximum number
of states until end of
current instruction
3
Saving PC and CCR
to stack
4
Vector fetch
Instruction prefetch *
5
Internal processing *
6
Total
Notes: 1. 1 state for internal interrupts.
2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the
interrupt service routine.
3. Internal processing after the interrupt is accepted and internal processing after vector
fetch.
4. The number of states increases if wait states are inserted in external memory access.
Rev. 4.00 Jan 26, 2006 page 116 of 938
REJ09B0276-0400
External Memory
8-Bit Bus
On-Chip
Memory
2 States
2 *
2 *
1
1
1 to 23
1 to 27
4
8
4
8
2
4
8
3
4
4
19 to 41
31 to 57
16-Bit Bus
3 States
2 States
2 *
2 *
1
1
1 to 31 *
4
1 to 23
12 *
4
4
12 *
4
4
12 *
4
4
4
4
43 to 73
19 to 41
3 States
2 *
1
1 to 25 *
4
6 *
4
6 *
4
6 *
4
4
25 to 49
Advertisement
Table of Contents
