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Renesas H8 Series Hardware Manual

16-bit single-chip microcomputer

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Page 1 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
Page 3 H8/36094 Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series H8/36094F HD64F36094 HD64F36094G H8/36092F HD64F36092 HD64F36092G Rev.1.00 2006.08...
Page 4 Rev. 1.00 Aug. 28, 2006 Page ii of xxviii...
Page 5 (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp.
Page 6: General Precautions On Handling Of Product
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 7 Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Page 8: Preface
The H8/36094 Group are single-chip microcomputers made up of the high-speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU.
Page 9 P87 are input pins, and P86 is an output pin. Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ H8/36094 Group manuals: Document Title Document No.
Page 10 Rev. 1.00 Aug. 28, 2006 Page viii of xxviii...
Page 11: Table Of Contents
Contents Section 1 Overview....................1 Features..........................1 Internal Block Diagram......................3 Pin Assignments........................4 Pin Functions ......................... 6 Section 2 CPU......................9 Address Space and Memory Map ..................10 Register Configuration......................11 2.2.1 General Registers....................12 2.2.2 Program Counter (PC) .................... 13 2.2.3 Condition-Code Register (CCR)................
Page 12 3.2.4 Interrupt Flag Register 1 (IRR1)................48 3.2.5 Wakeup Interrupt Flag Register (IWPR) ..............49 Reset Exception Handling....................51 Interrupt Exception Handling ....................51 3.4.1 External Interrupts ....................51 3.4.2 Internal Interrupts ....................53 3.4.3 Interrupt Handling Sequence .................. 53 3.4.4 Interrupt Response Time..................
Page 13 5.7.1 Prescaler S ......................82 5.7.2 Prescaler W......................82 Usage Notes ......................... 83 5.8.1 Note on Resonators....................83 5.8.2 Notes on Board Design ................... 83 Section 6 Power-Down Modes ................85 Register Descriptions ......................85 6.1.1 System Control Register 1 (SYSCR1) ..............85 6.1.2 System Control Register 2 (SYSCR2) ..............
Page 14 7.5.3 Error Protection ....................112 Programmer Mode ......................113 Power-Down States for Flash Memory................113 Section 8 RAM ....................115 Section 9 I/O Ports..................... 117 Port 1..........................117 9.1.1 Port Mode Register 1 (PMR1) ................118 9.1.2 Port Control Register 1 (PCR1) ................119 9.1.3 Port Data Register 1 (PDR1) ................
Page 15 Section 10 Timer A....................143 10.1 Features..........................143 10.2 Input/Output Pins ....................... 144 10.3 Register Descriptions ......................145 10.3.1 Timer Mode Register A (TMA)................145 10.3.2 Timer Counter A (TCA) ..................146 10.4 Operation ........................... 147 10.4.1 Interval Timer Operation ..................147 10.4.2 Clock Time Base Operation..................
Page 16 12.3.8 General Registers A to D (GRA to GRD)............. 175 12.4 Operation ........................... 176 12.4.1 Normal Operation ....................176 12.4.2 PWM Operation....................181 12.5 Operation Timing....................... 186 12.5.1 TCNT Count Timing .................... 186 12.5.2 Output Compare Output Timing................186 12.5.3 Input Capture Timing ................... 187 12.5.4 Timing of Counter Clearing by Compare Match ..........
Page 17 14.5 Operation in Clocked Synchronous Mode ................. 223 14.5.1 Clock........................223 14.5.2 SCI3 Initialization....................224 14.5.3 Serial Data Transmission ..................224 14.5.4 Serial Data Reception (Clocked Synchronous Mode)........... 227 14.5.5 Simultaneous Serial Data Transmission and Reception........229 14.6 Multiprocessor Communication Function................231 14.6.1 Multiprocessor Serial Data Transmission .............
Page 18 15.5 Interrupt Request........................ 273 15.6 Bit Synchronous Circuit..................... 273 15.7 Usage Notes ........................274 15.7.1 Issue (Retransmission) of Start/Stop Conditions ..........274 15.7.2 WAIT Setting in I C Bus Mode Register (ICMR) ..........274 Section 16 A/D Converter ................. 275 16.1 Features..........................
Page 19 Section 19 List of Registers ................303 19.1 Register Addresses (Address Order).................. 304 19.2 Register Bits........................309 19.3 Registers States in Each Operating Mode ................313 Section 20 Electrical Characteristics ..............317 20.1 Absolute Maximum Ratings ....................317 20.2 Electrical Characteristics....................317 20.2.1 Power Supply Voltage and Operating Ranges ............
Page 20 Rev. 1.00 Aug. 28, 2006 Page xviii of xxviii...
Page 21 Figures Section 1 Overview Figure 1.1 Internal Block Diagram of H8/36094 Group of F-ZTAT .......... 3 Figure 1.2 Pin Assignments of H8/36094 Group of F-ZTAT (FP-64K, FP-64A) ...... 4 Figure 1.3 Pin Assignments of H8/36094 Group of F-ZTAT (FP-48F, FP-48B, TNP-48) ..5 Section 2 CPU Figure 2.1 Memory map .......................
Page 22 Figure 5.5 Flowchart of Clock Switching with Backup Function Disabled (2) (From External Clock to On-Chip Oscillator Clock) ..........73 Figure 5.6 Timing Chart of Switching from On-Chip Oscillator Clock to External Clock ..74 Figure 5.7 Timing Chart to Switch from External Clock to On-Chip Oscillator Clock ....75 Figure 5.8 External Oscillation Backup Timing ................
Page 23 Figure 11.5 CMFA and CMFB Set Timing ................158 Figure 11.6 TMOV Output Timing .................... 158 Figure 11.7 Clear Timing by Compare Match................158 Figure 11.8 Clear Timing by TMRIV Input ................159 Figure 11.9 Pulse Output Example ..................... 159 Figure 11.10 Example of Pulse Output Synchronized to TRGV Input........
Page 24 Section 13 Watchdog Timer Figure 13.1 Block Diagram of Watchdog Timer ................ 195 Figure 13.2 Watchdog Timer Operation Example..............199 Section 14 Serial Communication Interface 3 (SCI3) Figure 14.1 Block Diagram of SCI3................... 202 Figure 14.2 Data Format in Asynchronous Communication ............215 Figure 14.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) .....
Page 25 Figure 15.8 Master Receive Mode Operation Timing (2)............262 Figure 15.9 Slave Transmit Mode Operation Timing (1) ............263 Figure 15.10 Slave Transmit Mode Operation Timing (2) ............264 Figure 15.11 Slave Receive Mode Operation Timing (1)............265 Figure 15.12 Slave Receive Mode Operation Timing (2)............265 Figure 15.13 Clocked Synchronous Serial Transfer Format............
Page 26 Figure 20.7 Output Load Circuit ....................337 Appendix Figure B.1 Port 1 Block Diagram (P17) ..................369 Figure B.2 Port 1 Block Diagram (P16 to P14) ................370 Figure B.3 Port 1 Block Diagram (P12, P11) ................371 Figure B.4 Port 1 Block Diagram (P10) ..................372 Figure B.5 Port 2 Block Diagram (P22) ..................
Page 27 Tables Section 1 Overview Table 1.1 Pin Functions ......................6 Section 2 CPU Table 2.1 Operation Notation ....................18 Table 2.2 Data Transfer Instructions..................19 Table 2.3 Arithmetic Operations Instructions (1) ..............20 Table 2.3 Arithmetic Operations Instructions (2) ..............21 Table 2.4 Logic Operations Instructions.................
Page 28 Table 7.4 Reprogram Data Computation Table ..............109 Table 7.5 Additional-Program Data Computation Table ............109 Table 7.6 Programming Time ....................109 Table 7.7 Flash Memory Operating States................113 Section 10 Timer A Table 10.1 Pin Configuration....................144 Section 11 Timer V Table 11.1 Pin Configuration....................
Page 29 Table 20.2 DC Characteristics (2)................... 324 Table 20.3 AC Characteristics ....................325 Table 20.4 C Bus Interface Timing ..................328 Table 20.5 Serial Communication Interface (SCI) Timing............. 329 Table 20.6 A/D Converter Characteristics ................330 Table 20.7 Watchdog Timer Characteristics................331 Table 20.8 Flash Memory Characteristics ................
Page 30 Rev. 1.00 Aug. 28, 2006 Page xxviii of xxviii...
Page 31: Section 1 Overview
Section 1 Overview Section 1 Overview Features • High-speed H8/300H central processing unit with an internal 16-bit architecture  Upward-compatible with H8/300 CPU on an object level  Sixteen 16-bit general registers  62 basic instructions • Various peripheral functions ...
Page 32: Section 1 Overview
= –20 to 75°C 16 MHz ± 4% = 3.0 to 5.5 V, T = –20 to 75°C • Supports various power-down modes Note: F-ZTAT is a trademark of Renesas Technology Corp. • Compact package Package Code Body Size Pin Pitch ×...
Page 33: Internal Block Diagram
Section 1 Overview Internal Block Diagram P80/FTCI External P81/FTIOA Subclock On-chip clock P82/FTIOB generator H8/300H oscillator generator P83/FTIOC P84/FTIOD Data bus (lower) P10/TMOW P14/IRQ0 P15/IRQ1 P74/TMRIV P16/IRQ2 P75/TMCIV P17/IRQ3/TRGV P76/TMOV Timer W SCI3 P50/WKP0 P51/WKP1 P20/SCK3 P52/WKP2 P21/RXD Watchdog P53/WKP3 Timer A timer P22/TXD...
Page 34: Pin Assignments
Section 1 Overview Pin Assignments 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P76/TMOV P14/IRQ0 P75/TMCIV P15/IRQ1 P74/TMRIV P16/IRQ2 P57/SCL P17/IRQ3/TRGV P56/SDA PB4/AN4 PB5/AN5 H8/36094 Group PB6/AN6 (Top view) P10/TMOW PB7/AN7 P55/WKP5/ADTRG PB3/AN3 P54/WKP4 PB2/AN2...
Page 35: Figure 1.3 Pin Assignments Of H8/36094 Group Of F-Ztat Tm (Fp-48F, Fp-48B, Tnp-48)
Section 1 Overview 36 35 34 33 32 31 30 29 28 27 26 25 P76/TMOV P14/IRQ0 P75/TMCIV P15/IRQ1 P74/TMRIV P16/IRQ2 P57/SCL P17/IRQ3/TRGV P56/SDA PB4/AN4 PB5/AN5 H8/36094 Group PB6/AN6 (Top View) P10/TMOW PB7/AN7 P55/WKP5/ADTRG PB3/AN3 P54/WKP4 PB2/AN2 P53/WKP3 PB1/AN1 P52/WKP2 PB0/AN0 8 9 10 11 12 Figure 1.3 Pin Assignments of H8/36094 Group of F-ZTAT...
Page 36: Pin Functions
Section 1 Overview Pin Functions Table 1.1 Pin Functions Pin No. FP-48F FP-64K FP-48B Type Symbol FP-64A TNP-48 Functions Power Input Power supply pin. Connect this pin to the source system power supply. pins Input Ground pin. Connect this pin to the system power supply (0V).
Page 37 Section 1 Overview Pin No. FP-48F FP-64K FP-48B Type Symbol FP-64A TNP-48 Functions Timer V TMOV Output This is an output pin for waveforms generated by the output compare function. TMCIV Input External event input pin. TMRIV Input Counter reset input pin. TRGV Input Counter start trigger input pin.
Page 38 Section 1 Overview Pin No. FP-48F FP-64K FP-48B Type Symbol FP-64A TNP-48 Functions I/O ports P76 to 28 to 30 22 to 24 3-bit I/O port P87 to 36 to 43 26 to 33 8-bit I/O port Rev. 1.00 Aug. 28, 2006 Page 8 of 400 REJ09B0268-0100...
Page 39: Section 2 Cpu
Section 2 CPU Section 2 CPU This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space. • Upward-compatible with H8/300 CPUs  Can execute H8/300 CPUs object programs ...
Page 40: Address Space And Memory Map
Section 2 CPU • Power-down state  Transition to power-down state by SLEEP instruction Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. Figure 2.1 shows the memory map. HD64F36094, HD64F36094G HD64F36092, HD64F36092G H'0000...
Page 41: Register Configuration
Section 2 CPU Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition code register (CCR). General Registers (ERn) (SP) Control Registers (CR)
Page 42: General Registers
Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers.
Page 43: Program Counter (Pc)
Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the relationship between stack pointer and the stack area. Free area SP (ER7) Stack area...
Page 44 Section 2 CPU Initial Bit Name Value Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. Undefined R/W User Bit Can be written and read by software using the LDC,...
Page 45: Data Formats
Section 2 CPU Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 46: Figure 2.5 General Register Data Formats (2)
Section 2 CPU Data Type General Data Format Register Word data Word data Longword data [Legend] ERn: General register ER General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.5 General Register Data Formats (2) Rev.
Page 47: Memory Data Formats
Section 2 CPU 2.3.2 Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address.
Page 48: Instruction Set
Section 2 CPU Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.1 Operation Notation Symbol...
Page 49: Table 2.2 Data Transfer Instructions
Section 2 CPU Symbol Description :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length Note: General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7). Table 2.2 Data Transfer Instructions Instruction Size*...
Page 50: Table 2.3 Arithmetic Operations Instructions (1)
Section 2 CPU Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register.
Page 51: Table 2.3 Arithmetic Operations Instructions (2)
Section 2 CPU Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function Rd ÷ Rs → Rd DIVXS Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
Page 52: Table 2.4 Logic Operations Instructions
Section 2 CPU Table 2.4 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 53: Table 2.6 Bit Manipulation Instructions (1)
Section 2 CPU Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 54: Table 2.6 Bit Manipulation Instructions (2)
Section 2 CPU Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ⊕...
Page 55: Table 2.7 Branch Instructions
Section 2 CPU Table 2.7 Branch Instructions Instruction Size Function Bcc* — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never C ∨...
Page 56: Table 2.8 System Control Instructions
Section 2 CPU Table 2.8 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. (EAs) → CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access.
Page 57: Basic Instruction Formats
Section 2 CPU Table 2.9 Block Data Transfer Instructions Instruction Size Function if R4L ≠ 0 then EEPMOV.B — Repeat @ER5+ → @ER6+, R4L–1 → R4L Until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W — Repeat @ER5+ → @ER6+, R4–1 →...
Page 58: Addressing Modes And Effective Address Calculation
Section 2 CPU Condition Field Specifies the branching condition of Bcc instructions. (1) Operation field only NOP, RTS, etc. (2) Operation field and register fields ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension MOV.B @(d:16, Rn), Rm EA(disp) (4) Operation field, effective address extension, and condition field EA(disp)
Page 59: Table 2.10 Addressing Modes
Section 2 CPU Table 2.10 Addressing Modes Addressing Mode Symbol Register direct Register indirect @ERn Register indirect with displacement @(d:16,ERn)/@(d:24,ERn) Register indirect with post-increment @ERn+ Register indirect with pre-decrement @–ERn Absolute address @aa:8/@aa:16/@aa:24 Immediate #xx:8/#xx:16/#xx:32 Program-counter relative @(d:8,PC)/@(d:16,PC) Memory indirect @@aa:8 Register Direct—Rn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the...
Page 60: Table 2.11 Absolute Address Access Ranges
Section 2 CPU • Register indirect with pre-decrement—@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the lower 24 bits of the result is the address of a memory operand. The result is also stored in the address register.
Page 61: Figure 2.8 Branch Address Specification In Memory Indirect Mode
Section 2 CPU Program-Counter Relative—@(d:8, PC) or @(d:16, PC) This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction.
Page 62: Effective Address Calculation
Section 2 CPU 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. Table 2.12 Effective Address Calculation (1) Addressing Mode and Instruction Format Effective Address Calculation...
Page 63: Table 2.12 Effective Address Calculation (2)
Section 2 CPU Table 2.12 Effective Address Calculation (2) Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address Sign extension Immediate Operand is immediate data. PC contents Sign extension Memory contents [Legend] r, rm,rn: Register field Operation field disp: Displacement...
Page 64: Basic Bus Cycle
Section 2 CPU Basic Bus Cycle CPU operation is synchronized by a system clock (φ) or a subclock (φ ). The period from a rising edge of φ or φ to the next rising edge is called one state. A bus cycle consists of two states or three states.
Page 65: On-Chip Peripheral Modules
Section 2 CPU 2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing states of each register, refer to section 19.1, Register Addresses (Address Order).
Page 66: Cpu States
Section 2 CPU CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode and subactive mode. For the program halt state there are a sleep mode, standby mode, and sub-sleep mode. These states are shown in figure 2.11.
Page 67: Usage Notes
Section 2 CPU Reset cleared Reset state Exception-handling state Reset occurs Reset Interrupt occurs source Reset Interrupt Exception- occurs source handling complete Program halt state Program execution state SLEEP instruction executed Figure 2.12 State Transitions Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user.
Page 68: Figure 2.13 Example Of Timer Configuration With Two Registers Allocated To Same
Section 2 CPU Bit manipulation for two registers assigned to the same address Example 1: Bit manipulation for the timer load register and timer counter (Applicable for timer B and timer C, not for the group of this LSI.) Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address.
Page 69 Section 2 CPU Example 2: The BSET instruction is executed for port 5. P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level signal at P50 with a BSET instruction is shown below.
Page 70 Section 2 CPU 3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET instruction. As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy of the PDR5 data in a work area in memory.
Page 71 Section 2 CPU Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56.
Page 72 Section 2 CPU 3. Finally, H'FE is written to PCR5 and BCLR instruction execution ends. As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However, bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins. To prevent this problem, store a copy of the PDR5 data in a work area in memory and manipulate data of the bit in the work area, then write this data to PDR5.
Page 73: Section 3 Exception Handling
Section 3 Exception Handling Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. • Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin.
Page 74 Section 3 Exception Handling Vector Relative Module Exception Sources Number Vector Address Priority Direct transition by executing the H'001A to H'001B High SLEEP instruction External interrupt IRQ0 H'001C to H'001D Low-voltage detection interrupt* IRQ1 H'001E to H'001F IRQ2 H'0020 to H'0021 IRQ3 H'0022 to H'0023 H'0024 to H'0025...
Page 75: Register Descriptions
Section 3 Exception Handling Register Descriptions Interrupts are controlled by the following registers. • Interrupt edge select register 1 (IEGR1) • Interrupt edge select register 2 (IEGR2) • Interrupt enable register 1 (IENR1) • Interrupt flag register 1 (IRR1) • Wakeup interrupt flag register (IWPR) 3.2.1 Interrupt Edge Select Register 1 (IEGR1) IEGR1 selects the direction of an edge that generates interrupt requests of pins NMI and IRQ3 to...
Page 76: Interrupt Edge Select Register 2 (Iegr2)
Section 3 Exception Handling 3.2.2 Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and WKP5 to WKP0. Initial Bit Name Value Description   7, 6 All 1 Reserved These bits are always read as 1.
Page 77: Interrupt Enable Register 1 (Ienr1)
Section 3 Exception Handling 3.2.3 Interrupt Enable Register 1 (IENR1) IENR1 enables direct transition interrupts, timer A overflow interrupts, and external pin interrupts. Initial Bit Name Value Description IENDT Direct Transfer Interrupt Enable When this bit is set to 1, direct transition interrupt requests are enabled.
Page 78: Interrupt Flag Register 1 (Irr1)
Section 3 Exception Handling 3.2.4 Interrupt Flag Register 1 (IRR1) IRR1 is a status flag register for direct transition interrupts, timer A overflow interrupts, and IRQ3 to IRQ0 interrupt requests. Initial Bit Name Value Description IRRDT Direct Transfer Interrupt Request Flag [Setting condition] When a direct transfer is made by executing a SLEEP instruction while DTON in SYSCR2 is set to 1.
Page 79: Wakeup Interrupt Flag Register (Iwpr)
Section 3 Exception Handling Initial Bit Name Value Description IRRI1 IRQ1 Interrupt Request Flag [Setting condition] When IRQ1 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IRRI1 is cleared by writing 0 IRRl0 IRQ0 Interrupt Request Flag [Setting condition]...
Page 80 Section 3 Exception Handling Initial Bit Name Value Description IWPF3 WKP3 Interrupt Request Flag [Setting condition] When WKP3 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF3 is cleared by writing 0. IWPF2 WKP2 Interrupt Request Flag [Setting condition]...
Page 81: Reset Exception Handling
Section 3 Exception Handling Reset Exception Handling When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure that this LSI is reset at power-up, hold the RES pin low until the clock pulse generator output stabilizes.
Page 82: Figure 3.1 Reset Sequence
Section 3 Exception Handling WKP5 to WKP0 Interrupts WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits WPEG5 to WPEG0 in IEGR2. When pins WKP5 to WKP0 are designated for interrupt input in PMR5 and the designated signal edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an interrupt.
Page 83: Internal Interrupts
Section 3 Exception Handling 3.4.2 Internal Interrupts Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. For timer A interrupt requests and direct transfer interrupt requests generated by execution of a SLEEP instruction, this function is included in IRR1 and IENR1.
Page 84: Interrupt Response Time
Section 3 Exception Handling Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and the stack area is in the on-chip RAM. SP – 4 SP (R7) SP – 3 SP + 1 SP –...
Page 85: Figure 3.3 Interrupt Sequence
Section 3 Exception Handling Figure 3.3 Interrupt Sequence Rev. 1.00 Aug. 28, 2006 Page 55 of 400 REJ09B0268-0100...
Page 86: Usage Notes
Section 3 Exception Handling Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset.
Page 87: Section 4 Address Break
Section 4 Address Break Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address.
Page 88: Address Break Control Register (Abrkcr)
Section 4 Address Break • Break data register (BDRH, BDRL) 4.1.1 Address Break Control Register (ABRKCR) ABRKCR sets address break conditions. Initial Bit Name Value Description RTINTE RTE Interrupt Enable When this bit is 0, the interrupt immediately after executing RTE is masked and then one instruction must be executed.
Page 89: Address Break Status Register (Abrksr)
Section 4 Address Break When an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. Table 4.1 shows the access and data bus used.
Page 90: Break Address Registers (Barh, Barl)
Section 4 Address Break 4.1.3 Break Address Registers (BARH, BARL) BARH and BARL are 16-bit read/write registers that set the address for generating an address break interrupt. When setting the address break condition to the instruction execution cycle, set the first byte address of the instruction. The initial value of this register is H'FFFF. 4.1.4 Break Data Registers (BDRH, BDRL) BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break...
Page 91: Figure 4.2 Address Break Interrupt Operation Example (1)
Section 4 Address Break Figures 4.2 show the operation examples of the address break interrupt setting. When the address break is specified in instruction execution cycle Register setting Program • ABRKCR = H'80 0258 • BAR = H'025A 025A 025C MOV.W @H'025A,R0 Underline indicates the address 0260...
Page 92 Section 4 Address Break Rev. 1.00 Aug. 28, 2006 Page 62 of 400 REJ09B0268-0100...
Page 93: Section 5 Clock Pulse Generators
Section 5 Clock Pulse Generators Section 5 Clock Pulse Generators The clock pulse generator (CPG) consists of a system clock generating circuitry, a subclock generating circuitry, and two prescalers. The system clock generating circuitry includes an external clock oscillator, a duty correction circuit, an on-chip oscillator, an RC clock divider, a clock select circuit, and a system clock divider.
Page 94: Features
Section 5 Clock Pulse Generators Features • Choice of two clock sources On-chip oscillator clock Clock by an external oscillator output • Choice of two types of RC oscillation frequency by the user software 16 MHz 20 MHz • Frequency trimming Since the initial frequency of the on-chip oscillator is within the range of two frequencies shown above, it is normally unnecessary to trim the frequency.
Page 95: Rc Control Register (Rccr)
Section 5 Clock Pulse Generators 5.2.1 RC Control Register (RCCR) RCCR controls the on-chip oscillator. Initial Bit Name Value Description RCSTP On-Chip Oscillator Standby The on-chip oscillator standby state is entered by setting this bit to 1. FSEL Frequency Select for On-chip Oscillator 0: 16 MHz 1: 20 MHz VCLSEL...
Page 96: Rc Trimming Data Protect Register (Rctrmdpr)
Section 5 Clock Pulse Generators 5.2.2 RC Trimming Data Protect Register (RCTRMDPR) RCTRMDPR controls RCTRMDPR itself and writing to RCTRMDR. Use the MOV instruction to rewrite this register. Bit manipulation instruction cannot change the settings. Initial Bit Name Value Description Write Inhibit Only when writing 0 to this bit, this register can be written to.
Page 97: Rc Trimming Data Register (Rctrmdr)
Section 5 Clock Pulse Generators Initial Bit Name Value Description Trimming Data Register Write Enable TRMDRWE This register can be written to when the LOCKDW bit is 0 and this bit is 1. [Setting condition] • When writing 0 to the WRI bit while writing 1 to the TRMDRWE bit while the PRWE bit is 1 [Clearing conditions] •...
Page 98: Clock Control/Status Register (Ckcsr)
Section 5 Clock Pulse Generators 5.2.4 Clock Control/Status Register (CKCSR) CKCSR selects the port C function, controls switching the system clocks, and indicates the system clock state. Initial Bit Name Value Description PMRC1 Port C Function Select 1 and 2 PMRC0 PMRC1 PMRC0...
Page 99 Section 5 Clock Pulse Generators Initial Bit Name Value Description OSCSEL LSI Operating Clock Select • When OSCBAKE = 0 This bit is used to forcibly select the system clock of this LSI. 0: The on-chip oscillator clock selected as the system clock source 1: The external input selected as the system clock source •...
Page 100: System Clock Select Operation
Section 5 Clock Pulse Generators Initial Bit Name Value Description CKSTA LSI Operating Clock Status 0: This LSI operates on the on-chip oscillator clock. 1: This LSI operates on the external clock. System Clock Select Operation Figure 5.2 shows the state transition of the system clock. LSI operates on on-chip oscillator clock Reset release On-chip oscillator: Operated...
Page 101: Clock Control Operation
Section 5 Clock Pulse Generators 5.3.1 Clock Control Operation The LSI system clock is generated by the on-chip oscillator clock after a reset. The system clock sources are switched from the on-chip oscillator to the external clock by the user software. Figure 5.3 shows the flowchart to switch clocks with the external clock backup function enabled.
Page 102: Figure 5.4 Flowchart Of Clock Switching With Backup Function Disabled (1) (From On-Chip Oscillator Clock To External Clock)
Section 5 Clock Pulse Generators LSI operates on on-chip oscillator clock External oscillation starts to be enabled when pins PC1 and PC0 are specified as external Start (reset) clock pins. Write 0 to bit PMRC1 to input the external clock. After writing 1 to the OSCSEL bit, this LSI Write 1 to PMRC0 in CKCSR waits until the oscillation of the external...
Page 103: Figure 5.5 Flowchart Of Clock Switching With Backup Function Disabled (2) (From External Clock To On-Chip Oscillator Clock)
Section 5 Clock Pulse Generators LSI operates on external clock When 0 is written to the OSCSEL bit, this LSI Start switches from the external clock to the on-chip (LSI operates on external clock) oscillator clock after a φ stop duration. The φ halt duration here is the duration while the φ...
Page 104: Clock Switching Timing
Section 5 Clock Pulse Generators 5.3.2 Clock Switching Timing The timing for switching clocks are shown in figures 5.6 to 5.8. φOSC φRC φ OSCSEL PHISTOP (Internal signal) CKSTA φ halt* On-chip oscillator clock operation External clock operation Wait for external oscillation settling Nwait [Legend]...
Page 105: Figure 5.7 Timing Chart To Switch From External Clock To On-Chip Oscillator Clock
Section 5 Clock Pulse Generators φOSC φRC φ OSCSEL PHISTOP (Internal signal) CKSTA CKSWIF On-chip oscillator φ halt* External RC clock operation clock operation [Legend] φOSC: External clock φRC: On-chip oscillator clock φ: System clock OSCSEL: Bit 4 in CKCSR PHISTOP: System clock stop control signal CKSTA: Bit 0 in CKCSR...
Page 106: Figure 5.8 External Oscillation Backup Timing
Section 5 Clock Pulse Generators External clock halt φOSC φRC φ OSCHLT PHISTOP (Internal signal) CKSTA CKSWIF φ halt On-chip oscillator φ halt* External clock operation clock operation detected* [Legend] φOSC: External clock φRC: On-chip oscillator clock φ: System clock OSCHLT: Bit 1 in CKCSR PHISTOP: System clock stop control signal CKSTA:...
Page 107: Trimming Of On-Chip Oscillator Frequency
Section 5 Clock Pulse Generators Trimming of On-Chip Oscillator Frequency Users can trim the on-chip oscillator clock, supplying the external reference pulses with the input capture function in internal timer W. An example of trimming flow and a timing chart are shown in figures 5.9 and 5.10, respectively.
Page 108: Figure 5.10 Timing Chart Of Trimming Of On-Chip Oscillator Frequency
Section 5 Clock Pulse Generators φRC FTIOA0 input capture input (µs) Timer W M + α M + 1 M − 1 TCNT M + α GRA_0 GRC_0 Capture 1 Capture 2 Figure 5.10 Timing Chart of Trimming of On-Chip Oscillator Frequency The on-chip oscillator frequency is gained by the expression below.
Page 109: External Clock Oscillators
Section 5 Clock Pulse Generators External Clock Oscillators There are two methods to supply external clock pulses into this LSI: connecting a crystal or ceramic resonator, and an external clock. Oscillation pins OSC1 and OSC2 are common with general ports PC0 and PC1, respectively. To set pins PC0 and PC1 as crystal resonator or external clock input ports, refer to section 5.2.4, Clock Control/Status Register (CKCSR).
Page 110: Connecting Ceramic Resonator
Section 5 Clock Pulse Generators 5.5.2 Connecting Ceramic Resonator Figure 5.13 shows an example of connecting a ceramic resonator. PC0/OSC1 C = C = 5 to 30 pF PC1/OSC2/CLKOUT Figure 5.13 Example of Connection to Ceramic Resonator 5.5.3 Inputting External Clock To use the external clock, input the external clock on pin OSC1.
Page 111: Subclock Oscillator
Section 5 Clock Pulse Generators Subclock Oscillator Figure 5.15 shows a block diagram of the subclock oscillator. 8 MΩ Note : Resistance here is a reference value. Figure 5.15 Block Diagram of Subclock Oscillator 5.6.1 Connecting 32.768-kHz Crystal Resonator Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal resonator, as shown in figure 5.16.
Page 112: Pin Connection When Not Using Subclock
Section 5 Clock Pulse Generators 5.6.2 Pin Connection when Not Using Subclock When the subclock is not used, connect pin X1 to V or V and leave pin X2 open, as shown in figure 5.18. or V Open Figure 5.18 Pin Connection when not Using Subclock Prescaler 5.7.1 Prescaler S...
Page 113: Usage Notes
Section 5 Clock Pulse Generators Usage Notes 5.8.1 Note on Resonators Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit parameters will differ depending on the resonator element, stray capacitance of the PCB, and other factors.
Page 114 Section 5 Clock Pulse Generators Rev. 1.00 Aug. 28, 2006 Page 84 of 400 REJ09B0268-0100...
Page 115: Section 6 Power-Down Modes
Section 6 Power-Down Modes Section 6 Power-Down Modes This LSI has six modes of operation after a reset. These include a normal active mode and four power-down modes, in which power consumption is significantly reduced. Module standby mode reduces power consumption by selectively halting on-chip module functions. •...
Page 116 Section 6 Power-Down Modes Initial Bit Name Value Description SSBY Software Standby This bit selects the mode to transit after the execution of the SLEEP instruction. 0: a transition is made to sleep mode or subsleep mode. 1: a transition is made to standby mode. For details, see table 6.2.
Page 117: System Control Register 2 (Syscr2)
Section 6 Power-Down Modes Table 6.1 Operating Frequency and Waiting Time STS2 STS1 STS0 Waiting Time 20 MHz 16 MHz 10 MHz 8 MHz 5 MHz 4 MHz 8,192 states 16,384 states 32,768 states 65,536 states 13.1 16.4 131,072 states 13.1 16.4 26.2...
Page 118: Module Standby Control Register 1 (Mstcr1)
Section 6 Power-Down Modes Initial Bit Name Value Description Subactive Mode Clock Select 1 and 0 These bits select the operating clock frequency in subactive and subsleep modes. The operating clock frequency changes to the set frequency after the SLEEP instruction is executed.
Page 119: Mode Transitions And States Of Lsi
Section 6 Power-Down Modes Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction.
Page 120: Table 6.2 Transition Mode After Sleep Instruction Execution And Interrupt Handling
Section 6 Power-Down Modes Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling Transition Mode after SLEEP Instruction Transition Mode due to DTON SSBY SMSEL LSON Execution Interrupt Sleep mode Active mode Subactive mode Subsleep mode Active mode Subactive mode Standby mode Active mode...
Page 121: Table 6.3 Internal State In Each Operating Mode
Section 6 Power-Down Modes Table 6.3 Internal State in Each Operating Mode Subactive Subsleep Standby Function Active Mode Sleep Mode Mode Mode Mode External clock oscillator Functioning Functioning Halted Halted Halted Subclock oscillator Functioning Functioning Functioning Functioning Functioning Instructions Functioning Halted Functioning Halted...
Page 122: Sleep Mode
Section 6 Power-Down Modes 6.2.1 Sleep Mode In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2, MA1, and MA0 bits in SYSCR2. CPU register contents are retained. When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the requested interrupt is disabled in the interrupt enable register.
Page 123: Subsleep Mode
Section 6 Power-Down Modes 6.2.3 Subsleep Mode In subsleep mode, operation of the CPU and on-chip peripheral modules other than RTC is halted. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM, and some registers of the on-chip peripheral modules are retained.
Page 124: Operating Frequency In Active Mode
Section 6 Power-Down Modes Operating Frequency in Active Mode Operation in active mode is clocked at the frequency designated by the MA2, MA1, and MA0 bits in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction execution. Direct Transition The CPU can execute programs in two modes: active and subactive mode.
Page 125: Direct Transition From Subactive Mode To Active Mode
Section 6 Power-Down Modes 6.4.2 Direct Transition from Subactive Mode to Active Mode The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2). Direct transition time = {(number of SLEEP instruction execution states) + (number of internal processing states)} ×...
Page 126 Section 6 Power-Down Modes Rev. 1.00 Aug. 28, 2006 Page 96 of 400 REJ09B0268-0100...
Page 127: Section 7 Rom
Section 7 ROM Section 7 ROM The features of the 32-kbyte or 16-kbyte flash memory built into the flash memory version are summarized below. • Programming/erase methods  The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units.
Page 128: Block Configuration
Section 7 ROM Block Configuration Figure 7.1 shows the block configuration of 32-kbyte or 16-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory of the H8/36094F is divided into 1 kbyte × 4 blocks and 28 kbytes × 1 block, and that of the H8/36092F is divided into 1 kbyte ×...
Page 129: Register Descriptions
Section 7 ROM Register Descriptions The flash memory has the following registers. • Flash memory control register 1 (FLMCR1) • Flash memory control register 2 (FLMCR2) • Erase block register 1 (EBR1) • Flash memory power control register (FLPWCR) • Flash memory enable register (FENR) 7.2.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify...
Page 130: Flash Memory Control Register 2 (Flmcr2)
Section 7 ROM Initial Bit Name Value Description Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, program- verify mode is cancelled. Erase When this bit is set to 1, and while the SWE=1 and ESU=1 bits are 1, the flash memory changes to erase mode.
Page 131: Erase Block Register 1 (Ebr1)
Section 7 ROM 7.2.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be automatically cleared to 0.
Page 132: Flash Memory Power Control Register (Flpwcr)
Section 7 ROM 7.2.4 Flash Memory Power Control Register (FLPWCR) FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. There are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in power-down mode and flash memory can be read, and mode in which even if a transition is made to subactive mode, operation of the power supply circuit of flash memory is retained and flash memory can be read.
Page 133: On-Board Programming Modes
Section 7 ROM On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode.
Page 134 Section 7 ROM 3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that of the host.
Page 135: Table 7.2 Boot Mode Operation
Section 7 ROM Table 7.2 Boot Mode Operation Host Operation Communication Contents LSI Operation Processing Contents Processing Contents Branches to boot program at reset-start. Boot program initiation H'00, H'00 . . . H'00 Continuously transmits data H'00 • Measures low-level period of receive data at specified bit rate.
Page 136: Programming/Erasing In User Program Mode
Section 7 ROM Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 9,600 bps 10 MHz 4,800 bps 7.3.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program.
Page 137: Flash Memory Programming/Erasing
Section 7 ROM Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the on- board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode.
Page 138: Figure 7.3 Program/Program-Verify Flowchart
Section 7 ROM 8. The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000. Write pulse application subroutine Apply Write Pulse START Set SWE bit in FLMCR1 WDT enable Wait 1 µs Set PSU bit in FLMCR1 Store 128-byte program data in program Wait 50 µs data area and reprogram data area...
Page 139: Erase/Erase-Verify
Section 7 ROM Table 7.4 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments Programming completed Reprogram bit — Remains in erased state Table 7.5 Additional-Program Data Computation Table Additional-Program Reprogram Data Verify Data Data Comments Additional-program bit No additional programming No additional programming No additional programming...
Page 140: Interrupt Handling When Programming/Erasing Flash Memory
Section 7 ROM 5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two bits are B'00. Verify data can be read in longwords from the address to which a dummy write was performed.
Page 141: Figure 7.4 Erase/Erase-Verify Flowchart
Section 7 ROM Erase start SWE bit ← 1 Wait 1 µs n ← 1 Set EBR1 Enable WDT ESU bit ← 1 Wait 100 µs E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 µs ESU bit ←...
Page 142: Program/Erase Protection
Section 7 ROM Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby mode.
Page 143: Programmer Mode
Section 7 ROM entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. Error protection can be cleared only by a reset. Programmer Mode In programmer mode, a PROM programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memory.
Page 144 Section 7 ROM Rev. 1.00 Aug. 28, 2006 Page 114 of 400 REJ09B0268-0100...
Page 145: Section 8 Ram
Section 8 RAM Section 8 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data. Product Classification RAM Size RAM Address Flash memory version...
Page 146 Section 8 RAM Rev. 1.00 Aug. 28, 2006 Page 116 of 400 REJ09B0268-0100...
Page 147: Section 9 I/O Ports
Section 9 I/O Ports Section 9 I/O Ports The group of this LSI has thirty-one general I/O ports and eight general input-only ports. Port 8 is a large current port, which can drive 20 mA (@V = 1.5 V) when a low level signal is output. Any of these ports can become an input port immediately after a reset.
Page 148: Port Mode Register 1 (Pmr1)
Section 9 I/O Ports 9.1.1 Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Initial Bit Name Value Description IRQ3 P17/IRQ3/TRGV Pin Function Switch This bit selects whether pin P17/IRQ3/TRGV is used as P17 or as IRQ3/TRGV.
Page 149: Port Control Register 1 (Pcr1)
Section 9 I/O Ports Initial Bit Name Value Description TMOW P10/TMOW Pin Function Switch This bit selects whether pin P10/TMOW is used as P10 or as TMOW. 0: General I/O port 1: TMOW output pin 9.1.2 Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1.
Page 150: Port Data Register 1 (Pdr1)
Section 9 I/O Ports 9.1.3 Port Data Register 1 (PDR1) PDR1 is a general I/O port data register of port 1. Initial Bit Name Value Description PDR1 stores output data for port 1 pins. If PDR1 is read while PCR1 bits are set to 1, the value stored in PDR1 are read.
Page 151: Pin Functions
Section 9 I/O Ports 9.1.5 Pin Functions The correspondence between the register specification and the port functions is shown below. • P17/IRQ3/TRGV pin Register PMR1 PCR1 Bit Name IRQ3 PCR17 Pin Function Setting value 0 P17 input pin P17 output pin IRQ3 input/TRGV input pin Legend X: Don't care.
Page 152 Section 9 I/O Ports • P14/IRQ0 pin Register PMR1 PCR1 Bit Name IRQ0 PCR14 Pin Function Setting value 0 P14 input pin P14 output pin IRQ0 input pin Legend X: Don't care. • P12 pin Register PCR1 Bit Name PCR12 Pin Function Setting value P12 input pin...
Page 153: Port 2
Section 9 I/O Ports Port 2 Port 2 is a general I/O port also functioning as a SCI3 I/O pin. Each pin of the port 2 is shown in figure 9.2. The register settings of PMR1 and SCI3 have priority for functions of the pins for both uses.
Page 154: Port Data Register 2 (Pdr2)
Section 9 I/O Ports 9.2.2 Port Data Register 2 (PDR2) PDR2 is a general I/O port data register of port 2. Initial Bit Name Value Description   7 to 3 All 1 Reserved These bits are always read as 1. PDR2 stores output data for port 2 pins.
Page 155: Port 5
Section 9 I/O Ports • P20/SCK3 pin Register SCR3 PCR2 Bit Name CKE1 CKE0 PCR20 Pin Function Setting Value P20 input pin P20 output pin SCK3 output pin SCK3 output pin SCK3 input pin Legend X: Don't care. Port 5 Port 5 is a general I/O port also functioning as an I C bus interface I/O pin, an A/D trigger input pin, wakeup interrupt input pin.
Page 156: Port Mode Register 5 (Pmr5)
Section 9 I/O Ports Port 5 has the following registers. • Port mode register 5 (PMR5) • Port control register 5 (PCR5) • Port data register 5 (PDR5) • Port pull-up control register 5 (PUCR5) 9.3.1 Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5.
Page 157: Port Control Register 5 (Pcr5)
Section 9 I/O Ports Initial Bit Name Value Description WKP1 P51/WKP1 Pin Function Switch Selects whether pin P51/WKP1 is used as P51 or as WKP1. 0: General I/O port 1: WKP1 input pin WKP0 P50/WKP0 Pin Function Switch Selects whether pin P50/WKP0 is used as P50 or as WKP0.
Page 158: Port Data Register 5 (Pdr5)
Section 9 I/O Ports 9.3.3 Port Data Register 5 (PDR5) PDR5 is a general I/O port data register of port 5. Initial Bit Name Value Description Stores output data for port 5 pins. If PDR5 is read while PCR5 bits are set to 1, the value stored in PDR5 are read.
Page 159: Pin Functions
Section 9 I/O Ports 9.3.5 Pin Functions The correspondence between the register specification and the port functions is shown below. • P57/SCL pin Register ICCR1 PCR5 Bit Name PCR57 Pin Function Setting Value 0 P57 input pin P57 output pin SCL I/O pin Legend X: Don't care.
Page 160 Section 9 I/O Ports • P54/WKP4 pin Register PMR5 PCR5 Bit Name WKP4 PCR54 Pin Function Setting Value 0 P54 input pin P54 output pin WKP4 input pin Legend X: Don't care. • P53/WKP3 pin Register PMR5 PCR5 Bit Name WKP3 PCR53 Pin Function...
Page 161: Port 7
Section 9 I/O Ports • P50/WKP0 pin Register PMR5 PCR5 Bit Name WKP0 PCR50 Pin Function Setting Value 0 P50 input pin P50 output pin WKP0 input pin Legend X: Don't care. Port 7 Port 7 is a general I/O port also functioning as a timer V I/O pin. Each pin of the port 7 is shown in figure 9.4.
Page 162: Port Control Register 7 (Pcr7)
Section 9 I/O Ports 9.4.1 Port Control Register 7 (PCR7) PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7. Initial Bit Name Value Description    Reserved PCR76 Setting a PCR7 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an PCR75 input port.
Page 163: Pin Functions
Section 9 I/O Ports 9.4.3 Pin Functions The correspondence between the register specification and the port functions is shown below. • P76/TMOV pin Register TCSRV PCR7 Bit Name OS3 to OS0 PCR76 Pin Function Setting Value 0000 P76 input pin P76 output pin Other than TMOV output pin...
Page 164: Port 8
Section 9 I/O Ports Port 8 Port 8 is a general I/O port also functioning as a timer W I/O pin. Each pin of the port 8 is shown in figure 9.5. The register setting of the timer W has priority for functions of the pins P84/FTIOD, P83/FTIOC, P82/FTIOB, and P81/FTIOA.
Page 165: Port Control Register 8 (Pcr8)
Section 9 I/O Ports 9.5.1 Port Control Register 8 (PCR8) PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8. Initial Bit Name Value Description PCR87 When each of the port 8 pins P87 to P80 functions as an general I/O port, setting a PCR8 bit to 1 makes the PCR86 corresponding pin an output port, while clearing the bit to...
Page 166: Pin Functions
Section 9 I/O Ports 9.5.3 Pin Functions The correspondence between the register specification and the port functions is shown below. • P87 pin Register PCR8 Bit Name PCR87 Pin Function Setting Value 0 P87 input pin P87 output pin • P86 pin Register PCR8 Bit Name...
Page 167 Section 9 I/O Ports • P84/FTIOD pin Register TMRW TIOR1 PCR8 Bit Name RWMD IOD2 IOD1 IOD0 PCR84 Pin Function Setting Value 0 P84 input/FTIOD input pin P84 output/FTIOD input FTIOD output pin FTIOD output pin P84 input/FTIOD input pin P84 output/FTIOD input PWM output Legend X: Don't care.
Page 168 Section 9 I/O Ports • P82/FTIOB pin Register TMRW TIOR0 PCR8 Bit Name RWMB IOB2 IOB1 IOB0 PCR82 Pin Function Setting Value 0 P82 input/FTIOB input P82 output/FTIOB input FTIOB output pin FTIOB output pin P82 input/FTIOB input P82 output/FTIOB input PWM output Legend X: Don't care.
Page 169: Port B
Section 9 I/O Ports Port B Port B is an input port also functioning as an A/D converter analog input pin. Each pin of the port B is shown in figure 9.6. PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 Port B PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 Figure 9.6 Port B Pin Configuration...
Page 170: Port C
Section 9 I/O Ports Port C Port C is a general I/O port also functioning as an external oscillation pin and clock output pin. Each pin of the port C is shown in figure 9.7. The register setting of CKCSR has priority for functions of the pins for both uses.
Page 171: Port Data Register C (Pdrc)
Section 9 I/O Ports 9.7.2 Port Data Register C (PDRC) PDRC is a general I/O port data register of port C. Initial Bit Name Value Description    7 to 2 Reserved These bits store output data for port C pins. If PDRC is read while PCRC bits are set to 1, the value stored in PDRC is read.
Page 172 Section 9 I/O Ports Rev. 1.00 Aug. 28, 2006 Page 142 of 400 REJ09B0268-0100...
Page 173: Section 10 Timer A
Section 10 Timer A Section 10 Timer A Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768kHz crystal oscillator is connected. Figure 10.1 shows a block diagram of timer A. 10.1 Features •...
Page 174: Input/Output Pins
Section 10 Timer A ø ø ø ø ø ø /128 ø TMOW ø ø/8192, ø/4096, ø ø/2048, ø/512, ø ø/256, ø/128, ø ø/32, ø/8 ø IRRTA [Legend] TMA: Timer mode register A TCA: Timer counter A IRRTA: Timer A overflow interrupt request flag PSW: Prescaler W PSS: Prescaler S...
Page 175: Register Descriptions
Section 10 Timer A 10.3 Register Descriptions Timer A has the following registers. • Timer mode register A (TMA) • Timer counter A (TCA) 10.3.1 Timer Mode Register A (TMA) TMA selects the operating mode, the divided clock output, and the input clock. Initial Bit Name Value...
Page 176: Timer Counter A (Tca)
Section 10 Timer A Initial Bit Name Value Description TMA2 Internal Clock Select 2 to 0 TMA1 These bits select the clock input to TCA when TMA3 = 0. 000: φ/8192 TMA0 001: φ/4096 010: φ/2048 011: φ/512 100: φ/256 101: φ/128 110: φ/32 111: φ/8...
Page 177: Operation
Section 10 Timer A 10.4 Operation 10.4.1 Interval Timer Operation When bit TMA3 in TMA is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting of timer A resume immediately as an interval timer.
Page 178 Section 10 Timer A Rev. 1.00 Aug. 28, 2006 Page 148 of 400 REJ09B0268-0100...
Page 179: Section 11 Timer V
Section 11 Timer V Section 11 Timer V Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Compare- match signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle.
Page 180 Section 11 Timer V TCRV1 TCORB Trigger TRGV control Comparator Clock select TMCIV TCNTV Comparator ø TCORA Clear TCRV0 TMRIV control Interrupt request control Output TMOV TCSRV control CMIA CMIB [Legend] TCORA: Time constant register A TCORB: Time constant register B TCNTV: Timer counter V TCSRV: Timer control/status register V TCRV0: Timer control register V0...
Page 181: Input/Output Pins
Section 11 Timer V 11.2 Input/Output Pins Table 11.1 shows the timer V pin configuration. Table 11.1 Pin Configuration Name Abbreviation I/O Function Timer V output TMOV Output Timer V waveform output Timer V clock input TMCIV Input Clock input to TCNTV Timer V reset input TMRIV Input...
Page 182: Time Constant Registers A And B (Tcora, Tcorb)
Section 11 Timer V 11.3.2 Time Constant Registers A and B (TCORA, TCORB) TCORA and TCORB have the same function. TCORA and TCORB are 8-bit read/write registers. TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match, CMFA is set to 1 in TCSRV.
Page 183: Table 11.2 Clock Signals To Input To Tcntv And Counting Conditions
Section 11 Timer V Initial Bit Name Value Description CKS2 Clock Select 2 to 0 CKS1 These bits select clock signals to input to TCNTV and the counting condition in combination with ICKS0 in TCRV1. CKS0 Refer to table 11.2. Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions TCRV0 TCRV1...
Page 184: Timer Control/Status Register V (Tcsrv)
Section 11 Timer V 11.3.4 Timer Control/Status Register V (TCSRV) TCSRV indicates the status flag and controls outputs by using a compare match. Initial Bit Name Value Description CMFB Compare Match Flag B Setting condition: When the TCNTV value matches the TCORB value Clearing condition: After reading CMFB = 1, cleared by writing 0 to CMFB CMFA...
Page 185: Timer Control Register V1 (Tcrv1)
Section 11 Timer V Initial Bit Name Value Description Output Select 1 and 0 These bits select an output method for the TMOV pin by the compare match of TCORA and TCNTV. 00: No change 01: 0 output 10: 1 output 11: Output toggles OS3 and OS2 select the output level for compare match B.
Page 186: Operation
Section 11 Timer V Initial Bit Name Value Description   Reserved This bit is always read as 1. ICKS0 Internal Clock Select 0 This bit selects clock signals to input to TCNTV in combination with CKS2 to CKS0 in TCRV0. Refer to table 11.2.
Page 187: Figure 11.2 Increment Timing With Internal Clock
Section 11 Timer V ø Internal clock TCNTV input clock N – 1 N + 1 TCNTV Figure 11.2 Increment Timing with Internal Clock ø TMCIV (External clock input pin) TCNTV input clock N – 1 N + 1 TCNTV Figure 11.3 Increment Timing with External Clock ø...
Page 188: Figure 11.5 Cmfa And Cmfb Set Timing
Section 11 Timer V ø TCNTV TCORA or TCORB Compare match signal CMFA or CMFB Figure 11.5 CMFA and CMFB Set Timing ø Compare match A signal Timer V output Figure 11.6 TMOV Output Timing ø Compare match A signal H'00 TCNTV Figure 11.7 Clear Timing by Compare Match...
Page 189: Timer V Application Examples
Section 11 Timer V ø TMRIV(External counter reset input pin ) TCNTV reset signal N – 1 H'00 TCNTV Figure 11.8 Clear Timing by TMRIV Input 11.5 Timer V Application Examples 11.5.1 Pulse Output with Arbitrary Duty Cycle Figure 11.9 shows an example of output of pulses with an arbitrary duty cycle. 1.
Page 190: Pulse Output With Arbitrary Pulse Width And Delay From Trgv Input
Section 11 Timer V 11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 11.10. To set up this output: 1.
Page 191: Usage Notes
Section 11 Timer V 11.6 Usage Notes The following types of contention or operation can occur in timer V operation. 1. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 11.11, clearing takes precedence and the write to the counter is not carried out.
Page 192: Figure 11.12 Contention Between Tcora Write And Compare Match
Section 11 Timer V TCORA write cycle by CPU ø TCORA address Address Internal write signal TCNTV TCORA TCORA write data Compare match signal Inhibited Figure 11.12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV Write to CKS1 and CKS0...
Page 193: Section 12 Timer W
Section 12 Timer W Section 12 Timer W The timer W has a 16-bit timer having output compare and input capture functions. The timer W can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers.
Page 194: Table 12.1 Timer W Functions
Section 12 Timer W Table 12.1 Timer W Functions Input/Output Pins Item Counter FTIOA FTIOB FTIOC FTIOD Internal clocks: φ, φ/2, φ/4, φ/8 Count clock External clock: FTCI General registers Period GRC (buffer GRD (buffer (output compare/input specified in register for register for capture registers) GRA in...
Page 195: Figure 12.1 Timer W Block Diagram
Section 12 Timer W Internal clock: ø FTIOA ø/2 Clock FTIOB ø/4 selector ø/8 FTIOC Control logic External clock: FTCI FTIOD Comparator IRRTW Internal data bus [Legend] TMRW: Timer mode register W (8 bits) TCRW: Timer control register W (8 bits) TIERW: Timer interrupt enable register W (8 bits) TSRW: Timer status register W (8 bits)
Page 196: Input/Output Pins
Section 12 Timer W 12.2 Input/Output Pins Table 12.2 summarizes the timer W pins. Table 12.2 Pin Configuration Name Abbreviation Input/Output Function External clock input FTCI Input External clock input pin Input capture/output FTIOA Input/output Output pin for GRA output compare compare A or input pin for GRA input capture Input capture/output...
Page 197: Timer Mode Register W (Tmrw)
Section 12 Timer W 12.3.1 Timer Mode Register W (TMRW) TMRW selects the general register functions and the timer output mode. Initial Bit Name Value Description Counter Start The counter operation is halted when this bit is 0, while it can be performed when this bit is 1.
Page 198: Timer Control Register W (Tcrw)
Section 12 Timer W 12.3.2 Timer Control Register W (TCRW) TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer output levels. Initial Bit Name Value Description CCLR Counter Clear The TCNT value is cleared by compare match A when this bit is 1.
Page 199: Timer Interrupt Enable Register W (Tierw)
Section 12 Timer W Initial Bit Name Value Description Timer Output Level Setting A Sets the output value of the FTIOA pin until the first compare match A is generated. 0: Output value is 0* 1: Output value is 1* Legend X: Don't care.
Page 200: Timer Status Register W (Tsrw)
Section 12 Timer W 12.3.4 Timer Status Register W (TSRW) TSRW shows the status of interrupt requests. Initial Bit Name Value Description Timer Overflow Flag [Setting condition] When TCNT overflows from H'FFFF to H'0000 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF ...
Page 201: Timer I/O Control Register 0 (Tior0)
Section 12 Timer W Initial Bit Name Value Description IMFB Input Capture/Compare Match Flag B [Setting conditions] • TCNT = GRB when GRB functions as an output compare register • The TCNT value is transferred to GRB by an input capture signal when GRB functions as an input capture register [Clearing condition]...
Page 202 Section 12 Timer W Initial Bit Name Value Description IOB1 I/O Control B1 and B0 IOB0 When IOB2 = 0, 00: No output at compare match 01: 0 output to the FTIOB pin at GRB compare match 10: 1 output to the FTIOB pin at GRB compare match 11: Output toggles to the FTIOB pin at GRB compare match When IOB2 = 1,...
Page 203: Timer I/O Control Register 1 (Tior1)
Section 12 Timer W 12.3.6 Timer I/O Control Register 1 (TIOR1) TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and FTIOD pins. Initial Bit Name Value Description   Reserved This bit is always read as 1. IOD2 I/O Control D2 Selects the GRD function.
Page 204: Timer Counter (Tcnt)
Section 12 Timer W Initial Bit Name Value Description IOC1 I/O Control C1 and C0 IOC0 When IOC2 = 0, 00: No output at compare match 01: 0 output to the FTIOC pin at GRC compare match 10: 1 output to the FTIOC pin at GRC compare match 11: Output toggles to the FTIOC pin at GRC compare match When IOC2 = 1,...
Page 205: General Registers A To D (Gra To Grd)
Section 12 Timer W 12.3.8 General Registers A to D (GRA to GRD) Each general register is a 16-bit readable/writable register that can function as either an output- compare register or an input-capture register. The function is selected by settings in TIOR0 and TIOR1.
Page 206: Operation
Section 12 Timer W 12.4 Operation The timer W has the following operating modes. • Normal Operation • PWM Operation 12.4.1 Normal Operation TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a free- running counter. When the CTS bit in TMRW is set to 1, TCNT starts incrementing the count. When the count overflows from H'FFFF to H'0000, the OVF flag in TSRW is set to 1.
Page 207: Figure 12.3 Periodic Counter Operation
Section 12 Timer W Periodic counting operation can be performed when GRA is set as an output compare register and bit CCLR in TCRW is set to 1. When the count matches GRA, TCNT is cleared to H'0000, the IMFA flag in TSRW is set to 1. If the corresponding IMIEA bit in TIERW is set to 1, an interrupt request is generated.
Page 208: Figure 12.5 Toggle Output Example (Toa = 0, Tob = 1)
Section 12 Timer W Figure 12.5 shows an example of toggle output when TCNT operates as a free-running counter, and toggle output is selected for both compare match A and B. TCNT value H'FFFF Time H'0000 Toggle output FTIOA Toggle output FTIOB Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1) Figure 12.6 shows another example of toggle output when TCNT operates as a periodic counter,...
Page 209: Figure 12.7 Input Capture Operating Example
Section 12 Timer W The TCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when a signal level changes at an input-capture pin (FTIOA, FTIOB, FTIOC, or FTIOD). Capture can take place on the rising edge, falling edge, or both edges. By using the input-capture function, the pulse width and periods can be measured.
Page 210: Figure 12.8 Buffer Operation Example (Input Capture)
Section 12 Timer W Figure 12.8 shows an example of buffer operation when the GRA is set as an input-capture register and GRC is set as the buffer register for GRA. TCNT operates as a free-running counter, and FTIOA captures both rising and falling edge of the input signal. Due to the buffer operation, the GRA value is transferred to GRC by input-capture A and the TCNT value is stored in GRA.
Page 211: Pwm Operation
Section 12 Timer W 12.4.2 PWM Operation In PWM mode, PWM waveforms are generated by using GRA as the period register and GRB, GRC, and GRD as duty registers. PWM waveforms are output from the FTIOB, FTIOC, and FTIOD pins. Up to three-phase PWM waveforms can be output. In PWM mode, a general register functions as an output compare register automatically.
Page 212: Figure 12.10 Pwm Mode Example (2)
Section 12 Timer W Figure 12.10 shows another example of operation in PWM mode. The output signals go to 0 and TCNT is cleared at compare match A, and the output signals go to 1 at compare match B, C, and D (TOB, TOC, and TOD = 0: initial output values are set to 1).
Page 213: Figure 12.11 Buffer Operation Example (Output Compare)
Section 12 Timer W Figure 12.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB outputs 1 at compare match B and 0 at compare match A.
Page 214: Figure 12.12 Pwm Mode Example (Tob, Toc, And Tod = 0: Initial Output Values Are Set To 0)
Section 12 Timer W Figures 12.12 and 12.13 show examples of the output of PWM waveforms with duty cycles of 0% and 100%. TCNT value Write to GRB Write to GRB H'0000 Time Duty 0% FTIOB Output does not change when cycle register and duty register compare matches occur TCNT value simultaneously.
Page 215: Figure 12.13 Pwm Mode Example (Tob, Toc, And Tod = 1: Initial Output Values Are Set To 1)
Section 12 Timer W TCNT value Write to GRB Write to GRB H'0000 Time Duty 100% FTIOB Output does not change when cycle register and duty register compare matches occur TCNT value simultaneously. Write to GRB Write to GRB Write to GRB H'0000 Time Duty 0%...
Page 216: Operation Timing
Section 12 Timer W 12.5 Operation Timing 12.5.1 TCNT Count Timing Figure 12.14 shows the TCNT count timing when the internal clock source is selected. Figure 12.15 shows the timing when the external clock source is selected. The pulse width of the external clock signal must be at least two system clock (φ) cycles;...
Page 217: Input Capture Timing
Section 12 Timer W Figure 12.16 shows the output compare timing. φ TCNT input clock TCNT GRA to GRD Compare match signal FTIOA to FTIOD Figure 12.16 Output Compare Output Timing 12.5.3 Input Capture Timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR0 and TIOR1.
Page 218: Timing Of Counter Clearing By Compare Match
Section 12 Timer W 12.5.4 Timing of Counter Clearing by Compare Match Figure 12.18 shows the timing when the counter is cleared by compare match A. When the GRA value is N, the counter counts from 0 to N, and its cycle is N + 1. φ...
Page 219: Timing Of Imfa To Imfd Flag Setting At Compare Match
Section 12 Timer W φ Input capture signal TCNT GRA, GRB GRC, GRD Figure 12.20 Buffer Operation Timing (Input Capture) 12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general register.
Page 220: Timing Of Imfa To Imfd Setting At Input Capture
Section 12 Timer W 12.5.7 Timing of IMFA to IMFD Setting at Input Capture If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure 12.22 shows the timing of the IMFA to IMFD flag setting at input capture.
Page 221: Usage Notes
Section 12 Timer W 12.6 Usage Notes The following types of contention or operation can occur in timer W operation. 1. The pulse width of the input clock signal and the input capture signal must be at least two system clock (φ) cycles; shorter pulses will not be detected correctly. 2.
Page 222: Figure 12.25 Internal Clock Switching And Tcnt Operation
Section 12 Timer W Previous clock New clock Count clock TCNT The change in signal level at clock switching is assumed to be a rising edge, and TCNT increments the count. Figure 12.25 Internal Clock Switching and TCNT Operation 5. The TOA to TOD bits in TCRW decide the value of the FTIO pin, which is output until the first compare match occurs.
Page 223: Figure 12.26 When Compare Match And Bit Manipulation Instruction To Tcrw Occur At The Same Timing
Section 12 Timer W TCRW has been set to H'06. Compare match B and compare match C are used. The FTIOB pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match B. When BCLR#2, @TCRW is executed to clear the TOC bit (the FTIOC signal is low) and compare match B occurs at the same timing as shown below, the H'02 writing to TCRW has priority and compare match B does not drive the FTIOB signal low;...
Page 224 Section 12 Timer W Rev. 1.00 Aug. 28, 2006 Page 194 of 400 REJ09B0268-0100...
Page 225: Section 13 Watchdog Timer
Section 13 Watchdog Timer Section 13 Watchdog Timer The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. The block diagram of the watchdog timer is shown in figure 13.1.
Page 226: Register Descriptions
Section 13 Watchdog Timer 13.2 Register Descriptions The watchdog timer has the following registers. • Timer control/status register WD (TCSRWD) • Timer counter WD (TCWD) • Timer mode register WD (TMWD) 13.2.1 Timer Control/Status Register WD (TCSRWD) TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the watchdog timer operation and indicates the operating state.
Page 227: Timer Counter Wd (Tcwd)
Section 13 Watchdog Timer Initial Bit Name Value Description WDON Watchdog Timer On TCWD starts counting up when WDON is set to 1 and halts when WDON is cleared to 0. [Setting condition] When 1 is written to the WDON bit while writing 0 to the B2WI bit when the TCSRWE bit=1 [Clearing condition] Reset by RES pin...
Page 228: Timer Mode Register Wd (Tmwd)
Section 13 Watchdog Timer 13.2.3 Timer Mode Register WD (TMWD) TMWD selects the input clock. Initial Bit Name Value Description   7 to 4 All 1 Reserved These bits are always read as 1. CKS3 Clock Select 3 to 0 CKS2 Select the clock to be input to TCWD.
Page 229: Operation
Section 13 Watchdog Timer 13.3 Operation The watchdog timer is provided with an 8-bit counter. If 1 is written to WDON while writing 0 to B2WI when the TCSRWE bit in TCSRWD is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write accesses to TCSRWD are required.) When a clock pulse is input after the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset signal is generated.
Page 230 Section 13 Watchdog Timer Rev. 1.00 Aug. 28, 2006 Page 200 of 400 REJ09B0268-0100...
Page 231: Section 14 Serial Communication Interface 3 (Sci3)
Section 14 Serial Communication Interface 3 (SCI3) Section 14 Serial Communication Interface 3 (SCI3) Serial Communication Interface 3 (SCI3) can handle both asynchronous and clocked synchronous serial communication. In the asynchronous method, serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA).
Page 232: Figure 14.1 Block Diagram Of Sci3
Section 14 Serial Communication Interface 3 (SCI3) Internal clock (ø/64, ø/16, ø/4, ø) External SCK 3 clock Baud rate generator Clock Transmit/receive SCR3 control circuit Interrupt request (TEI, TXI, RXI, ERI) [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR:...
Page 233: Input/Output Pins
Section 14 Serial Communication Interface 3 (SCI3) 14.2 Input/Output Pins Table 14.1 shows the SCI3 pin configuration. Table 14.1 Pin Configuration Pin Name Abbreviation Function SCI3 clock SCK3 SCI3 clock input/output SCI3 receive data input Input SCI3 receive data input SCI3 transmit data output Output SCI3 transmit data output...
Page 234: Receive Shift Register (Rsr)
Section 14 Serial Communication Interface 3 (SCI3) 14.3.1 Receive Shift Register (RSR) RSR is a shift register that is used to receive serial data input from the RxD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU.
Page 235: Serial Mode Register (Smr)
Section 14 Serial Communication Interface 3 (SCI3) 14.3.5 Serial Mode Register (SMR) SMR is used to set the SCI3’s serial transfer format and select the on-chip baud rate generator clock source. Initial Bit Name Value Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length.
Page 236: Serial Control Register 3 (Scr3)
Section 14 Serial Communication Interface 3 (SCI3) Initial Bit Name Value Description CKS1 Clock Select 0 and 1 CKS0 These bits select the clock source for the on-chip baud rate generator. 00: φ clock (n = 0) 01: φ/4 clock (n = 1) 10: φ/16 clock (n = 2) 11: φ/64 clock (n = 3) For the relationship between the bit rate register setting...
Page 237 Section 14 Serial Communication Interface 3 (SCI3) Initial Bit Name Value Description MPIE Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and OER status flags in SSR is prohibited.
Page 238: Serial Status Register (Ssr)
Section 14 Serial Communication Interface 3 (SCI3) 14.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. Initial Bit Name Value...
Page 239 Section 14 Serial Communication Interface 3 (SCI3) Initial Bit Name Value Description Parity Error [Setting condition] • When a parity error is generated during reception [Clearing condition] • When 0 is written to PER after reading PER = 1 TEND Transmit End [Setting conditions] •...
Page 240: Bit Rate Register (Brr)
Section 14 Serial Communication Interface 3 (SCI3) 14.3.8 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 14.2 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in asynchronous mode.
Page 241: Table 14.2 Examples Of Brr Settings For Various Bit Rates (Asynchronous Mode) (1)
Section 14 Serial Communication Interface 3 (SCI3) Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency φ (MHz) 4.9152 Bit Rate (bits/s) Error (%) Error (%) Error (%) 0.03 0.31 –0.25 0.16 0.00 0.16 0.16 0.00 0.16...
Page 242: Table 14.2 Examples Of Brr Settings For Various Bit Rates (Asynchronous Mode) (2)
Section 14 Serial Communication Interface 3 (SCI3) Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency φ (MHz) 9.8304 12.888 Bit Rate Error Error Error Error (bit/s) –0.26 –0.25 0.03 0.08 0.00 0.16 0.16 0.00 0.00 0.16...
Page 243: Table 14.3 Maximum Bit Rate For Each Frequency (Asynchronous Mode)
Section 14 Serial Communication Interface 3 (SCI3) Table 14.3 Maximum Bit Rate for Each Frequency (Asynchronous Mode) Maximum Bit Maximum Bit φ (MHz) φ (MHz) Rate (bit/s) Rate (bit/s) 125000 375000 4.9152 153600 12.288 384000 156250 437500 187500 14.7456 460800 6.144 192000 500000...
Page 244: Table 14.4 Examples Of Bbr Setting For Various Bit Rates (Clocked Synchronous Mode)
Section 14 Serial Communication Interface 3 (SCI3) Table 14.4 Examples of BBR Setting for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) Bit Rate (bit/s) — — — — — — — — — — — — — —...
Page 245: Operation In Asynchronous Mode
Section 14 Serial Communication Interface 3 (SCI3) 14.4 Operation in Asynchronous Mode Figure 14.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level).
Page 246: Sci3 Initialization
Section 14 Serial Communication Interface 3 (SCI3) 14.4.2 SCI3 Initialization Follow the flowchart as shown in figure 14.4 to initialize the SCI3. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the contents of RDR.
Page 247: Data Transmission
Section 14 Serial Communication Interface 3 (SCI3) 14.4.3 Data Transmission Figure 14.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 248: Figure 14.6 Sample Serial Transmission Flowchart (Asynchronous Mode)
Section 14 Serial Communication Interface 3 (SCI3) Start transmission [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is Read TDRE flag in SSR written to TDR, the TDRE flag is automaticaly cleared to 0.
Page 249: Serial Data Reception
Section 14 Serial Communication Interface 3 (SCI3) 14.4.4 Serial Data Reception Figure 14.7 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives data in RSR, and checks the parity bit and stop bit.
Page 250: Table 14.5 Ssr Status Flags And Receive Data Handling
Section 14 Serial Communication Interface 3 (SCI3) Table 14.5 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1.
Page 251: Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (1)
Section 14 Serial Communication Interface 3 (SCI3) [1] Read the OER, PER, and FER flags in Start reception SSR to identify the error. If a receive error occurs, performs the appropriate error processing. Read OER, PER, and [2] Read SSR and check that RDRF = 1, FER flags in SSR then read the receive data in RDR.
Page 252: Figure 14.8 Sample Serial Reception Data Flowchart (2)
Section 14 Serial Communication Interface 3 (SCI3) Error processing OER = 1 Overrun error processing FER = 1 Break? Framing error processing PER = 1 Parity error processing Clear OER, PER, and FER flags in SSR to 0 <End> Figure 14.8 Sample Serial Reception Data Flowchart (2) Rev.
Page 253: Operation In Clocked Synchronous Mode
Section 14 Serial Communication Interface 3 (SCI3) 14.5 Operation in Clocked Synchronous Mode Figure 14.9 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next.
Page 254: Sci3 Initialization
Section 14 Serial Communication Interface 3 (SCI3) 14.5.2 SCI3 Initialization Before transmitting and receiving data, the SCI3 should be initialized as described in a sample flowchart in figure 14.4. 14.5.3 Serial Data Transmission Figure 14.10 shows an example of SCI3 operation for transmission in clocked synchronous mode. In serial transmission, the SCI3 operates as described below.
Page 255: Figure 14.10 Example Of Sci3 Operation In Transmission In Clocked Synchronous Mode
Section 14 Serial Communication Interface 3 (SCI3) Serial clock Serial Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 data 1 frame 1 frame TDRE TEND TXI interrupt TDRE flag TXI interrupt request generated TEI interrupt request operation request cleared...
Page 256: Figure 14.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)
Section 14 Serial Communication Interface 3 (SCI3) Start transmission Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag Read TDRE flag in SSR is automatically cleared to 0 and clocks are output to start the data transmission.
Page 257: Serial Data Reception (Clocked Synchronous Mode)
Section 14 Serial Communication Interface 3 (SCI3) 14.5.4 Serial Data Reception (Clocked Synchronous Mode) Figure 14.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 performs internal initialization synchronous with a synchronous clock input or output, starts receiving data.
Page 258: Figure 14.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)
Section 14 Serial Communication Interface 3 (SCI3) Start reception Read the OER flag in SSR to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Read OER flag in SSR Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR.
Page 259: Simultaneous Serial Data Transmission And Reception
Section 14 Serial Communication Interface 3 (SCI3) 14.5.5 Simultaneous Serial Data Transmission and Reception Figure 14.14 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations.
Page 260: Figure 14.14 Sample Flowchart Of Simultaneous Serial Transmit And Receive Operations (Clocked Synchronous Mode)
Section 14 Serial Communication Interface 3 (SCI3) Start transmission/reception [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the Read TDRE flag in SSR TDRE flag is automatically cleared to [2] Read SSR and check that the RDRF TDRE = 1...
Page 261: Multiprocessor Communication Function
Section 14 Serial Communication Interface 3 (SCI3) 14.6 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code.
Page 262: Figure 14.15 Example Of Communication Using Multiprocessor Format (Transmission Of Data H'aa To Receiving Station A)
Section 14 Serial Communication Interface 3 (SCI3) Transmitting station Serial transmission line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle =...
Page 263: Multiprocessor Serial Data Transmission
Section 14 Serial Communication Interface 3 (SCI3) 14.6.1 Multiprocessor Serial Data Transmission Figure 14.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission.
Page 264: Multiprocessor Serial Data Reception
Section 14 Serial Communication Interface 3 (SCI3) 14.6.2 Multiprocessor Serial Data Reception Figure 14.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR.
Page 265: Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (1)
Section 14 Serial Communication Interface 3 (SCI3) Set the MPIE bit in SCR3 to 1. Start reception Read OER and FER in SSR to check for errors. Receive error processing is performed Set MPIE bit in SCR3 to 1 in cases where a receive error occurs. Read SSR and check that the RDRF flag is Read OER and FER flags in SSR set to 1, then read the receive data in RDR...
Page 266: Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2)
Section 14 Serial Communication Interface 3 (SCI3) Error processing OER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear OER, and FER flags in SSR to 0 <End> Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2) Rev.
Page 267: Figure 14.18 Example Of Sci3 Operation In Reception Using Multiprocessor Format (Example With 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Section 14 Serial Communication Interface 3 (SCI3) Start Receive Stop Start Receive data Stop Mark state data (ID1) (Data1) (idle state) Serial data 1 frame 1 frame MPIE RDRF value RXI interrupt RDRF flag RXI interrupt request operation request cleared is not generated, and MPIE cleared to 0...
Page 268: Interrupts
Section 14 Serial Communication Interface 3 (SCI3) 14.7 Interrupts The SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 14.6 shows the interrupt sources. Table 14.6 SCI3 Interrupt Requests Interrupt Requests Abbreviation...
Page 269: Mark State And Break Sending
Section 14 Serial Communication Interface 3 (SCI3) 14.8.2 Mark State and Break Sending When the TXD bit in PMR1 is 1, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by PCR and PDR. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission.
Page 270: Figure 14.19 Receive Data Sampling Timing In Asynchronous Mode
Section 14 Serial Communication Interface 3 (SCI3) Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula. M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design.
Page 271: Section 15 I C Bus Interface 2 (Iic2)
Section 15 I C Bus Interface 2 (IIC2) Section 15 I C Bus Interface 2 (IIC2) The I C bus interface 2 conforms to and provides a subset of the Philips I C bus (inter-IC bus) interface functions. The register configuration that controls the I C bus differs partly from the Philips configuration, however.
Page 272: Figure 15.1 Block Diagram Of I
Section 15 I C Bus Interface 2 (IIC2) Transfer clock generation circuit Transmission/ ICCR1 reception control circuit Output ICCR2 control ICMR Noise canceler ICDRT Output ICDRS control Address Noise canceler comparator ICDRR Bus state decision circuit Arbitration ICSR decision circuit ICIER Interrupt Interrupt request...
Page 273: Input/Output Pins
Section 15 I C Bus Interface 2 (IIC2) SCL in SCL out SDA in SDA out (Master) SCL in SCL in SCL out SCL out SDA in SDA in SDA out SDA out (Slave 1) (Slave 2) Figure 15.2 External Circuit Connections of I/O Pins 15.2 Input/Output Pins Table 15.1 summarizes the input/output pins used by the I...
Page 274: Register Descriptions
Section 15 I C Bus Interface 2 (IIC2) 15.3 Register Descriptions The I C bus interface 2 has the following registers: • I C bus control register 1 (ICCR1) • I C bus control register 2 (ICCR2) • I C bus mode register (ICMR) •...
Page 275 Section 15 I C Bus Interface 2 (IIC2) Initial Bit Name Value Description Master/Slave Select Transmit/Receive Select In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode.
Page 276: Table 15.2 Transfer Rate
Section 15 I C Bus Interface 2 (IIC2) Table 15.2 Transfer Rate Bit 3 Bit 2 Bit 1 Bit 0 Transfer Rate φ=5 MHz φ=8 MHz φ=10 MHz φ=16 MHz φ=20 MHz CKS3 CKS2 CKS1 CKS0 Clock φ/28 179 kHz 286 kHz 357 kHz 571 kHz...
Page 277: C Bus Control Register 2 (Iccr2)
Section 15 I C Bus Interface 2 (IIC2) 15.3.2 C Bus Control Register 2 (ICCR2) ICCR1 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in the control part of the I C bus interface 2. Initial Bit Name Value...
Page 278 Section 15 I C Bus Interface 2 (IIC2) Initial Bit Name Value Description SDAOP SDAO Write Protect This bit controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0 by the MOV instruction.
Page 279: C Bus Mode Register (Icmr)
Section 15 I C Bus Interface 2 (IIC2) 15.3.3 C Bus Mode Register (ICMR) ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the transfer bit count. Initial Bit Name Value Description MSB-First/LSB-First Select 0: MSB-first 1: LSB-first...
Page 280 Section 15 I C Bus Interface 2 (IIC2) Initial Bit Name Value Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits is indicated. With the I C bus format, the data is transferred with one addition acknowledge bit.
Page 281: C Bus Interrupt Enable Register (Icier)
Section 15 I C Bus Interface 2 (IIC2) 15.3.4 C Bus Interrupt Enable Register (ICIER) ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received. Initial Bit Name Value Description Transmit Interrupt Enable...
Page 282 Section 15 I C Bus Interface 2 (IIC2) Initial Bit Name Value Description NAKIE NACK Receive Interrupt Enable This bit enables or disables the NACK receive interrupt request (NAKI) and the overrun error (setting of the OVE bit in ICSR) interrupt request (ERI) with the clocked synchronous format, when the NACKF and AL bits in ICSR are set to 1.
Page 283: C Bus Status Register (Icsr)
Section 15 I C Bus Interface 2 (IIC2) 15.3.5 C Bus Status Register (ICSR) ICSR performs confirmation of interrupt request flags and status. Initial Bit Name Value Description TDRE Transmit Data Register Empty [Setting conditions] • When data is transferred from ICDRT to ICDRS and ICDRT becomes empty •...
Page 284 Section 15 I C Bus Interface 2 (IIC2) Initial Bit Name Value Description NACKF No Acknowledge Detection Flag [Setting condition] • When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 [Clearing condition] •...
Page 285: Slave Address Register (Sar)
Section 15 I C Bus Interface 2 (IIC2) Initial Bit Name Value Description Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting conditions] •...
Page 286: C Bus Transmit Data Register (Icdrt)
Section 15 I C Bus Interface 2 (IIC2) 15.3.7 C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data.
Page 287: Operation
Section 15 I C Bus Interface 2 (IIC2) 15.4 Operation The I C bus interface can communicate either in I C bus mode or clocked synchronous serial mode by setting FS in SAR. 15.4.1 C Bus Format Figure 15.3 shows the I C bus formats.
Page 288: Master Transmit Operation
Section 15 I C Bus Interface 2 (IIC2) Legend Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0.
Page 289: Figure 15.5 Master Transmit Mode Operation Timing (1)
Section 15 I C Bus Interface 2 (IIC2) (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (Master output) Slave address (Slave output) TDRE TEND ICDRT Address + R/W Data 1 Data 2 ICDRS...
Page 290: Master Receive Operation
Section 15 I C Bus Interface 2 (IIC2) 15.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 15.7 and 15.8.
Page 291: Figure 15.7 Master Receive Mode Operation Timing (1)
Section 15 I C Bus Interface 2 (IIC2) Master transmit mode Master receive mode (Master output) (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 (Slave output) TDRE TEND RDRF ICDRS Data 1...
Page 292: Slave Transmit Operation
Section 15 I C Bus Interface 2 (IIC2) (Master output) (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Slave output) RDRF RCVD ICDRS Data n-1 Data n ICDRR Data n Data n-1 User [7] Read ICDRR,...
Page 293: Figure 15.9 Slave Transmit Mode Operation Timing (1)
Section 15 I C Bus Interface 2 (IIC2) Slave receive mode Slave transmit mode (Master output) (Master output) (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 (Slave output) TDRE TEND ICDRT...
Page 294: Slave Receive Operation
Section 15 I C Bus Interface 2 (IIC2) Slave receive mode Slave transmit mode (Master output) (Master output) (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Slave output) TDRE TEND ICDRT ICDRS Data n...
Page 295: Figure 15.11 Slave Receive Mode Operation Timing (1)
Section 15 I C Bus Interface 2 (IIC2) 3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be returned to the master device, is reflected to the next transmit frame.
Page 296: Clocked Synchronous Serial Format
Section 15 I C Bus Interface 2 (IIC2) 15.4.6 Clocked Synchronous Serial Format This module can be operated with the clocked synchronous serial format, by setting the FS bit in SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When MST is 0, the external clock input is selected.
Page 297: Figure 15.14 Transmit Mode Operation Timing
Section 15 I C Bus Interface 2 (IIC2) Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 0 Bit 1 (Output) TDRE Data 1 ICDRT Data 2 Data 3 Data 1 Data 2 Data 3 ICDRS User [3] Write data [3] Write data...
Page 298: Noise Canceler
Section 15 I C Bus Interface 2 (IIC2) Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 1 Bit 0 Bit 1 (Input) RDRF Data 2 Data 3 Data 1 ICDRS ICDRR Data 1 Data 2 User [2] Set MST [3] Read ICDRR...
Page 299: Example Of Use
Section 15 I C Bus Interface 2 (IIC2) 15.4.8 Example of Use Flowcharts in respective modes that use the I C bus interface are shown in figures 15.17 to 15.20. Start Test the status of the SCL and SDA lines. Initialize Set master transmit mode.
Page 300: Figure 15.18 Sample Flowchart For Master Receive Mode
Section 15 I C Bus Interface 2 (IIC2) Mater receive mode Clear TEND, select master receive mode, and then clear TDRE.* Clear TEND in ICSR Set acknowledge to the transmit device.* Clear TRS in ICCR1 to 0 Dummy-read ICDDR.* Clear TDRE in ICSR Wait for 1 byte to be received Clear ACKBT in ICIER to 0 Check whether it is the (last receive - 1).
Page 301: Figure 15.19 Sample Flowchart For Slave Transmit Mode
Section 15 I C Bus Interface 2 (IIC2) [1] Clear the AAS flag. Slave transmit mode Clear AAS in ICSR [2] Set transmit data for ICDRT (except for the last data). [3] Wait for ICDRT empty. Write transmit data in ICDRT [4] Set the last byte of transmit data.
Page 302: Figure 15.20 Sample Flowchart For Slave Receive Mode
Section 15 I C Bus Interface 2 (IIC2) Slave receive mode [1] Clear the AAS flag. Clear AAS in ICSR [2] Set acknowledge to the transmit device. Clear ACKBT in ICIER to 0 [3] Dummy-read ICDRR. Dummy-read ICDRR [4] Wait for 1 byte to be received. [5] Check whether it is the (last receive - 1).
Page 303: Interrupt Request
Section 15 I C Bus Interface 2 (IIC2) 15.5 Interrupt Request There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost/overrun. Table 15.3 shows the contents of each interrupt request.
Page 304: Usage Notes
Section 15 I C Bus Interface 2 (IIC2) SCL monitor timing reference clock Internal SCL Figure 15.21 The Timing of the Bit Synchronous Circuit Table 15.4 Time for Monitoring SCL CKS3 CKS2 Time for Monitoring SCL 7.5 tcyc 19.5 tcyc 17.5 tcyc 41.5 tcyc 15.7...
Page 305: Section 16 A/D Converter
Section 16 A/D Converter Section 16 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. The block diagram of the A/D converter is shown in figure 16.1.
Page 306: Figure 16.1 Block Diagram Of A/D Converter
Section 16 A/D Converter Module data bus Internal data bus 10-bit D/A ø/4 Control circuit ø/8 Comparator Sample-and- hold circuit interrupt ADTRG [Legend] ADCR : A/D control register ADCSR : A/D control/status register ADDRA : A/D data register A ADDRB : A/D data register B ADDRC : A/D data register C...
Page 307: Input/Output Pins
Section 16 A/D Converter 16.2 Input/Output Pins Table 16.1 summarizes the input pins used by the A/D converter. The 8 analog input pins are divided into two groups; analog input pins 0 to 3 (AN0 to AN3) comprising group 0, analog input pins 4 to 7 (AN4 to AN7) comprising group 1.
Page 308: Register Descriptions
Section 16 A/D Converter 16.3 Register Descriptions The A/D converter has the following registers. • A/D data register A (ADDRA) • A/D data register B (ADDRB) • A/D data register C (ADDRC) • A/D data register D (ADDRD) • A/D control/status register (ADCSR) •...
Page 309: A/D Control/Status Register (Adcsr)
Section 16 A/D Converter 16.3.2 A/D Control/Status Register (ADCSR) ADCSR consists of the control bits and conversion end status bits of the A/D converter. Initial Bit Name Value Description A/D End Flag [Setting conditions] • When A/D conversion ends in single mode •...
Page 310 Section 16 A/D Converter Initial Bit Name Value Description Channel Select 2 to 0 Select analog input channels. When SCAN = 0 When SCAN = 1 000: AN0 000: AN0 001: AN1 001: AN0 and AN1 010: AN2 010: AN0 to AN2 011: AN3 011: AN0 to AN3 100: AN4...
Page 311: A/D Control Register (Adcr)
Section 16 A/D Converter 16.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion started by an external trigger signal. Initial Bit Name Value Description TRGE Trigger Enable A/D conversion is started at the falling edge and the rising edge of the external trigger signal (ADTRG) when this bit is set to 1.
Page 312: Operation
Section 16 A/D Converter 16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST in ADCSR to 0. The ADST bit can be set at the same time as the operating mode or analog input channel is changed.
Page 313: Input Sampling And A/D Conversion Time
Section 16 A/D Converter 16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (t ) has passed after the ADST bit is set to 1, then starts conversion.
Page 314: External Trigger Input Timing
Section 16 A/D Converter Table 16.3 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Item Symbol A/D conversion start delay time — — Input sampling time — — — — A/D conversion time — — CONV Note: All values represent the number of states. 16.4.4 External Trigger Input Timing A/D conversion can also be started by an external trigger input.
Page 315: A/D Conversion Accuracy Definitions
Section 16 A/D Converter 16.5 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.4). •...
Page 316: Figure 16.4 A/D Conversion Accuracy Definitions (1)
Section 16 A/D Converter Digital output Ideal A/D conversion characteristic Quantization error Analog input voltage Figure 16.4 A/D Conversion Accuracy Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog Offset error input voltage Figure 16.5 A/D Conversion Accuracy Definitions (2) Rev.
Page 317: Usage Notes
Section 16 A/D Converter 16.6 Usage Notes 16.6.1 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time;...
Page 318 Section 16 A/D Converter Rev. 1.00 Aug. 28, 2006 Page 288 of 400 REJ09B0268-0100...
Page 319: Section 17 Band-Gap Circuit, Power-On Reset, And Low-Voltage Detection Circuits
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits This LSI can include a band-gap circuit (BGR, band-gap regulator), a power-on reset circuit and low-voltage detection circuit. BGR supplies a reference voltage to the on-chip oscillator and low-voltage detection circuit. Figure 17.1 shows the block diagram of how BGR is allocated.
Page 320: Features
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 17.1 Features • BGR circuit Supplies stable reference voltage covering the entire operating voltage range and the operating temperature range. • Power-on reset circuit Uses an external capacitor to generate an internal reset signal when power is first supplied. •...
Page 321: Figure 17.2 Block Diagram Of Power-On Reset Circuit And Low-Voltage Detection Circuit
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits φ Internal Noise filter reset signal circuit Power-on reset circuit Noise filter circuit LVDCR Vreset LVDRES Ladder Vint network LVDINT Interrupt LVDSR control circuit Interrupt request VBGR Low-voltage-detection circuit [Legend] PSS: Prescaler S LVDCR: Low-voltage-detection control register...
Page 322: Register Descriptions
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 17.2 Register Descriptions The low-voltage detection circuit has the following registers. • Low-voltage-detection control register (LVDCR) • Low-voltage-detection status register (LVDSR) • Reset source decision register (LVDRF) 17.2.1 Low-Voltage-Detection Control Register (LVDCR) LVDCR sets the detection levels for the LVDR circuit, enables or disables the LVDR circuit, and enables or disables generation of an interrupt when the power-supply voltage rises above or falls below the respective levels.
Page 323: Low-Voltage-Detection Status Register (Lvdsr)
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Table 17.1 LVDCR Settings and Select Functions LVDCR Settings Select Functions Low-Voltage- Low-Voltage- Power-On Detection Fall Detection Rise VDDII LVDSEL LVDDE LVDUE Reset LVDR Interrupt Interrupt √ √   √...
Page 324: Reset Source Decision Register (Lvdrf)
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 17.2.3 Reset Source Decision Register (LVDRF) LVDRF indicates sources of resets. Initial Bit Name Value Description    7 to 2 Reserved The read value is undefined and these bits cannot be modified.
Page 325: Operations
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 17.3 Operations 17.3.1 Power-On Reset Circuit Figure 17.3 shows the timing of the operation of the power-on reset circuit. As the power-supply voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via the internal pull-up resistor (Typ.
Page 326: Low-Voltage Detection Circuit
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits PWON Vpor PSS-reset signal Internal reset signal 131,072 cycles PSS counter starts Reset released Figure 17.3 Operational Timing of Power-On Reset Circuit 17.3.2 Low-Voltage Detection Circuit LVDR (Reset by Low Voltage Detection) Circuit: Figure 17.4 shows the timing of the operation of the LVDR circuit.
Page 327: Figure 17.4 Operating Timing Of Lvdr Circuit
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Vreset LVDRmin LVDRES PSS-reset signal Internal reset signal 131,072 cycles PSS counter starts Reset released Figure 17.4 Operating Timing of LVDR Circuit Rev. 1.00 Aug. 28, 2006 Page 297 of 400 REJ09B0268-0100...
Page 328: Figure 17.5 Operational Timing Of Lvdi Circuit
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Low Voltage Detection Interrupt (LVDI) Circuit (When Internally Generated Voltage is used for Detection): Figure 17.5 shows the timing of the operation of the LVDI circuit. The LVDI circuit is enabled after a power-on reset, however, the interrupt request is disabled. To enable the LVDI, the LVDDF bit and LVDUF bit in LVDSR must be cleared to 0 and then the LVDDE bit or LVDUE bit in LVDCR must be set to 1.
Page 329: Deciding Reset Source
Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits 17.3.3 Deciding Reset Source The source of a reset can be decided by reading the reset source decision register (LVDRF) in the reset exception handler (see table 17.2). After that, writing 0 to the bit can clear the flag and can be ready to decide the next reset source.
Page 330 Section 17 Band-Gap Circuit, Power-On Reset, and Low-Voltage Detection Circuits Rev. 1.00 Aug. 28, 2006 Page 300 of 400 REJ09B0268-0100...
Page 331: Section 18 Power Supply Circuit
Section 18 Power Supply Circuit Section 18 Power Supply Circuit This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external V pin.
Page 332: When Not Using Internal Power Supply Step-Down Circuit
Section 18 Power Supply Circuit 18.2 When Not Using Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supply to the V pin and V pin, as shown in figure 18.2. The external power supply is then input directly to the internal power supply.
Page 333: Section 19 List Of Registers
Section 19 List of Registers Section 19 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below.
Page 334: Register Addresses (Address Order)
Section 19 List of Registers 19.1 Register Addresses (Address Order) The data-bus width column indicates the number of bits. The access-state column shows the number of states of the selected basic clock that is required for access to the register. Note: Access to undefined or reserved addresses should not take place.
Page 335 Section 19 List of Registers Module Data Bus Access Register Name Abbreviation Bit No Address Name Width State Timer control register W TCRW H'FF81 Timer W Timer interrupt enable register W TIERW H'FF82 Timer W Timer status register W TSRW H'FF83 Timer W Timer I/O control register 0...
Page 336 Section 19 List of Registers Module Data Bus Access Register Name Abbreviation Bit No Address Name Width State Receive data register H'FFAD SCI3 — — — H'FFAE, — — — H'FFAF A/D data register A ADDRA H'FFB0 A/D converter A/D data register B ADDRB H'FFB2 A/D converter...
Page 337 Section 19 List of Registers Module Data Bus Access Register Name Abbreviation Bit No Address Name Width State Port data register 5 PDR5 H'FFD8 I/O port — — — H'FFD9 I/O port — — Port data register 7 PDR7 H'FFDA I/O port Port data register 8 PDR8...
Page 338 Section 19 List of Registers Module Data Bus Access Register Name Abbreviation Bit No Address Name Width State — — — H'FFFA, Power-down — — H'FFFB — — — H'FFFC to — — — H'FFFF Notes: 1. LVDCR and LVDSR are optional 2.
Page 339: Register Bits
Section 19 List of Registers 19.2 Register Bits The addresses and bit names of the registers in the on-chip peripheral modules are listed below. The 16-bit register is indicated in two rows, 8 bits for each row. Register Module Name Bit 7 Bit 6 Bit 5...
Page 340 Section 19 List of Registers Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name GRB15 GRB14 GRB13 GRB12 GRB11 GRB10 GRB9 GRB8 Timer W GRB7 GRB6 GRB5 GRB4 GRB3 GRB2 GRB1 GRB0...
Page 341 Section 19 List of Registers Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name ADCSR ADIE ADST SCAN converter ADCR TRGE — — — — — — — — —...
Page 342 Section 19 List of Registers Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name IEGR1 NMIEG — — — IEG3 IEG2 IEG1 IEG0 Interrupts IEGR2 — — WPEG5 WPEG4 WPEG3 WPEG2 WPEG1...
Page 343: Registers States In Each Operating Mode
Section 19 List of Registers 19.3 Registers States in Each Operating Mode Register Name Reset Active Sleep Subactive Subsleep Standby Module — — — — — Initialized LVDC (optional) LVDCR — — — — — Initialized LVDSR — Initialized RSTSR —...
Page 344 Section 19 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module — — TCRV0 Initialized Initialized Initialized Initialized Timer V — — TCSRV Initialized Initialized Initialized Initialized — — TCORA Initialized Initialized Initialized Initialized — — TCORB Initialized Initialized Initialized...
Page 345 Section 19 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module — — — — — PDR5 Initialized I/O port — — — — — PDR7 Initialized — — — — — PDR8 Initialized — — — —...
Page 346 Section 19 List of Registers Rev. 1.00 Aug. 28, 2006 Page 316 of 400 REJ09B0268-0100...
Page 347: Section 20 Electrical Characteristics
Section 20 Electrical Characteristics Section 20 Electrical Characteristics 20.1 Absolute Maximum Ratings Table 20.1 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage –0.3 to +7.0 Analog power supply voltage –0.3 to +7.0 Input voltage Ports other than ports –0.3 to V +0.3 B and X1...
Page 348 Section 20 Electrical Characteristics Power Supply Voltage and Operating Frequency Range φ (MHz) φ (kHz) 20.0 16.384 10.0 8.192 4.096 • AV = 3.0 to 5.5 V • AV = 3.0 to 5.5 V • Active mode • Subactive mode •...
Page 349 Section 20 Electrical Characteristics Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection Circuit is Used φosc (MHz) 20.0 16.0 Vcc(V) Operation guarantee range Operation guarantee range except A/D conversion accuracy Rev. 1.00 Aug. 28, 2006 Page 319 of 400 REJ09B0268-0100...
Page 350: Dc Characteristics
Section 20 Electrical Characteristics 20.2.2 DC Characteristics Table 20.2 DC Characteristics (1) = 3.0 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Item Symbol Applicable Pins Test Condition Unit Notes RES, NMI, ×...
Page 351 Section 20 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Unit Notes Output P10 to P12, = 4.0 to 5.5 V – 1.0 — — high P14 to P17, –I = 1.5 mA voltage P20 to P22, P50 to P55, –I = 0.1 mA –...
Page 352 Section 20 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Unit Notes Pull-up –I P10 to P12, = 5.0 V, 50.0 — 300.0 µA P14 to P17, = 0.0 V current P50 to P55 = 3.0 V, — 60.0 —...
Page 353 Section 20 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Unit Notes Subsleep = 3.0 V — 85.0 140.0 µA SUBSP1 mode 32-kHz crystal Optional current resonator — 15.0 45.0 = φ consump- (φ tion = 3.0 V — 85.0 135.0 SUBSP2...
Page 354: Table 20.2 Dc Characteristics (2)
Section 20 Electrical Characteristics Table 20.2 DC Characteristics (2) = 3.0 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Applicable Item Symbol Pins Unit Test Condition Allowable output low Output pins = 4.0 to 5.5 V — —...
Page 355: Ac Characteristics
Section 20 Electrical Characteristics 20.2.3 AC Characteristics Table 20.3 AC Characteristics = 3.0 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Applicable Reference Item Symbol Pins Test Condition Unit Figure System clock OSC1, OSC2 V = 4.0 to 5.5 V —...
Page 356 Section 20 Electrical Characteristics Values Applicable Reference Item Symbol Pins Test Condition Typ Max Unit Figure RES pin low At power-on and in — — Figure 20.2 width modes other than those below In active mode and 1500 — — sleep mode operation NMI pin high width...
Page 357 Section 20 Electrical Characteristics Values Applicable Reference Item Symbol Pins Test Condition Unit Figure On-chip oscillator = 4.0 to 5.5 V 19.70 20.0 20.30 oscillation Ta = 25°C frequency FSEL = 1 Ta = 25°C 19.60 20.0 20.40 FSEL = 1 = 4.0 to 5.5 V 19.40 20.0...
Page 358: Table 20.4 I 2 C Bus Interface Timing
Section 20 Electrical Characteristics Table 20.4 I C Bus Interface Timing = 3.0 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Test Reference Item Symbol Condition Unit Figure SCL input cycle time + 600 —...
Page 359: Table 20.5 Serial Communication Interface (Sci) Timing
Section 20 Electrical Characteristics Table 20.5 Serial Communication Interface (SCI) Timing = 3.0 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Applicable Reference Item Symbol Pins Test Condition Typ Max Unit Figure Input Asynchro- SCK3...
Page 360: A/D Converter Characteristics
Section 20 Electrical Characteristics 20.2.4 A/D Converter Characteristics Table 20.6 A/D Converter Characteristics = 3.0 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Applicable Test Reference Item Symbol Pins Condition Typ Max Unit Figure Analog power supply...
Page 361: Watchdog Timer Characteristics
Section 20 Electrical Characteristics Values Applicable Test Reference Item Symbol Pins Condition Typ Max Unit Figure Conversion time = 4.0 to — — (single mode) 5.5 V Nonlinearity error — — ±3.5 Offset error — — ±3.5 Full-scale error — —...
Page 362: Flash Memory Characteristics
Section 20 Electrical Characteristics 20.2.6 Flash Memory Characteristics Table 20.8 Flash Memory Characteristics = 3.0 to 5.5 V, V = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Test Item Symbol Condition Unit Programming time (per 128 bytes)* —...
Page 363 Section 20 Electrical Characteristics Values Test Item Symbol Condition Unit Erasing Wait time after SWE — — µs bit setting* Wait time after ESU — — µs bit setting* Wait time after E bit — setting* α Wait time after E bit clear* —...
Page 364: Power-Supply-Voltage Detection Circuit Characteristics (Optional)
Section 20 Electrical Characteristics 20.2.7 Power-Supply-Voltage Detection Circuit Characteristics (Optional) Table 20.9 Power-Supply-Voltage Detection Circuit Characteristics = 0.0 V, T = –20 to +75°C, unless otherwise indicated. Values Test Item Symbol Condition Unit Power-supply falling detection Vint (D) LVDSEL = 0 —...
Page 365: Operation Timing
Section 20 Electrical Characteristics 20.3 Operation Timing OSC1 Figure 20.1 System Clock Input Timing × 0.7 OSC1 Figure 20.2 RES Low Width Timing IRQ0 to IRQ3 WKP0 to WKP5 ADTRG FTCI FTIOA to FTIOD TMCIV, TMRIV TRGV Figure 20.3 Input Timing Rev.
Page 366: Figure 20.4 I C Bus Interface Input/Output Timing
Section 20 Electrical Characteristics STAH STOS SCLH STAS SCLL SDAS SDAH Note: * S, P, and Sr represent the following: S: Start condition P: Stop condition Sr: Retransmission start condition Figure 20.4 I C Bus Interface Input/Output Timing SCKW SCK3 Scyc Figure 20.5 SCK3 Input Clock Timing Rev.
Page 367: Output Load Condition
Section 20 Electrical Characteristics Scyc or V SCK3 or V (transmit data) (receive data) Note: * Output timing reference levels Output high: = 2.0 V Output low: = 0.8 V Load conditions are shown in figure 21.8. Figure 20.6 SCI Input/Output Timing in Clocked Synchronous Mode 20.4 Output Load Condition 2.4 kΩ...
Page 368 Section 20 Electrical Characteristics Rev. 1.00 Aug. 28, 2006 Page 338 of 400 REJ09B0268-0100...
Page 369: Appendix A Instruction Set
Appendix Appendix A Instruction Set Instruction List Condition Code Symbol Description General destination register General source register General register General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) (EAd) Destination operand (EAs) Source operand...
Page 370 Appendix Symbol Description ( ), < > Contents of operand Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (R0 to R7 and E0 to E7). Condition Code Notation (cont) Symbol Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1...
Page 371: Table A.1 Instruction Set
Appendix Table A.1 Instruction Set 1. Data Transfer Instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation #xx:8 → Rd8 MOV.B #xx:8, Rd — — — Rs8 → Rd8 MOV.B Rs, Rd — — — @ERs →...
Page 372 Appendix Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation ERd32–2 → ERd32 MOV.W Rs, @–ERd — — — Rs16 → @ERd Rs16 → @aa:16 MOV.W Rs, @aa:16 — — — Rs16 → @aa:24 MOV.W Rs, @aa:24 —...
Page 373 Appendix 2. Arithmetic Instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Rd8+#xx:8 → Rd8 ADD.B #xx:8, Rd — Rd8+Rs8 → Rd8 ADD.B Rs, Rd — Rd16+#xx:16 → Rd16 ADD.W #xx:16, Rd — Rd16+Rs16 → Rd16 ADD.W Rs, Rd —...
Page 374 Appendix Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation ERd32–1 → ERd32 DEC.L #1, ERd — — — ERd32–2 → ERd32 DEC.L #2, ERd — — — DAS.Rd Rd8 decimal adjust — — → Rd8 Rd8 ×...
Page 375 Appendix Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation 0–Rd8 → Rd8 NEG.B Rd — 0–Rd16 → Rd16 NEG.W Rd — 0–ERd32 → ERd32 NEG.L ERd — 0 → (<bits 15 to 8> EXTU EXTU.W Rd —...
Page 376 Appendix 3. Logic Instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Rd8∧#xx:8 → Rd8 AND.B #xx:8, Rd — — — Rd8∧Rs8 → Rd8 AND.B Rs, Rd — — — Rd16∧#xx:16 → Rd16 AND.W #xx:16, Rd —...
Page 377 Appendix 4. Shift Instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation SHAL.B Rd — — SHAL SHAL.W Rd — — SHAL.L ERd — — SHAR.B Rd — — SHAR SHAR.W Rd — — SHAR.L ERd —...
Page 378 Appendix 5. Bit-Manipulation Instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation (#xx:3 of Rd8) ← 1 BSET #xx:3, Rd — — — — — — BSET (#xx:3 of @ERd) ← 1 BSET #xx:3, @ERd —...
Page 379 Appendix Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation (#xx:3 of @ERd) → C BLD #xx:3, @ERd — — — — — (#xx:3 of @aa:8) → C BLD #xx:3, @aa:8 — — — — — ¬...
Page 380 Appendix 6. Branching Instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation Branch Condition BRA d:8 (BT d:8) — Always — — — — — — If condition is true then BRA d:16 (BT d:16) —...
Page 381 Appendix Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation PC ← ERn JMP @ERn — — — — — — — PC ← aa:24 JMP @aa:24 — — — — — — — PC ← @aa:8 JMP @@aa:8 —...
Page 382 Appendix 7. System Control Instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation PC → @–SP TRAPA #x:2 — — — — — — TRAPA CCR → @–SP <vector> → PC CCR ← @SP+ — PC ←...
Page 383 Appendix 8. Block Transfer Instructions Addressing Mode and No. of Instruction Length (bytes) States Condition Code Mnemonic Operation if R4L ≠ 0 then EEPMOV. B — — — — — — — EEPMOV repeat @R5 → @R6 R5+1 → R5 R6+1 →...
Page 384: Operation Code Map
Appendix Operation Code Map Table A.2 Operation Code Map (1) Rev. 1.00 Aug. 28, 2006 Page 354 of 400 REJ09B0268-0100...
Page 385: Table A.2 Operation Code Map (2)
Appendix Table A.2 Operation Code Map (2) Rev. 1.00 Aug. 28, 2006 Page 355 of 400 REJ09B0268-0100...
Page 386: Table A.2 Operation Code Map (3)
Appendix Table A.2 Operation Code Map (3) Rev. 1.00 Aug. 28, 2006 Page 356 of 400 REJ09B0268-0100...
Page 387: Number Of Execution States
Appendix Number of Execution States The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write.
Page 388: Table A.3 Number Of Cycles In Each Instruction
Appendix Table A.3 Number of Cycles in Each Instruction Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module Instruction fetch — Branch address read Stack operation Byte data access 2 or 3* Word data access 2 or 3* Internal operation Note: Depends on which on-chip peripheral module is accessed.
Page 389: Table A.4 Number Of Cycles In Each Instruction
Appendix Table A.4 Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS ADDS #1/2/4, ERd...
Page 390 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BLT d:8 BGT d:8 BLE d:8 BRA d:16(BT d:16) BRN d:16(BF d:16) BHI d:16 BLS d:16 BCC d:16(BHS d:16) BCS d:16(BLO d:16) BNE d:16 BEQ d:16 BVC d:16...
Page 391 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BIOR BIOR #xx:8, Rd BIOR #xx:8, @ERd BIOR #xx:8, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8 BLD #xx:3, Rd...
Page 392 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BTST BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 CMP.B #xx:8, Rd...
Page 393 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic INC.B Rd INC.W #1/2, Rd INC.L #1/2, ERd JMP @ERn JMP @aa:24 JMP @@aa:8 JSR @ERn JSR @aa:24 JSR @@aa:8 LDC #xx:8, CCR LDC Rs, CCR LDC@ERs, CCR LDC@(d:16, ERs), CCR...
Page 394 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd MOV.W @(d:16,ERs), Rd MOV.W @(d:24,ERs), Rd MOV.W @ERs+, Rd MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd...
Page 395 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd MULXU MULXU.B Rs, Rd MULXU.W Rs, ERd NEG.B Rd NEG.W Rd NEG.L ERd NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8, Rd...
Page 396 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd SHAL SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd...
Page 397 Appendix Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic SUBX SUBX #xx:8, Rd SUBX. Rs, Rd TRAPA TRAPA #xx:2 XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd XORC...
Page 398: Combinations Of Instructions And Addressing Modes
Appendix Combinations of Instructions and Addressing Modes Table A.5 Combinations of Instructions and Addressing Modes Addressing Mode Functions Instructions Data — — — — transfer POP, PUSH — — — — — — — — — — — — instructions MOVFPE, —...
Page 399: Appendix B I/O Port Block Diagrams
Appendix Appendix B I/O Port Block Diagrams I/O Port Block Diagrams RES goes low in a reset, and SBY goes low in a reset and in standby mode. Internal data bus PUCR Pull-up MOS TRGV [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register...
Page 400: Figure B.2 Port 1 Block Diagram (P16 To P14)
Appendix Internal data bus PUCR Pull-up MOS [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.2 Port 1 Block Diagram (P16 to P14) Rev. 1.00 Aug. 28, 2006 Page 370 of 400 REJ09B0268-0100...
Page 401: Figure B.3 Port 1 Block Diagram (P12, P11)
Appendix Internal data bus PUCR Pull-up MOS [Legend] PUCR: Port pull-up control register PDR: Port data register PCR: Port control register Figure B.3 Port 1 Block Diagram (P12, P11) Rev. 1.00 Aug. 28, 2006 Page 371 of 400 REJ09B0268-0100...
Page 402: Figure B.4 Port 1 Block Diagram (P10)
Appendix Internal data bus PUCR Pull-up MOS Timer A TMOW [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.4 Port 1 Block Diagram (P10) Rev. 1.00 Aug. 28, 2006 Page 372 of 400 REJ09B0268-0100...
Page 403: Figure B.5 Port 2 Block Diagram (P22)
Appendix Internal data bus SCI3 [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.5 Port 2 Block Diagram (P22) Rev. 1.00 Aug. 28, 2006 Page 373 of 400 REJ09B0268-0100...
Page 404: Figure B.6 Port 2 Block Diagram (P21)
Appendix Internal data bus SCI3 [Legend] PDR: Port data register PCR: Port control register Figure B.6 Port 2 Block Diagram (P21) Rev. 1.00 Aug. 28, 2006 Page 374 of 400 REJ09B0268-0100...
Page 405: Figure B.7 Port 2 Block Diagram (P20)
Appendix SCI3 SCKIE SCKOE Internal data bus SCKO SCKI [Legend] PDR: Port data register PCR: Port control register Figure B.7 Port 2 Block Diagram (P20) Rev. 1.00 Aug. 28, 2006 Page 375 of 400 REJ09B0268-0100...
Page 406: Figure B.8 Port 5 Block Diagram (P57, P56)
Appendix Internal data bus IIC2 SDAO/SCLO SDAI/SCLI [Legend] PDR: Port data register PCR: Port control register Figure B.8 Port 5 Block Diagram (P57, P56) Rev. 1.00 Aug. 28, 2006 Page 376 of 400 REJ09B0268-0100...
Page 407: Figure B.9 Port 5 Block Diagram (P55)
Appendix Internal data bus PUCR Pull-up MOS ADTRG [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.9 Port 5 Block Diagram (P55) Rev. 1.00 Aug. 28, 2006 Page 377 of 400 REJ09B0268-0100...
Page 408: Figure B.10 Port 5 Block Diagram (P54 To P50)
Appendix Internal data bus PUCR Pull-up MOS [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.10 Port 5 Block Diagram (P54 to P50) Rev. 1.00 Aug. 28, 2006 Page 378 of 400 REJ09B0268-0100...
Page 409: Figure B.11 Port 7 Block Diagram (P76)
Appendix Internal data bus Timer V TMOV [Legend] PDR: Port data register PCR: Port control register Figure B.11 Port 7 Block Diagram (P76) Rev. 1.00 Aug. 28, 2006 Page 379 of 400 REJ09B0268-0100...
Page 410: Figure B.12 Port 7 Block Diagram (P75)
Appendix Internal data bus Timer V TMCIV [Legend] PDR: Port data register PCR: Port control register Figure B.12 Port 7 Block Diagram (P75) Rev. 1.00 Aug. 28, 2006 Page 380 of 400 REJ09B0268-0100...
Page 411: Figure B.13 Port 7 Block Diagram (P74)
Appendix Internal data bus Timer V TMRIV [Legend] PDR: Port data register PCR: Port control register Figure B.13 Port 7 Block Diagram (P74) Rev. 1.00 Aug. 28, 2006 Page 381 of 400 REJ09B0268-0100...
Page 412: Figure B.14 Port 8 Block Diagram (P87 To P85)
Appendix Internal data bus [Legend] PDR: Port data register PCR: Port control register Figure B.14 Port 8 Block Diagram (P87 to P85) Rev. 1.00 Aug. 28, 2006 Page 382 of 400 REJ09B0268-0100...
Page 413: Figure B.15 Port 8 Block Diagram (P84 To P81)
Appendix Internal data bus Timer W Output control signals A to D FTIOA FTIOB FTIOC FTIOD [Legend] PDR: Port data register PCR: Port control register Figure B.15 Port 8 Block Diagram (P84 to P81) Rev. 1.00 Aug. 28, 2006 Page 383 of 400 REJ09B0268-0100...
Page 414: Figure B.16 Port 8 Block Diagram (P80)
Appendix Internal data bus Timer W FTCI [Legend] PDR: Port data register PCR: Port control register Figure B.16 Port 8 Block Diagram (P80) Rev. 1.00 Aug. 28, 2006 Page 384 of 400 REJ09B0268-0100...
Page 415: Figure B.17 Port B Block Diagram (Pb7 To Pb0)
Appendix Internal data bus A/D converter CH3 to CH0 Figure B.17 Port B Block Diagram (PB7 to PB0) Rev. 1.00 Aug. 28, 2006 Page 385 of 400 REJ09B0268-0100...
Page 416: Figure B.18 Port C Block Diagram (Pc1)
Appendix Internal data bus φ PMRC1 PMRC0 XTALI [Legend] PDR: Port data register PCR: Port control register Figure B.18 Port C Block Diagram (PC1) Rev. 1.00 Aug. 28, 2006 Page 386 of 400 REJ09B0268-0100...
Page 417: Figure B.19 Port C Block Diagram (Pc0)
Appendix Internal data bus PMRC0 EXTALI [Legend] PDR: Port data register PCR: Port control register Figure B.19 Port C Block Diagram (PC0) Rev. 1.00 Aug. 28, 2006 Page 387 of 400 REJ09B0268-0100...
Page 418: Port States In Each Operating State
Appendix Port States in Each Operating State Port Reset Sleep Subsleep Standby Subactive Active P17 to P14, High Retained Retained High Functioning Functioning P12 to P10 impedance impedance* P22 to P20 High Retained Retained High Functioning Functioning impedance impedance P57 to P50 High Retained Retained...
Page 419: Appendix C Product Code Lineup
Appendix Appendix C Product Code Lineup Product Classification Product Code Model Marking Package Code H8/36094 Flash Standard HD64F36094FZ HD64F36094FZ LQFP-64 (FP-64K) memory product HD64F36094H HD64F36094H QFP-64 (FP-64A) version HD64F36094FX HD64F36094FX LQFP-48 (FP-48F) HD64F36094FY HD64F36094FY LQFP-48 (FP-48B) HD64F36094FT HD64F36094FT QFN-48 (TNP-48) Product with HD64F36094GFZ HD64F36094GFZ LQFP-64 (FP-64K)
Page 420: Appendix D Package Dimensions
Appendix Appendix D Package Dimensions The package dimensions that are shown in the Renesas Semiconductor Packages Data Book have priority. Rev. 1.00 Aug. 28, 2006 Page 390 of 400 REJ09B0268-0100...
Page 421: Figure D.1 Fp-64K Package Dimensions
Appendix Figure D.1 FP-64K Package Dimensions Rev. 1.00 Aug. 28, 2006 Page 391 of 400 REJ09B0268-0100...
Page 422: Figure D.2 Fp-64A Package Dimensions
Appendix Figure D.2 FP-64A Package Dimensions Rev. 1.00 Aug. 28, 2006 Page 392 of 400 REJ09B0268-0100...
Page 423: Figure D.3 Fp-48F Package Dimensions
Appendix Figure D.3 FP-48F Package Dimensions Rev. 1.00 Aug. 28, 2006 Page 393 of 400 REJ09B0268-0100...
Page 424: Figure D.4 Fp-48B Package Dimensions
Appendix Figure D.4 FP-48B Package Dimensions Rev. 1.00 Aug. 28, 2006 Page 394 of 400 REJ09B0268-0100...
Page 425: Figure D.5 Tnp-48 Package Dimensions
Appendix Figure D.5 TNP-48 Package Dimensions Rev. 1.00 Aug. 28, 2006 Page 395 of 400 REJ09B0268-0100...
Page 426: Appendix E Function Comparison
Appendix Appendix E Function Comparison Item H8/3694F H8/36094F H8/36092F Memory Flash memory 32 kbytes 32 kbytes 16 kbytes 2 kbytes 2 kbytes 2 kbytes Oscillator External clock oscillator Supported Supported Supported − On-chip oscillator Supported Supported Total number of pins I/O port General I/O port Large current port...
Page 427: Index
Index Effective address extension....... 27 Erase/erase-verify ........109 A/D converter ......... 275 Erasing units ..........98 Absolute address........30 Error protection........112 Acknowledge .......... 258 Exception handling ........43 Address break ........... 57 Addressing modes........28 Arithmetic operations instructions.... 20 Asynchronous mode .......
Page 428 Low-voltage detection circuit ....289 Programming units........98 LVDI (interrupt by low voltage detect) Programming/erasing in user program circuit............298 mode ............106 LVDR (reset by low voltage detect) circuit............296 Register direct ........... 29 Register field..........27 Mark state ..........239 Register indirect........
Page 429 ICDRT ......256, 304, 309, 313 SYSCR2......87, 307, 311, 315 ICIER......251, 304, 309, 313 TCA ......146, 305, 310, 314 ICMR......249, 304, 309, 313 TCNT ......174, 305, 309, 313 ICSR ......253, 304, 309, 313 TCNTV ....... 151, 305, 310, 314 IEGR1......
Page 430 System clocks ........... 63 Trap instruction......... 43 System control instructions ...... 26 System Prescaler S ........82 System Prescaler W ........82 Vector address........... 43 Timer A ..........143 Timer V ..........149 Watchdog timer........195 Timer W ..........163 WKP5 to WKP0 interrupts .......
Page 431 H8/36094 Group Publication Date: Rev.1.00, Aug. 28, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.  2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 432 Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Page 434 H8/36094 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0268-0100...

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