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Section 6 Bus Controller
The basic CBS refresh cycle timing comprises three states: one RAS precharge cycle (T
and two RAS output cycle (T
precharge cycle. When the TPC bit is set to 1 in DRCRB, RAS signal output is delayed by one
cycle. This does not affect the timing of UCAS and LCAS output.
Use the RLW bit in DRCRB to adjust the RAS signal width. A single refresh wait state (T
be inserted between the T
The RLW bit setting is valid only for CBR refresh cycles, and does not affect DRAM read/write
cycles. The number of states in the CBR refresh cycle is not affected by the settings in ASTCR,
WCRH, or WCRL, or by the state of the WAIT pin.
Figure 6.29 shows the timing when the TPC bit and RLW bit are both set to 1.
φ
Address bus*
CS
(RAS)
n
PB
/PB
4
5
(UCAS/LCAS)
RD(WE)
RFSH
AS
Note: * In address update mode 1, the area 2 start address is output.
In address update mode 2, the address in the preceding bus cycle is retained.
Figure 6.29 CBR Refresh Timing (CSEL = 0, TPC = 1, RLW = 1)
Rev. 4.00 Jan 26, 2006 page 182 of 938
REJ09B0276-0400
, T
) states. Either one or two states can be selected for the RAS
R1
R2
state and T
state by setting the RLW bit to 1.
R1
R2
T
T
Rp1
RP2
Area 2 start address
High level
T
T
R1
RW
High
) state,
RP
) can
RW
T
R2
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