Table of Contents
Advertisement
Appendix D Pin States
D.1
Port States in Each Mode
Table D.1
Port States
Pin
Name Mode Reset
17
17
RESO *
T *
P1
to
1 to 4 L
7
P1
0
5
T
6, 7
T
P2
to
1 to 4 L
7
P2
0
5
T
6, 7
T
P3
to
1 to 5 T
7
P3
0
6, 7
T
P4
to
1, 3, 5 T
7
P4
0
2, 4
T
6, 7
T
Rev. 4.00 Jan 26, 2006 page 914 of 938
REJ09B0276-0400
Appendix D Pin States
Hardware
Standby
Software Standby
Mode
Mode
17
T *
T
T
(SSOE=0)
T
(SSOE=1)
Keep
T
(DDR = 0)
Keep
(DDR=1, SSOE=0)
T
(DDR=1, SSOE=1)
Keep
T
Keep
T
(SSOE = 0)
T
(SSOE = 1)
Keep
T
(DDR = 0)
Keep
(DDR=1,SSOE=0)
T
(DDR=1,SSOE=1)
Keep
T
Keep
T
T
T
Keep
T
Keep
T
T
T
Keep
Bus-Released
Mode
17
T *
T
T
—
T
T
—
T
—
Keep
T
—
Program Execution
Mode
17
T *
A
to A
7
0
(DDR=0)
Input port
(DDR=1)
A
to A
7
0
I/O port
A
to A
15
8
(DDR=0)
Input port
(DDR=1)
A
to A
15
8
I/O port
D
to D
15
8
I/O port
I/O port
D
to D
7
0
I/O port
Advertisement
Table of Contents
