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EBR-Erase Block Register
Bit
EBR
Modes 1 to
Initial value
4, and 6
Read/Write
Modes 5
Initial value
and 7
Read/Write
Note: This register is used only in the flash memory and flash memory R versions.
Reading the corresponding address in a mask ROM version will always return
1s, and writes to this address are disabled.
P2PCR—Port 2 Input Pull-Up Control Register
Bit
P2
7
Initial value
Read/Write
R/W
7
6
EB7
EB6
0
0
R
R
0
0
R/W
R/W
Block 7 to 0
0
Block EB7 to EB0 is not selected (Initial value)
Block EB7 to EB0 is selected
1
Note: When not erasing flash memory, EBR should be cleared to H'00.
7
6
5
PCR
P2
PCR
P2
PCR
6
5
0
0
0
R/W
R/W
Port 2 input pull-up control 7 to 0
0
Input pull-up transistor is off
1
Input pull-up transistor is on
Note: Valid when the corresponding P2DDR bit is cleared to 0
(designating generic input).
Appendix B Internal I/O Registers
H'EE032
5
4
3
EB5
EB4
EB3
0
0
0
R
R
R
0
0
0
R/W
R/W
R/W
H'EE03C
4
3
P2
PCR
P2
PCR
P2
4
3
0
0
R/W
R/W
R/W
Rev. 4.00 Jan 26, 2006 page 813 of 938
Flash Memory
2
1
EB2
EB1
0
0
R
R
0
0
R/W
R/W
Port 2
2
1
0
PCR
P2
PCR
P2
PCR
2
1
0
0
0
0
R/W
R/W
REJ09B0276-0400
0
EB0
0
R
0
R/W
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