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SSR—Serial Status Register
7
6
Bit
TDRE
RDRF
Initial value
1
0
Read/Write
R/(W)*
R/(W)*
Receive data register full
0
1
Transmit data register empty
[Clearing conditions] Read TDRE when TDRE = 1, then write 0 in TDRE.
0
[Setting conditions]
1
Note: * Only 0 can be written, to clear the flag.
5
4
3
ORER
FER/ERS
PER
0
0
0
R/(W)*
R/(W)*
R/(W)*
Parity error
[Clearing conditions] Reset or transition to standby mode
0
[Setting condition]
1
Framing error (for serial communication interface)
[Clearing conditions] Reset or transition to standby mode
0
1
[Setting condition]
Error signal status (for smart card interface)
[Clearing conditions] Reset or transition to standby mode
0
1
[Setting condition]
Overrun error
[Clearing conditions] Reset or transition to standby mode
0
Read ORER when ORER = 1, then write 0 in ORER.
1
[Setting condition]
Overrun error (reception of the next serial data ends when RDRF = 1)
[Clearing conditions] Reset or transition to standby mode
Read RDRF when RDRF = 1, then write 0 in RDRF.
The DMAC reads data from RDR.
[Setting condition]
Serial data is received normally and transferred from RSR to RDR.
The DMAC writes data in TDR.
Reset or transition to standby mode
TE is 0 in SCR.
Data is transferred from TDR to TSR, enabling new data to be written in TDR
Appendix B Internal I/O Registers
H'FFFB4
2
1
0
TEND
MPB
MPBT
1
0
0
R
R
R/W
Multiprocessor bit transfer
0
Multiprocessor bit value in transmit data is 0
1
Multiprocessor bit value in transmit data is 1
Multiprocessor bit
0
Multiprocessor bit value in receive data is 0
1
Multiprocessor bit value in receive data is 1
Transmit end (for serial communication interface)
[Clearing conditions]
Read TDRE when TDRE = 1, then write 0 in TDRE.
0
The DMAC writes data in TDR.
[Setting conditions]
Reset or transition to standby mode
TE is cleared to 0 in SCR.
1
TDRE is 1 when last bit of 1-byte serial character is
transmitted.
Transmit end (for smart card interface)
[Clearing conditions]
Read TDRE when TDRE = 1, then write 0 in TDRE.
0
The DMAC writes data in TDR.
[Setting conditions]
Reset or transition to standby mode
TE is cleared to 0 in SCR and FER/ERS is cleared to 0.
1
TDRE is 1 and FER/ERS is 0 (normal transmission) 2.5 etu*
(when GM = 0) or 1.0 etu (when GM = 1) after 1-byte serial
character is transmitted.
Note: * etu: Elementary time unit (time required to transmit one bit)
Read PER when PER = 1, then write 0 in PER.
Parity error (parity of receive data does not match parity
setting of O/E bit in SMR)
Read FER when FER = 1, then write 0 in FER.
Framing error (stop bit is 0)
Read ERS when ERS = 1, then write 0 in ERS.
A low error signal is received.
Rev. 4.00 Jan 26, 2006 page 865 of 938
SCI0
REJ09B0276-0400
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