Renesas H8/3067 Series User Manual page 258

Section 7 DMA Controller
Table 7.7 indicates the register functions in idle mode.
Table 7.7 Register Functions in Idle Mode
Register
23
MAR
23 7
All 1s IOAR
15
ETCR
Legend
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or
destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all
1s. MAR and IOAR are not incremented or decremented.
Figure 7.4 illustrates how idle mode operates.
Rev. 4.00 Jan 26, 2006 page 234 of 938
REJ09B0276-0400
Function
Activated by
SCI 0 Receive-
Data-Full
Interrupt or by
A/D Converter
Conversion- Other
End Interrupt Activation
Destination Source
0
address address
register register
Source Destination
0
address address
register register
Transfer counter
0
Initial Setting Operation
Destination or Held fixed
source address
Source or Held fixed
destination
address
Number of Decremented
transfers once per
transfer until
H'0000 is
reached and
transfer ends