Page 1 Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself.
Page 2 H8/300 Programming Manual...
Page 3: Table Of Contents
Contents Section 1. CPU....................1.1 General CPU Architecture....................2 1.2 Registers .......................... 5 1.3 Instructions ........................8 Section 2. Instruction Set ....................32 ADD (ADD binary) (byte) ....................37 ADD (ADD binary) (word) ..................... 38 ADDS (ADD with Sign extension) ................. 39 ADDX (ADD with eXtend carry) ...................
Page 4 INC (INCrement) ......................78 JMP (JuMP)........................79 JSR (Jump to SubRoutine) ....................80 LDC (LoaD to Control register) ..................81 MOV(MOVe data) (byte) ....................82 MOV(MOVe data) (word)....................83 MOV(MOVe data) (byte) ....................84 MOV(MOVe data) (word)....................85 MOV(MOVe data) (byte) ....................86 MOV(MOVe data) (word)....................
Page 5 XORC (eXclusive OR Control register) .................116 Appendix A. Operation Code Map ................117 Appendix B. Instruction Set List ..................118 Appendix C. Number of Execution States ..............124...
Page 6 Preface The H8/300 CPU forms the common core of all chips in the H8/300 Series. Featuring a Hitachi-original, high-speed, RISC-like architecture, it has eight 16-bit (or sixteen 8-bit) general registers and a concise, optimized instruction set. This manual gives detailed descriptions of the H8/300 instructions. The descriptions apply to all chips in the H8/300 Series.
Page 7: Section 1. Cpu
Section 1. CPU This document is a reference manual for programming the H8/300, a high-speed central processing unit with a Hitachi-original RISC-like architecture that is employed as a CPU core in a series of low-cost single-chip microcomputers intended for applications ranging from smart cards to office and factory automation.
Page 8: 1.1 General Cpu Architecture
1.1 General CPU Architecture 1.1.1 Features Table 1-1 summarizes the CPU architecture. Figures 1-1 and 1-2 show how data are stored in registers and memory. Table 1-1. CPU Architecture Item Description Address space 64K bytes, H'0000 to H'FFFF Data types Bit, 4-bit (packed BCD), byte, word (2 bytes) General registers Sixteen 8-bit general registers (R0H, R0L, ..., R7H, R7L),...
Page 9 • The DAA and DAS instruction perform decimal arithmetic adjustments on byte data in packed BCD form. Each 4-bit of the byte is treated as a decimal digit. The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and •...
Page 10 1.1.3 Address Space The H8/300 CPU supports a 64K-byte address space. The memory map differs depending on the particular chip in the H8/300 Series and its operating mode. See the Hardware Manual of the chip for details.
Page 11: 1.2 Registers
1.2 Registers Figure 1-3 shows the register structure of the H8/300 CPU. There are sixteen 8-bit general registers (R0H, R0L, ..., R7H, R7L), which can also be accessed as eight 16-bit registers (R0 to R7). There are two control registers: the 16-bit program counter (PC) and the 8-bit condition code register (CCR).
Page 12 1.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high (R0H to R7H) and low (R0L to R7L) bytes can be accessed separately as 8-bit registers.
Page 13 Initial value Read/Write Undetermined Bit 7—Interrupt Mask Bit (I): When this bit is set to "1," all interrupts except NMI are masked. This bit is set to "1" automatically by a reset and at the start of interrupt handling. Bits 6 and 4—User Bits (U): These bits can be written and read by software for its own purposes.
Page 14: 1.3 Instructions
In particular, the stack pointer (R7) is not initialized. To prevent program crashes the stack pointer should be initialized by software, by the first instruction executed after a reset. 1.3 Instructions Features: • The H8/300 has a concise set of 57 RISC-like instructions. •...
Page 15 1.3.2 Instruction Functions Tables 1-3 to 1-10 give brief descriptions of the instructions in each functional group. The following notation is used. Notation General register (destination) General register (source) General register (EAd) Destination operand (EAs) Source operand CCR Condition code register N (negative) bit of CCR Z (zero) bit of CCR V (overflow) bit of CCR...
Page 16 Table 1-3. Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:8 or #xx:16, @–Rn, and @Rn+ addressing modes are available for byte or word data.
Page 17 Table 1-4. Arithmetic Instructions Instruction Size* Function Rd ± Rs → Rd, Rd + #Imm → Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register. Word data can be added or subtracted only when both words are in general registers.
Page 18 Table 1-5. Logic Operation Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #Imm → Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #Imm → Rd Performs a logical OR operation on a general register and another general register or immediate data.
Page 19 Table 1-7. Bit-Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory to “1.” The bit is specified by a bit number, given in 3-bit immediate data or the lower three bits of a general register.
Page 20 Table 1-7. Bit-Manipulation Instructions (Cont.) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR Exclusive-ORs the C flag with a specified bit in a general register or memory. C ⊕ [¬ (<bit-No.> of <EAd>)] → C BIXOR Exclusive-ORs the C flag with the inverse of a specified bit in a general register or memory.
Page 21 Table 1-8. Branching Instructions Instruction Size Function — Branches if condition cc is true. Mnemonic cc Field Description Condition 0 0 0 0 Always (True) Always BRA (BT) 0 0 0 1 Never (False) Never BRN (BF) C ∨ Z = 0 0 0 1 0 High C ∨...
Page 22 Table 1-9. System Control Instructions Instruction Size* Function — Returns from an exception-handling routine. — Causes a transition to the power-down state. SLEEP Rs → CCR, #Imm → CCR Moves immediate data or general register contents to the condition code register. CCR →...
Page 23 Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are read- modify-write instructions. They read a byte of data, modify one bit in the byte, then write the byte back. Care is required when these instructions are applied to registers with write-only bits and to the I/O port registers.
Page 24 Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F. Next the CPU clears bit 0 of the read data, changing the value to H'FE. Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.
Page 25 After Execution of BSET Instruction Input/output Input Input Output Output Output Output Output Output Pin state High High Pull-up Explanation: To execute the BSET instruction, the CPU begins by reading port 4. Since P4 and P4 are input pins, the CPU reads the level of these pins directly, not the value in the data register.
Page 26 Input/output Input Input Output Output Output Output Output Output Pin state High Pull-up RAM0 Execution of BSET Instruction ;set bit 0 in DR work area (RAM0) BSET @RAM0 After Execution of BSET Instruction ;get value in work area (RAM0) MOV.B @RAM0 @PORT4 ;write value to DR MOV.B...
Page 27 1.3.3 Machine-Language Coding Rm → Rn Rn → @Rm, or @Rm → @(d:16, Rm) → Rn, or disp. Rn → @(d:16, Rm) @Rm+ → Rn, or Rn → @–Rm @aa:8 → Rn, or Rn → @aa:8 abs. @aa:16 → Rn, or abs.
Page 28 ADD, SUB, CMP (Rm) ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT MULXU, DIVXU ADD, ADDX, SUBX, CMP (#xx:8) AND, OR, XOR (Rm) AND, OR, XOR (#xx:8) SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR Notation Operation field r m , r n : Register field IMM:...
Page 29 BSET, BCLR, BNOT, BTST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm) Operand: register indirect (@Rn) 0 0 0 0 0 0 0 0 Bit No.: immediate (#xx:3) 0 0 0 0 Operand: register indirect (@Rn) 0 0 0 0 Bit No.: register direct (Rm)
Page 30 BIAND, BIOR, BIXOR, BILD, BIST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) 0 0 0 0 0 0 0 0 Bit No.: immediate (#xx:3) abs. Operand: absolute (@aa:8) 0 0 0 0 Bit No.: immediate (#xx:3) Notation Operation field r m , r n :...
Page 31 disp. 0 0 0 0 JMP (@Rm) JMP (@aa:16) abs. abs. JMP (@@aa:8) disp. 0 0 0 0 JSR (@Rm) JSR (@aa:16) abs. abs. JSR (@@aa:8) Notation Operation field Condition field r m : Register field disp.: Displacement abs.: Absolute address Figure 1-8.
Page 32 RTE, SLEEP, NOP LDC, STC (Rn) ANDC, ORC, XORC, LDC (#xx:8) Notation Operation field r n : Register field IMM: Immediate data Figure 1-9. Machine-Language Coding of System Control Instructions EEPMOV Figure 1-10. Machine-Language Coding of Block Data Transfer Instruction...
Page 33 1.3.4 Addressing Modes and Effective Address Calculation Table 1-11 lists the eight addressing modes and their assembly-language notation. Each instruction can use a specific subset of these addressing modes. Table 1-11. Addressing Modes Mode Notation Register direct Register indirect Register indirect with 16-bit displacement @(d:16, Rn) Register indirect with post-increment @Rn+...
Page 34 word operand. For a word operand, the original contents of the 16-bit general register must be even. • Register indirect with pre-decrement—@–Rn The @–Rn mode is used with MOV instructions that store registers contents to memory. It is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is decremented before the operand is accessed.
Page 35 Calculation of Effective Address: Table 1-12 shows how the H8/300 calculates effective addresses in each addressing mode. Arithmetic, logic, and shift instructions use register direct addressing (1). The ADD.B, ADDX, SUBX, CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6).
Page 36 Table 1-12, Effective Address Calculation (2) Addressing mode, Effective address Effective instruction format calculation address Register indirect with displacement @(d:16, Rn) 16-bit register contents 16-bit register contents 16-bit displacement Operand address is sum of register contents and disp displacement 16-bit register contents 16-bit displacement Register indirect with pre-decrement 16-bit register contents...
Page 37 Table 1-12, Effective Address Calculation (3) Addressing mode, Effective address Effective instruction format calculation address Absolute address None @aa:8 H'FF Operand address is in range from H'FF00 to H'FFFF Absolute address @aa:16 Arbitrary address PC-relative @(d:8, PC) PC contents PC contents Sign extension disp Destination address...
Page 38: Section 2. Instruction Set
Section 2. Instruction Set Section 2 gives full descriptions of all the H8/300 instructions, presenting them in alphabetic order. Each instruction is explained in a table like the following: ADD (ADD binary) (byte) <Operation> <Condition Code> Rd + (EAs) → Rd —...
Page 39 <Instruction Formats> Name: The full and mnemonic names of the instruction are given at the top of the page. Operation: Describes the instruction in symbolic notation. The following symbols are used. Symbol Meaning (EAs) Source operand (EAd) Destination operand Rs, Rd, Rn 8-bit or 16-bit general register (s—source;...
Page 40 The operand size is indicated by the letter B (byte) or W (word). The size is indicated explicitly in this manual, but for instructions that permit only one size, the size designation can be omitted in source-program coding. The abbreviation EAs or EAd (effective address of source or destination) is used for operands that permit more than one addressing mode.
Page 41 16-bit general registers are indicated by a 3-bit r , or r value. 8-bit registers are indicated by a 4-bit r , or r value. Address registers used in the @Rn, @(disp:16, Rn), @Rn+, and @–Rn addressing modes are always 16-bit registers. Data registers are 8-bit or 16-bit registers depending on the size of the operand.
Page 42 BLD #5, @H'FF02:8 Bit No. 5 1 0 1 0 0 1 1 0 H'FF02 Loaded to C (carry) flag in CCR The addressing mode and operand size apply to the register or memory byte containing the bit. Number of States Required for Execution: The number of states indicated is the number required when the instruction and any memory operands are located in on-chip ROM or RAM.
Page 43: Add (Add Binary) (Byte)
ADD (ADD binary) (byte) <Operation> <Condition Code> Rd + (EAs) → Rd — — — <Assembly-Language Format> ADD.B <EAs>, Rd I: Previous value remains unchanged. H: Set to "1" when there is a carry from bit <Examples> 3; otherwise cleared to "0." ADD.B R0H, R1H N: Set to "1"...
Page 44: Add (Add Binary) (Word)
ADD (ADD binary) (word) <Operation> <Condition Code> Rd + Rs → Rd — — — <Assembly-Language Format> ADD.W Rs, Rd I: Previous value remains unchanged. H: Set to "1" when there is a carry from bit <Examples> 11; otherwise cleared to "0." ADD.W R0, R1 N: Set to "1"...
Page 45: Adds (Add With Sign Extension)
ADDS (ADD with Sign extension) ADDS <Operation> <Condition Code> Rd + 1 → Rd Rd + 2 → Rd — — — — — — — — <Assembly-Language Format> I: Previous value remains unchanged. ADDS #1, Rd H: Previous value remains unchanged. ADDS #2, Rd N: Previous value remains unchanged.
Page 46: Addx (Add With Extend Carry)
ADDX (ADD with eXtend carry) ADDX <Operation> <Condition Code> Rd + (EAs) + C → Rd — — — <Assembly-Language Format> ADDX <EAs>, Rd I: Previous value remains unchanged. H: Set to "1" if there is a carry from bit 3; <Examples>...
Page 47: And (And Logical)
AND (AND logical) <Operation> <Condition Code> Rd ∧ (EAs) → Rd — — — — — <Assembly-Language Format> AND <EAs>, Rd I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Set to "1" when the result is negative; AND R6H, R6L otherwise cleared to "0."...
Page 48: Andc (And Control Register)
ANDC (AND Control register) ANDC <Operation> <Condition Code> CCR ∧ #IMM→ CCR <Assembly-Language Format> ANDC #xx:8, CCR I: ANDed with bit 7 of the immediate data. <Examples> H: ANDed with bit 5 of the immediate data. N: ANDed with bit 3 of the immediate data. ANDC #H'7F, CCR Z: ANDed with bit 2 of the immediate data.
Page 49: Band (Bit And)
BAND (Bit AND) BAND <Operation> <Condition Code> C ∧ (<Bit No.> of <EAd>) → C — — — — — — — <Assembly-Language Format> BAND #xx:3, <EAd> I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Previous value remains unchanged. BAND #0, R1L Z: Previous value remains unchanged.
Page 50: Bcc (Branch Conditionally)
Bcc (Branch conditionally) <Operation> <Condition Code> If cc then PC + d:8 → PC — — — — — — — — else next; I: Previous value remains unchanged. <Assembly-Language Format> H: Previous value remains unchanged. N: Previous value remains unchanged. Condition code field Z: Previous value remains unchanged.
Page 51 Bcc (Branch conditionally) <Description> If the specified condition is false, this instruction does nothing; the next instruction is executed. If the specified condition is true, a signed displacement is added to the address of the next instruction and execution branches to the resulting address. The displacement is a signed 8-bit value which must be even.
Page 52 Bcc (Branch conditionally) <Instruction Formats> Instruction code Adressing No . of Mnem. Operands states mode 1st byte 2nd byte 3rd byte 4th byte PC relative BRA (BT) disp. PC relative BRN (BF) disp. PC relative disp. PC relative disp. PC relative BCC (BHS) disp.
Page 53: Bclr (Bit Clear)
BCLR (Bit CLeaR) BCLR <Operation> <Condition Code> 0 → (<Bit No.> of <EAd>) — — — — — — — — <Assembly-Language Format> I: Previous value remains unchanged. BCLR #xx:3, <EAd> H: Previous value remains unchanged. BCLR Rn, <EAd> N: Previous value remains unchanged. Z: Previous value remains unchanged.
Page 54 BCLR (Bit CLeaR) BCLR <Instruction Formats> Instruction code Addressing No. of Mnem. Operands states mode 1st byte 2nd byte 3rd byte 4th byte Register direct BCLR #xx:3, Rd 0 IMM 0 rd 0 IMM Register indirect BCLR #xx:3,@Rd 0 IMM Absolute address BCLR #xx:3,@aa:8...
Page 55: Biand (Bit Invert And)
BIAND (Bit Invert AND) BIAND <Operation> <Condition Code> C ∧[ ¬ (<Bit No.> of <EAd>)] → C — — — — — — — — — — — — — — <Assembly-Language Format> BIAND #xx:3, <EAd> I: Previous value remains unchanged. H: Previous value remains unchanged.
Page 56: Bild (Bit Invert Load)
BILD (Bit Invert LoaD) BILD <Operation> <Condition Code> ¬ (<Bit No.> of <EAd>) → C — — — — — — — <Assembly-Language Format> BILD #xx:3, <EAd> I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Previous value remains unchanged. BILD #3, R4L Z: Previous value remains unchanged.
Page 57: Bior (Bit Invert Or)
BIOR (Bit Invert OR) BIOR <Operation> <Condition Code> C ∨ [¬ (<Bit No.> of <EAd>)] → — — — — — — — <Assembly-Language Format> BIOR #xx:3, <EAd> I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Previous value remains unchanged. BIOR #6, R1H Z: Previous value remains unchanged.
Page 58: Bist (Bit Invert Store)
BIST (Bit Invert STore) BIST <Operation> <Condition Code> ¬ C → (<Bit No.> of <EAd>) — — — — — — — — <Assembly-Language Format> BIST #xx:3, <EAd> I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Previous value remains unchanged. BIST #0, R0L Z: Previous value remains unchanged.
Page 59: Bixor (Bit Invert Exclusive Or)
BIXOR (Bit Invert eXclusive OR) BIXOR <Operation> <Condition Code> C ⊕ [¬ (<Bit No.> of <EAd>)] → C — — — — — — — <Assembly-Language Format> Previous value remains unchanged. BIXOR #xx:3, <EAd> H: Previous value remains unchanged. N: Previous value remains unchanged. <Examples>...
Page 60: Bld (Bit Load)
BLD (Bit LoaD) <Operation> <Condition Code> (<Bit No.> of <EAd>) → C — — — — — — — <Assembly-Language Format> BLD #xx:3, <EAd> I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Previous value remains unchanged. BLD #1, R3H Z: Previous value remains unchanged.
Page 61: Bnot (Bit Not)
BNOT (Bit NOT) BNOT <Operation> <Condition Code> ¬ (<Bit No.> of <EAd>) → (<Bit No.> of <EAd>) — — — — — — — — <Assembly-Language Format> I: Previous value remains unchanged. BNOT #xx:3, <EAd> H: Previous value remains unchanged. BNOT Rn, <EAd>...
Page 62 BNOT (Bit NOT) BNOT <Instruction Formats> Instruction code Addressing No. of Mnem. Operands states mode 1st byte 2nd byte 3rd byte 4th byte Register direct BNOT #xx:3, Rd 0 IMM 0 rd 0 IMM Register indirect BNOT #xx:3,@Rd 0 IMM Absolute address BNOT #xx:3,@aa:8...
Page 63: Bor (Bit Inclusive Or)
BOR (Bit inclusive OR) <Operation> <Condition Code> C ∨ (<Bit No.> of <EAd>) → C — — — — — — — <Assembly-Language Format> BOR #xx:3, <EAd> I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Previous value remains unchanged. BOR #5, R2H Z: Previous value remains unchanged.
Page 64 BOR (Bit inclusive OR) <Instruction Formats> Instruction code Addressing No. of Mnem. Operands mode states 1st byte 2nd byte 3rd byte 4th byte Register direct #xx:3, Rd 0 IMM rd 0 rd 4 0 IMM 0 Register indirect #xx:3,@Rd 4 0 IMM 0 Absolute address #xx:3,@aa:8...
Page 65: Bset (Bit Set)
BSET (Bit SET) BSET <Operation> <Condition Code> 1 → (<Bit No.> of <EAd>) — — — — — — — — <Assembly-Language Format> BSET #xx:3,<EAd> I: Previous value remains unchanged. BSET Rn,<EAd> H: Previous value remains unchanged. N: Previous value remains unchanged. <Examples>...
Page 66 BSET (Bit SET) BSET <Instruction Formats> Instruction code Addressing No. of Mnem. Operands states mode 1st byte 2nd byte 3rd byte 4th byte Register direct BSET #xx:3, Rd 0 IMM 0 rd 0 IMM Register indirect BSET #xx:3,@Rd 0 IMM Absolute address BSET #xx:3,@aa:8...
Page 67: Bsr (Branch To Subroutine)
BSR (Branch to SubRoutine) <Operation> <Condition Code> PC → @–SP PC + d:8 → PC — — — — — — — — <Assembly-Language Format> I: Previous value remains unchanged. BSR d:8 H: Previous value remains unchanged. N: Previous value remains unchanged. <Examples>...
Page 68: Bst (Bit Store)
BST (Bit STore) <Operation> <Condition Code> C → (<Bit No.> of <EAd>) — — — — — — — — <Assembly-Language Format> BST #xx:3, <EAd> I: Previous value remains unchanged. <Examples> H: Previous value remains unchanged. N: Previous value remains unchanged. BST #7, R4L Z: Previous value remains unchanged.
Page 69: Btst (Bit Test)
BTST (Bit TeST) BTST <Operation> <Condition Code> ¬ (<Bit No.> of <EAd>) → Z — — — — — — — <Assembly-Language Format> BTST #xx:3, <EAd> I: Previous value remains unchanged. BTST Rn, <EAd> H: Previous value remains unchanged. N: Previous value remains unchanged. <Examples>...
Page 70 BTST (Bit TeST) BTST <Instruction Formats> Instruction code Addressing No. of Mnem. Operands states mode 1st byte 2nd byte 3rd byte 4th byte Register direct BTST #xx:3, Rd 0 IMM 0 rd 0 IMM Register indirect BTST #xx:3,@Rd 0 IMM Absolute address BTST #xx:3,@aa:8...
Page 71: Bxor (Bit Exclusive Or)
BXOR (Bit eXclusive OR) BXOR <Operation> <Condition Code> C ⊕ (<Bit No.> of <EAd>) → C — — — — — — — <Assembly-Language Format> BXOR #xx:3, <EAd> I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Previous value remains unchanged. BXOR #4, R6H Z: Previous value remains unchanged.
Page 72 BXOR (Bit eXclusive OR) BXOR <Instruction Formats> Instruction code Addressing No. of Mnem. Operands mode states 1st byte 2nd byte 3rd byte 4th byte Register direct BXOR #xx:3, Rd 0 IMM 0 rd 5 0 IMM 0 Register indirect BXOR #xx:3,@Rd 5 0 IMM 0 Absolute address BXOR...
Page 73: Cmp (Compare) (Byte)
CMP (CoMPare) (byte) <Operation> <Condition Code> Rd – (EAs); set condition code — — — <Assembly-Language Format> CMP.B <EAs>, Rd I: Previous value remains unchanged. H: Set to "1" when there is a borrow from <Examples> bit 3; otherwise cleared to "0." CMP.B #H'E5, R1H N: Set to "1"...
Page 74: Cmp (Compare) (Word)
CMP (CoMPare) (word) <Operation> <Condition Code> Rd – Rs; set condition code — — — <Assembly-Language Format> CMP.W Rs, Rd I: Previous value remains unchanged. H: Set to "1" when there is a borrow from <Examples> bit 11; otherwise cleared to "0." CMP.W R5, R6 N: Set to "1"...
Page 75: Daa (Decimal Adjust Add)
DAA (Decimal Adjust Add) <Operation> <Condition Code> Rd (decimal adjust) → Rd — — — <Assembly-Language Format> DAA Rd I: Previous value remains unchanged. H: Unpredictable. <Examples> N: Set to "1" if the adjusted result is DAA R5L negative; otherwise cleared to "0." Z: Set to "1"...
Page 76 DAA (Decimal Adjust Add) <Instruction Formats> Instruction code Addressing No. of Mnem. Operands mode states 1st byte 2nd byte 3rd byte 4th byte Register direct...
Page 77: Das (Decimal Adjust Subtract)
DAS (Decimal Adjust Subtract) <Operation> <Condition Code> Rd (decimal adjust) → Rd — — — — <Assembly-Language Format> DAS Rd I: Previous value remains unchanged. H: Unpredictable. <Examples> N: Set to "1" if the adjusted result is DAS R0H negative; otherwise cleared to "0." Z: Set to "1"...
Page 78 DAS (Decimal Adjust Subtract) <Instruction Formats> Instruction code Addressing No. of Mnem. Operands mode states 1st byte 2nd byte 3rd byte 4th byte Register direct...
Page 79: Dec (Decrement)
DEC (DECrement) <Operation> <Condition Code> Rd – 1 → Rd — — — — — <Assembly-Language Format> DEC Rd I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Set to "1" if the result is negative; DEC R2L otherwise cleared to "0."...
Page 80: Divxu (Divide Extend As Unsigned)
DIVXU (DIVide eXtend as Unsigned) DIVXU <Operation> <Condition Code> Rd ÷ Rs → Rd — — — — — — <Assembly-Language Format> DIVXU Rs, Rd I: Previous value remains unchanged. <Examples> H: Previous value remains unchanged. N: Set to "1" if the divisor is negative; DIVXU R0L, R1 otherwise cleared to "0."...
Page 81 DIVXU (DIVide eXtend as Unsigned) DIVXU <Note: DIVXU Overflow> Since the DIVXU instruction performs 16-bit ÷ 8-bit → 8-bit division, an overflow will occur if the divisor byte is equal to or less than the upper byte of the dividend. For example, H'FFFF ÷...
Page 82: Eepmov (Move Data To Eeprom)
At the end of this instruction, R4L contains H'00. R5 and R6 contain the last transfer address Chips in the H8/300 Series having large on-chip EEPROM memories use this instruction to write data in the EEPROM. For details, see the hardware manual for the particular chip.
Page 83 EEPMOV (MOV data to EEPROM) EEPMOV <Instruction Formats> Instruction code Addressing No. of Mnem. Operands mode states 1st byte 2nd byte 3rd byte 4th byte EEPMOV 8+4n* * n is the initial value in R4L (0 ≤ n ≤ 255). Although n bytes of data are transferred, memory is accessed 2(n+1) times, requiring 4(n+1) states.
Page 84: Inc (Increment)
INC (INCrement) <Operation> <Condition Code> Rd + 1 → Rd — — — — — <Assembly-Language Format> INC Rd I: Previous value remains unchanged. <Examples> H: Previous value remains unchanged. N: Set to "1" if the result is negative; INC R3L otherwise cleared to "0."...
Page 85: Jmp (Jump)
JMP (JuMP) <Operation> <Condition Code> (EAd) → PC — — — — — — — — <Assembly-Language Format> JMP <EA> I: Previous value remains unchanged. <Examples> H: Previous value remains unchanged. JMP @R6 N: Previous value remains unchanged. JMP @H'2000 Z: Previous value remains unchanged.
Page 86: Jsr (Jump To Subroutine)
JSR (Jump to SubRoutine) <Operation> <Condition Code> PC → @-SP (EAd) → PC — — — — — — — — <Assembly-Language Format> I: Previous value remains unchanged. JSR <EA> H: Previous value remains unchanged. N: Previous value remains unchanged. <Examples>...
Page 87: Ldc (Load To Control Register)
LDC (LoaD to Control register) <Operation> <Condition Code> (EAs) → CCR <Assembly-Language Format> LDC <EAs>, CCR I: Loaded from the source operand. H: Loaded from the source operand. <Examples> N: Loaded from the source operand. LDC #H'80, CCR Z: Loaded from the source operand. LDC R4H, CCR V: Loaded from the source operand.
Page 88: Mov(Move Data) (Byte)
MOV (MOVe data) (byte) <Operation> <Condition Code> Rs → Rd — — — — — <Assembly-Language Format> I: Previous value remains unchanged. MOV.B Rs, Rd H: Previous value remains unchanged. N: Set to "1" if the data value is negative; <Examples>...
Page 89: Mov(Move Data) (Word)
MOV (MOVe data) (word) <Operation> <Condition Code> Rs → Rd — — — — — <Assembly-Language Format> I: Previous value remains unchanged. MOV.W Rs, Rd H: Previous value remains unchanged. N: Set to "1" if the data value is negative; <Examples>...
Page 90: Mov(Move Data) (Byte)
MOV (MOVe data) (byte) <Operation> <Condition Code> (EAs) → Rd — — — — — <Assembly-Language Format> MOV.B <EAs>, Rd I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Set to "1" if the data value is negative; MOV.B @R1, R2H otherwise cleared to "0."...
Page 91: Mov(Move Data) (Word)
MOV (MOVe data) (word) <Operation> <Condition Code> (EAs) → Rd — — — — — <Assembly-Language Format> MOV.W <EAs>, Rd I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Set to "1" if the data value is negative; MOV.W @R3, R4 otherwise cleared to "0."...
Page 92: Mov(Move Data) (Byte)
MOV (MOVe data) (byte) <Operation> <Condition Code> Rs → (EAd) — — — — — <Assembly-Language Format> I: Previous value remains unchanged. MOV.B Rs, <EAd> H: Previous value remains unchanged. N: Set to "1" if the data value is negative; <Examples>...
Page 93: Mov(Move Data) (Word)
MOV (MOVe data) (word) <Operation> <Condition Code> Rs → (EAd) — — — — — <Assembly-Language Format> MOV.W Rs, <EAd> I: Previous value remains unchanged. <Examples> H: Previous value remains unchanged. N: Set to "1" if the data value is negative; MOV.W R3, @R4 otherwise cleared to "0."...
Page 94: Movfpe (Move Data From Peripheral With E Clock)
MOVFPE (MOVe data From Peripheral with E clock) MOVFPE <Operation> <Condition Code> synchronization with the E clock (EAs) → Rd — — — — — <Assembly-Language Format> MOVFPE @aa:16, Rd I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples>...
Page 95: Movtpe (Move Data To Peripheral With E Clock)
MOVTPE (MOVe data To Peripheral with E clock) MOVTPE <Operation> <Condition Code> synchronization with the E clock Rs → (EAd) — — — — — <Assembly-Language Format> MOVTPE Rs, @aa:16 I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples>...
Page 96: Mulxu (Multiply Extend As Unsigned)
MULXU (MULtiply eXtend as Unsigned) MULXU <Operation> <Condition Code> Rd × Rs → Rd — — — — — — — — <Assembly-Language Format> MULXU Rs, Rd I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Previous value remains unchanged. Z: Previous value remains unchanged.
Page 97: Neg (Negate)
NEG (NEGate) <Operation> <Condition Code> 0 – Rd → Rd — — — <Assembly-Language Format> NEG Rd I: Previous value remains unchanged. H: Set to "1" when there is a borrow from <Examples> bit 3; otherwise cleared to "0." N: Set to "1" when the result is negative; NEG R0L otherwise cleared to "0."...
Page 98: Nop (No Operation)
NOP (No OPeration) <Operation> <Condition Code> PC + 2 → PC — — — — — — — — <Assembly-Language Format> I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Previous value remains unchanged. Z: Previous value remains unchanged. V: Previous value remains unchanged.
Page 99: Not (Not = Logical Complement)
NOT (NOT = logical complement) <Operation> <Condition Code> ¬ Rd → Rd — — — — — <Assembly-Language Format> NOT Rd I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Set to "1" if the result is negative; NOT R4L otherwise cleared to "0."...
Page 100: Or (Inclusive Or Logical)
OR (inclusive OR logical) <Operation> <Condition Code> Rd ∨ (EAs) → Rd — — — — — <Assembly-Language Format> I: Previous value remains unchanged. OR <EAs>, Rd H: Previous value remains unchanged. N: Set to "1" when the result is negative; <Examples>...
Page 101: Orc (Inclusive Or Control Register)
ORC (inclusive OR Control register) <Operation> <Condition Code> CCR ∨ #IMM → CCR <Assembly-Language Format> I: ORed with bit 7 of the immediate data. ORC #xx:8, CCR H: ORed with bit 5 of the immediate data. N: ORed with bit 3 of the immediate data. <Examples>...
Page 102: Pop (Pop Data)
POP (POP data) <Operation> <Condition Code> @SP+ → Rn — — — — — <Assembly-Language Format> POP Rn I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Set to "1" if the data value is negative; POP R1 otherwise cleared to "0."...
Page 103: Push (Push Data)
PUSH (PUSH data) PUSH <Operation> <Condition Code> Rn → @–SP — — — — — <Assembly-Language Format> PUSH Rn I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Set to "1" if the data value is negative; PUSH R2 otherwise cleared to "0."...
Page 104: Rotl (Rotate Left)
ROTL (ROTate Left) ROTL <Operation> <Condition Code> Rd (rotated left) → Rd — — — — <Assembly-Language Format> ROTL Rd I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Set to "1" if the result is negative; ROTL R2L otherwise cleared to "0."...
Page 105: Rotr (Rotate Right)
ROTR (ROTate Right) ROTR <Operation> <Condition Code> Rd (rotated right) → Rd — — — — <Assembly-Language Format> ROTR Rd I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Set to "1" if the result is negative; ROTR R5L otherwise cleared to "0."...
Page 106: Rotxl (Rotate With Extend Carry Left)
ROTXL (ROTate with eXtend carry Left) ROTXL <Operation> <Condition Code> Rd (rotated with carry left) → Rd — — — — <Assembly-Language Format> ROTXL Rd I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Set to "1" if the result is negative; ROTXL R1H otherwise cleared to "0."...
Page 107: Rotxr (Rotate With Extend Carry Right)
ROTXR (ROTate with eXtend carry Right) ROTXR <Operation> <Condition Code> Rd (rotated with carry right) → Rd — — — — <Assembly-Language Format> ROTXR Rd I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Set to "1" if the result is negative; ROTXR R5L otherwise cleared to "0."...
Page 108: Rte (Return From Exception)
RTE (ReTurn from Exception) <Operation> <Condition Code> @SP+ → CCR @SP+ → PC <Assembly-Language Format> I: Restored from stack. H: Restored from stack. N: Restored from stack. <Examples> Z: Restored from stack. V: Restored from stack. C: Restored from stack. <Operand Size>...
Page 109: Rts (Return From Subroutine)
RTS (ReTurn from Subroutine) <Operation> <Condition Code> @SP+ → PC — — — — — — — — <Assembly-Language Format> I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Previous value remains unchanged. Z: Previous value remains unchanged. V: Previous value remains unchanged.
Page 110: Shal (Shift Arithmetic Left)
SHAL (SHift Arithmetic Left) SHAL <Operation> <Condition Code> Rd (shifted arithmetic left ) → Rd — — — — <Assembly-Language Format> SHAL Rd I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Set to "1" if the result is negative; SHAL R5H otherwise cleared to "0."...
Page 111: Shar (Shift Arithmetic Right)
SHAR (SHift Arithmetic Right) SHAR <Operation> <Condition Code> Rd (shifted arithmetic right ) → Rd — — — — <Assembly-Language Format> SHAR Rd I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Set to "1" if the result is negative; SHAR R5H otherwise cleared to "0."...
Page 112: Shll (Shift Logical Left)
SHLL (SHift Logical Left) SHLL <Operation> <Condition Code> Rd (shifted logical left ) → Rd — — — — <Assembly-Language Format> SHLL Rd I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Set to "1" if the result is negative; SHLL R2L otherwise cleared to "0."...
Page 113: Shlr (Shift Logical Right)
SHLR (SHift Logical Right) SHLR <Operation> <Condition Code> Rd (shifted logical right ) → Rd — — — — <Assembly-Language Format> SHLR Rd I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Set to "1" if the result is negative; SHLR R3L otherwise cleared to "0."...
Page 114: Sleep (Sleep)
SLEEP (SLEEP) SLEEP <Operation> <Condition Code Program execution state → power- down mode — — — — — — — — <Assembly-Language Format> I: Previous value remains unchanged. SLEEP H: Previous value remains unchanged. N: Previous value remains unchanged. <Examples> Z: Previous value remains unchanged.
Page 115: Stc (Store From Control Register)
STC (STore from Control register) <Operation> <Condition Code> CCR → Rd — — — — — — — — <Assembly-Language Format> STC CCR, Rd I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Previous value remains unchanged. STC CCR, R6H Z: Previous value remains unchanged.
Page 116: Sub (Subtract Binary) (Byte)
SUB (SUBtract binary) (byte) <Operation> <Condition Code> Rd – Rs → Rd — — — <Assembly-Language Format> SUB.B Rs, Rd I: Previous value remains unchanged. H: Set to "1" when there is a borrow from <Examples> bit 3; otherwise cleared to "0." SUB.B R0L, R2L N: Set to "1"...
Page 117 SUB (SUBtract binary) (byte) <Instruction Formats> Instruction code Addressing No. of Mnem. Operands mode states 1st byte 2nd byte 3rd byte 4th byte Register direct SUB.B Rs, Rd...
Page 118: Sub (Subtract Binary) (Word)
SUB (SUBtract binary) (word) <Operation> <Condition Code> Rd - Rs — — — <Assembly-Language Format> SUB.W Rs, Rd I: Previous value remains unchanged. H: Set to "1" when there is a borrow from <Examples> bit 11; otherwise cleared to "0." SUB.W R0, R1 N: Set to "1"...
Page 119: Subs (Subtract With Sign Extension)
SUBS (SUBtract with Sign extension) SUBS <Operation> <Condition Code> Rd – 1 → Rd Rd – 2 → Rd — — — — — — — — <Assembly-Language Format> I: Previous value remains unchanged. SUBS #1, Rd H: Previous value remains unchanged. SUBS #2, Rd N: Previous value remains unchanged.
Page 120: Subx (Subtract With Extend Carry)
SUBX (SUBtract with eXtend carry) SUBX <Operation> <Condition Code> Rd – (EAs) – C → Rd — — — <Assembly-Language Format> SUBX <EAs>, Rd I: Previous value remains unchanged. H: Set to "1" if there is a borrow from bit 3; <Examples>...
Page 121: Xor (Exclusive Or Logical)
XOR (eXclusive OR logical) <Operation> <Condition Code> Rd ⊕ (EAs) → Rd — — — — — <Assembly-Language Format> XOR <EAs>, Rd I: Previous value remains unchanged. H: Previous value remains unchanged. <Examples> N: Set to "1" when the result is negative; XOR R0H, R1H otherwise cleared to "0."...
Page 122: Xorc (Exclusive Or Control Register)
XORC (eXclusive OR Control register) XORC <Operation> <Condition Code> CCR ⊕ #IMM → CCR <Assembly-Language Format> XORC #xx:8, CCR I: Exclusive-ORed with bit 7 of the immediate data. <Examples> H: Exclusive-ORed with bit 5 of the XORC #H'50, CCR immediate data. N: Exclusive-ORed with bit 3 of the <Operand Size>...
Page 123: Appendix A. Operation Code Map
Appendix A. Operation Code Map This table is a map of the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Some pairs of instructions have identical first bytes. These instructions are differentiated by the first bit of the second byte (bit 7 of the first instruction word).
Page 124: Appendix B. Instruction Set List
Appendix B. Instruction Set List Addressing mode/ instruction length Mnemonic Operation Condition code H N Z #xx:8 → Rd8 ◊ ◊ 0 MOV.B #xx:8,Rd – – – Rs8 → Rd8 ◊ ◊ 0 MOV.B Rs,Rd – – – @Rs16 → Rd8 ◊...
Page 125 Appendix B. Instruction Set List (cont.) Addressing mode/ instruction length Mnemonic Operation Condition code H N Z V C Rd8+#xx:8 → Rd8 ◊ ◊ ◊ ◊ ◊ ADD.B #xx:8,Rd – Rd8+Rs8 → Rd8 ◊ ◊ ◊ ◊ ◊ ADD.B Rs,Rd –...
Page 126 Appendix B. Instruction Set List (cont.) Addressing mode/ instruction length Mnemonic Operation Condition code H N Z V C ◊ ◊ ◊ ◊ SHAL.B Rd – – ◊ ◊ ◊ SHAR.B Rd – – ◊ ◊ ◊ SHLL.B Rd – –...
Page 127 Appendix B. Instruction Set List (cont.) Addressing mode/ instruction length Mnemonic Operation Condition code H N Z V C (Rn8 of Rd8) ← (Rn8 of Rd8) BNOT Rn,Rd – – – – – – ← BNOT Rn,@Rd – – – –...
Page 128 Appendix B. Instruction Set List (cont.) Addressing mode/ instruction length Mnemonic Operation Condition code Branching condition H N Z V C C∨(#xx:3 of @Rd16) → C ◊ BIOR #xx:3,@Rd – – – – – C∨(#xx:3 of @aa:8) → C ◊ BIOR #xx:3, @aa:8 –...
Page 129 Appendix B. Instruction Set List (cont.) Addressing mode/ instruction length Mnemonic Operation Condition code Z V C SP–2 → SP JSR @Rn – – – – – – – PC → @SP PC ← Rn16 SP–2 → SP JSR @aa:16 –...
Page 130: Appendix C. Number Of Execution States
Appendix C. Number of Execution States The tables in this appendix can be used to calculate the number of states required for instruction execution. Table C-1 indicates the number of states required for each cycle (instruction fetch, branch address read, stack operation, byte data access, word data access, internal operation).
Page 131 Table C-1. Number of States Taken by Each Cycle in Instruction Execution Execution Status Access Location (instruction cycle) On-Chip Memory On-Chip Reg. Field External Memory Instruction fetch Branch address read 6 + 2m Stack operation Byte data access 3 + m Word data access 6 + 2m Internal operation...
Page 132 Table C-2. Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Word Data Internal Instruction Mnemonic Fetch Addr. Read Operation Access Access Operation ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDS.W #1/2, Rd ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd AND.B #xx:8, Rd AND.B Rs, Rd...
Page 133 Instruction Branch Stack Byte Data Word Data Internal Instruction Mnemonic Fetch Addr. Read Operation Access Access Operation BCLR BCLR Rn, @Rd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 BILD BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BIOR BIOR #xx:3, Rd...
Page 134 Instruction Branch Stack Byte Data Word Data Internal Instruction Mnemonic Fetch Addr. Read Operation Access Access Operation BSET BSET Rn, @aa:8 BSR d:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BTST BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8...
Page 135 Instruction Branch Stack Byte Data Word Data Internal Instruction Mnemonic Fetch Addr. Read Operation Access Access Operation MOV.B @(d:16, Rs), Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @–Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd...
Page 136 Instruction Branch Stack Byte Data Word Data Internal Instruction Mnemonic Fetch Addr. Read Operation Access Access Operation SHAL SHAL.B Rd SHAR SHAR.B Rd SHLL SHLL.B Rd SHLR SHLR.B Rd SLEEP SLEEP STC CCR, Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBS SUBS.W #1/2, Rd SUBX...

Renesas H8/300 Series Programming Manual

Section 1. CPU

Section 2. Instruction Set

Appendix A. Operation Code Map

Appendix B. Instruction Set List

Appendix C. Number of Execution States

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Summary of Contents for Renesas H8/300 Series

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