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Section 6 Bus Controller
(UCAS /LCAS)
Read access
(UCAS /LCAS)
Write access
Note: n = 2 to 5
Figure 6.20 Example of Wait State Insertion Timing (CSEL = 0)
Byte Access Control and CAS
6.5.9
When an access is made to DRAM space designated as a 16-bit-access area in ABWCR, column
address strobes (UCAS and LCAS) corresponding to the upper and lower halves of the external
data bus are output. In the case of × 16-bit organization DRAM, the 2-CAS type can be connected.
Either PB4 and PB5, or HWR and LWR, can be used as the UCAS and LCAS output pins, the
selection being made with the CSEL bit in DRCRB. Table 6.8 shows the CSEL bit settings and
corresponding output pin selections.
Rev. 4.00 Jan 26, 2006 page 172 of 938
REJ09B0276-0400
T
p
φ
A
to A
23
0
AS
CSn(RAS)
PB
/PB
4
5
RD(WE)
D
to D
15
0
PB
/PB
4
5
RD(WE)
D
to D
15
0
CAS Output Pin
CAS
CAS
Tr
Trw
T
Tw
c1
Row
Column
High level
High level
Tw
T
c2
Read data
Write data
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